Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10233	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9074	1			T4	24		T5	7		T20	43
len_5001_7500	14660	1			T4	24		T5	13		T20	95
len_2501_5000	9237	1			T4	24		T5	3		T20	17
len_1025_2500	5404	1			T4	14		T5	3		T20	8
len_769_1024	6229	1			T4	2		T17	7		T18	28
len_513_768	6778	1			T4	3		T5	1		T17	7
len_257_512	21103	1			T4	2		T5	2		T17	7
len_0_256	256909	1			T4	211		T5	59		T6	70
len_keccak_block_sizes[72]	712	1			T4	2		T87	2		T156	2
len_keccak_block_sizes[104]	618	1			T4	2		T19	1		T87	2
len_keccak_block_sizes[136]	512	1			T157	3		T155	3		T158	2
len_keccak_block_sizes[144]	425	1			T72	1		T157	3		T155	3
len_keccak_block_sizes[168]	324	1			T22	1		T157	3		T155	3
len_1	751	1			T4	2		T17	1		T87	2
len_0	1259	1			T4	2		T5	2		T6	5