Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100286678	1			T1	5		T2	4		T56	8
all_pins[1]	100286678	1			T1	5		T2	4		T56	8
all_pins[2]	100286678	1			T1	5		T2	4		T56	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	249625359	1			T1	14		T2	12		T56	16
values[0x1]	51234675	1			T1	1		T56	8		T63	1
transitions[0x0=>0x1]	50815569	1			T1	1		T56	5		T63	1
transitions[0x1=>0x0]	50815593	1			T1	1		T56	5		T63	1

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99779103	1			T1	4		T2	4		T56	6
all_pins[0]	values[0x1]	507575	1			T1	1		T56	2		T124	2
all_pins[0]	transitions[0x0=>0x1]	214567	1			T1	1		T56	1		T124	1
all_pins[0]	transitions[0x1=>0x0]	50121545	1			T56	3		T63	1		T70	4
all_pins[1]	values[0x0]	49872125	1			T1	5		T2	4		T56	4
all_pins[1]	values[0x1]	50414553	1			T56	4		T63	1		T70	4
all_pins[1]	transitions[0x0=>0x1]	50290373	1			T56	2		T63	1		T70	3
all_pins[1]	transitions[0x1=>0x0]	188367	1			T64	1		T124	1		T125	1
all_pins[2]	values[0x0]	99974131	1			T1	5		T2	4		T56	6
all_pins[2]	values[0x1]	312547	1			T56	2		T64	1		T70	1
all_pins[2]	transitions[0x0=>0x1]	310629	1			T56	2		T64	1		T70	1
all_pins[2]	transitions[0x1=>0x0]	505681	1			T1	1		T56	2		T124	2