Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	646	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5666	1			T5	3		T17	4		T18	14
len_601_800	12854	1			T5	16		T17	8		T18	52
len_401_600	8701	1			T5	9		T17	6		T18	32
len_201_400	16388	1			T5	4		T17	4		T18	16
len_65_200	73557	1			T5	16		T6	37		T17	3
len_min_for_xof_require_squeeze	978	1			T20	1		T157	9		T155	10
len_keccak_block_sizes[72]	749	1			T11	2		T32	1		T33	1
len_keccak_block_sizes[104]	760	1			T11	2		T32	2		T157	9
len_keccak_block_sizes[136]	761	1			T157	9		T155	5		T159	9
len_keccak_block_sizes[144]	277	1			T20	1		T11	1		T155	5
len_keccak_block_sizes[168]	280	1			T11	1		T32	1		T36	1
len_datapath_width	14280	1			T5	11		T20	2		T21	3
len_2_63	213366	1			T4	310		T5	32		T6	33
len_1	65	1			T32	1		T160	1		T161	2