Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10892379 |
1 |
|
|
T4 |
3720 |
|
T5 |
7172 |
|
T6 |
2498 |
auto[1] |
10892059 |
1 |
|
|
T4 |
3720 |
|
T5 |
7172 |
|
T6 |
2498 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21545325 |
1 |
|
|
T4 |
7440 |
|
T5 |
14256 |
|
T6 |
4908 |
triple_byte_access |
79695 |
1 |
|
|
T5 |
22 |
|
T6 |
42 |
|
T17 |
18 |
halfword_access |
79828 |
1 |
|
|
T5 |
40 |
|
T6 |
22 |
|
T17 |
18 |
byte_access |
79590 |
1 |
|
|
T5 |
26 |
|
T6 |
24 |
|
T17 |
6 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10772822 |
1 |
|
|
T4 |
3720 |
|
T5 |
7128 |
|
T6 |
2454 |
auto[0] |
triple_byte_access |
39848 |
1 |
|
|
T5 |
11 |
|
T6 |
21 |
|
T17 |
9 |
auto[0] |
halfword_access |
39914 |
1 |
|
|
T5 |
20 |
|
T6 |
11 |
|
T17 |
9 |
auto[0] |
byte_access |
39795 |
1 |
|
|
T5 |
13 |
|
T6 |
12 |
|
T17 |
3 |
auto[1] |
word_access |
10772503 |
1 |
|
|
T4 |
3720 |
|
T5 |
7128 |
|
T6 |
2454 |
auto[1] |
triple_byte_access |
39847 |
1 |
|
|
T5 |
11 |
|
T6 |
21 |
|
T17 |
9 |
auto[1] |
halfword_access |
39914 |
1 |
|
|
T5 |
20 |
|
T6 |
11 |
|
T17 |
9 |
auto[1] |
byte_access |
39795 |
1 |
|
|
T5 |
13 |
|
T6 |
12 |
|
T17 |
3 |