Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 281 1 T1 4 T2 4 T56 7
all_values[1] 281 1 T1 4 T2 4 T56 7
all_values[2] 281 1 T1 4 T2 4 T56 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 464 1 T1 8 T2 8 T56 10
auto[1] 379 1 T1 4 T2 4 T56 11


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 354 1 T1 5 T2 9 T56 5
auto[1] 489 1 T1 7 T2 3 T56 16


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 505 1 T1 7 T2 9 T56 10
auto[1] 338 1 T1 5 T2 3 T56 11


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 64 1 T1 1 T2 1 T56 1
all_values[0] auto[0] auto[0] auto[1] 24 1 T124 2 T125 1 T140 1
all_values[0] auto[0] auto[1] auto[0] 57 1 T1 2 T2 2 T56 2
all_values[0] auto[0] auto[1] auto[1] 27 1 T128 1 T140 1 T154 1
all_values[0] auto[1] auto[0] auto[1] 68 1 T2 1 T56 2 T70 1
all_values[0] auto[1] auto[1] auto[1] 41 1 T1 1 T56 2 T64 1
all_values[1] auto[0] auto[0] auto[0] 65 1 T2 2 T63 2 T64 2
all_values[1] auto[0] auto[0] auto[1] 27 1 T1 2 T63 1 T64 1
all_values[1] auto[0] auto[1] auto[0] 53 1 T2 1 T56 1 T125 1
all_values[1] auto[0] auto[1] auto[1] 26 1 T56 2 T70 2 T124 2
all_values[1] auto[1] auto[0] auto[1] 50 1 T1 2 T2 1 T56 3
all_values[1] auto[1] auto[1] auto[1] 60 1 T56 1 T70 2 T124 3
all_values[2] auto[0] auto[0] auto[0] 65 1 T1 2 T2 2 T56 1
all_values[2] auto[0] auto[0] auto[1] 22 1 T56 1 T64 1 T124 1
all_values[2] auto[0] auto[1] auto[0] 50 1 T2 1 T70 2 T125 1
all_values[2] auto[0] auto[1] auto[1] 25 1 T56 2 T70 1 T153 1
all_values[2] auto[1] auto[0] auto[1] 79 1 T1 1 T2 1 T56 2
all_values[2] auto[1] auto[1] auto[1] 40 1 T1 1 T56 1 T140 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%