Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.01	98.38	93.15	99.93	94.55	96.04	98.89	98.17

Total test records in report: 1255

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html

T1251	/workspace/coverage/cover_reg_top/18.kmac_csr_rw.1507791764			Jan 10 01:10:53 PM PST 24	Jan 10 01:12:22 PM PST 24	43210099 ps
T1252	/workspace/coverage/cover_reg_top/17.kmac_tl_errors.1900508860			Jan 10 01:10:18 PM PST 24	Jan 10 01:11:35 PM PST 24	101237950 ps
T1253	/workspace/coverage/cover_reg_top/18.kmac_intr_test.4294787919			Jan 10 01:10:50 PM PST 24	Jan 10 01:12:15 PM PST 24	43563008 ps
T1254	/workspace/coverage/cover_reg_top/4.kmac_intr_test.3988616075			Jan 10 01:10:27 PM PST 24	Jan 10 01:11:45 PM PST 24	42917484 ps
T1255	/workspace/coverage/cover_reg_top/2.kmac_tl_errors.1467881957			Jan 10 01:10:14 PM PST 24	Jan 10 01:11:28 PM PST 24	40533169 ps

Test location	/workspace/coverage/default/48.kmac_app.1142028741
Short name	T10
Test name
Test status
Simulation time	44839535245 ps
CPU time	368.9 seconds
Started	Jan 10 12:52:44 PM PST 24
Finished	Jan 10 01:00:11 PM PST 24
Peak memory	254068 kb
Host	smart-1b3b7fb6-bf2a-4e3b-8c4a-1abcb193b6df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1142028741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1142028741 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_app/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_intr_test.4045816461
Short name	T1
Test name
Test status
Simulation time	19770682 ps
CPU time	0.75 seconds
Started	Jan 10 01:10:27 PM PST 24
Finished	Jan 10 01:11:45 PM PST 24
Peak memory	216680 kb
Host	smart-975021c9-41a7-4fae-9836-4fab01a6b9ac
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045816461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.4045816461 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.1438518290
Short name	T53
Test name
Test status
Simulation time	683066060 ps
CPU time	8.71 seconds
Started	Jan 10 01:10:26 PM PST 24
Finished	Jan 10 01:11:52 PM PST 24
Peak memory	217860 kb
Host	smart-ae9a76de-9865-4158-811d-48004e4b260e
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438518290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.1438518 290 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.1050674264
Short name	T114
Test name
Test status
Simulation time	534613710 ps
CPU time	3.13 seconds
Started	Jan 10 01:10:24 PM PST 24
Finished	Jan 10 01:11:45 PM PST 24
Peak memory	217844 kb
Host	smart-0e434322-8ae6-47b6-8aff-ed8df8ef663b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050674264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.1050 674264 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_intg_err/latest

Test location	/workspace/coverage/default/47.kmac_stress_all_with_rand_reset.4178959853
Short name	T72
Test name
Test status
Simulation time	73048776430 ps
CPU time	1560.58 seconds
Started	Jan 10 12:52:47 PM PST 24
Finished	Jan 10 01:20:11 PM PST 24
Peak memory	325800 kb
Host	smart-be37af2d-0c4e-479e-92c5-6dbe635d47b0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4178959853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all_with_rand_reset.4178959853 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.kmac_error.1270038327
Short name	T39
Test name
Test status
Simulation time	1267312819 ps
CPU time	92.82 seconds
Started	Jan 10 12:52:08 PM PST 24
Finished	Jan 10 12:55:00 PM PST 24
Peak memory	252140 kb
Host	smart-7a1bbda3-2be1-4adc-b12e-4ca75ee8ff28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1270038327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.1270038327 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_error/latest

Test location	/workspace/coverage/default/1.kmac_sec_cm.1968683820
Short name	T8
Test name
Test status
Simulation time	2442570254 ps
CPU time	35.65 seconds
Started	Jan 10 12:50:07 PM PST 24
Finished	Jan 10 12:52:23 PM PST 24
Peak memory	257308 kb
Host	smart-5dcc2d2c-0daf-4a24-b02a-fb3f30e47e49
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968683820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.1968683820 +enable_maski ng=1 +sw_key_masked=0
Directory	/workspace/1.kmac_sec_cm/latest

Test location	/workspace/coverage/default/34.kmac_stress_all.1850806301
Short name	T5
Test name
Test status
Simulation time	61335929396 ps
CPU time	508.4 seconds
Started	Jan 10 12:52:15 PM PST 24
Finished	Jan 10 01:01:59 PM PST 24
Peak memory	286416 kb
Host	smart-bfbe7b81-8300-461c-8bb1-73311abc272c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1850806301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.1850806301 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3561375457
Short name	T89
Test name
Test status
Simulation time	41290908 ps
CPU time	1.38 seconds
Started	Jan 10 01:10:34 PM PST 24
Finished	Jan 10 01:11:59 PM PST 24
Peak memory	218256 kb
Host	smart-7168ff5c-6cc1-462a-ad17-e0bea267da66
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561375457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg _errors.3561375457 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_shake_256.1080426059
Short name	T155
Test name
Test status
Simulation time	302521797009 ps
CPU time	5060.43 seconds
Started	Jan 10 12:50:32 PM PST 24
Finished	Jan 10 02:16:08 PM PST 24
Peak memory	582404 kb
Host	smart-6ca92968-7015-4014-8ec3-57a7e020dd40
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1080426059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.1080426059 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1066867317
Short name	T65
Test name
Test status
Simulation time	138003684 ps
CPU time	1.23 seconds
Started	Jan 10 01:10:43 PM PST 24
Finished	Jan 10 01:12:07 PM PST 24
Peak memory	218536 kb
Host	smart-ec1eaf97-5266-41fe-88e8-f6ccc5c89a24
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066867317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg _errors.1066867317 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/default/23.kmac_key_error.404826747
Short name	T26
Test name
Test status
Simulation time	807168339 ps
CPU time	4.72 seconds
Started	Jan 10 12:51:54 PM PST 24
Finished	Jan 10 12:53:20 PM PST 24
Peak memory	219232 kb
Host	smart-4ec0238a-101b-4dec-8bed-c88391630945
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=404826747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.404826747 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_key_error/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.4142037116
Short name	T121
Test name
Test status
Simulation time	420388789 ps
CPU time	2.96 seconds
Started	Jan 10 01:10:31 PM PST 24
Finished	Jan 10 01:11:56 PM PST 24
Peak memory	217764 kb
Host	smart-2ea77ad1-c981-43e4-82df-2046e81bf4b0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142037116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.4142 037116 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_intr_test.2490829789
Short name	T153
Test name
Test status
Simulation time	80256166 ps
CPU time	0.8 seconds
Started	Jan 10 01:10:22 PM PST 24
Finished	Jan 10 01:11:39 PM PST 24
Peak memory	217448 kb
Host	smart-06981088-d80d-4c1a-829b-629965eb0e20
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490829789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.2490829789 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.1960981756
Short name	T51
Test name
Test status
Simulation time	48513507 ps
CPU time	1.36 seconds
Started	Jan 10 01:10:17 PM PST 24
Finished	Jan 10 01:11:37 PM PST 24
Peak memory	217692 kb
Host	smart-8661d506-e73a-4f61-9fa5-4b1dd394db2b
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960981756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia l_access.1960981756 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_partial_access/latest

Test location	/workspace/coverage/default/4.kmac_entropy_ready_error.236055998
Short name	T640
Test name
Test status
Simulation time	6178140587 ps
CPU time	66.52 seconds
Started	Jan 10 12:50:24 PM PST 24
Finished	Jan 10 12:52:48 PM PST 24
Peak memory	222604 kb
Host	smart-b7c58982-de45-4659-a108-f8ce4ff6f892
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=236055998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.236055998 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspace/4.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/8.kmac_error.2634934566
Short name	T37
Test name
Test status
Simulation time	20130271493 ps
CPU time	241.62 seconds
Started	Jan 10 12:51:04 PM PST 24
Finished	Jan 10 12:56:27 PM PST 24
Peak memory	255404 kb
Host	smart-22bfcd21-024c-4cc5-a72b-63656210adae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2634934566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.2634934566 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_error/latest

Test location	/workspace/coverage/default/0.kmac_edn_timeout_error.1403581819
Short name	T75
Test name
Test status
Simulation time	26484400 ps
CPU time	1.14 seconds
Started	Jan 10 12:50:12 PM PST 24
Finished	Jan 10 12:51:52 PM PST 24
Peak memory	219308 kb
Host	smart-c527c7d5-4957-412b-a0dc-4f85e284d8f4
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1403581819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.1403581819 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/29.kmac_stress_all.127331030
Short name	T32
Test name
Test status
Simulation time	114872208712 ps
CPU time	997.74 seconds
Started	Jan 10 12:51:58 PM PST 24
Finished	Jan 10 01:09:54 PM PST 24
Peak memory	327884 kb
Host	smart-d455231d-ea68-4687-887d-5a3c0b4a6791
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=127331030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.127331030 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.1897196158
Short name	T137
Test name
Test status
Simulation time	220606248 ps
CPU time	1.82 seconds
Started	Jan 10 01:10:14 PM PST 24
Finished	Jan 10 01:11:33 PM PST 24
Peak memory	221236 kb
Host	smart-b2ab2b3b-4714-4791-9617-ea1dacc4c404
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897196158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac _shadow_reg_errors_with_csr_rw.1897196158 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/47.kmac_intr_test.3103276403
Short name	T128
Test name
Test status
Simulation time	67452166 ps
CPU time	0.79 seconds
Started	Jan 10 01:10:50 PM PST 24
Finished	Jan 10 01:12:14 PM PST 24
Peak memory	217520 kb
Host	smart-18585a79-60d6-45fe-a0ce-a69c0eb88d81
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103276403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.3103276403 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_intr_test/latest

Test location	/workspace/coverage/default/30.kmac_error.4061662435
Short name	T22
Test name
Test status
Simulation time	23489108603 ps
CPU time	293 seconds
Started	Jan 10 12:52:04 PM PST 24
Finished	Jan 10 12:58:13 PM PST 24
Peak memory	260324 kb
Host	smart-67f7d492-8b3d-45c6-b2fe-02b503bb8729
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4061662435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.4061662435 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_error/latest

Test location	/workspace/coverage/default/18.kmac_entropy_refresh.3736875699
Short name	T83
Test name
Test status
Simulation time	16767171980 ps
CPU time	326.53 seconds
Started	Jan 10 12:51:32 PM PST 24
Finished	Jan 10 12:58:13 PM PST 24
Peak memory	249316 kb
Host	smart-70dd7eaa-2f40-4488-b6cc-9cdfd3f3d57f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3736875699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.3736875699 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/18.kmac_entropy_refresh/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.2094349020
Short name	T117
Test name
Test status
Simulation time	650518510 ps
CPU time	3.17 seconds
Started	Jan 10 01:10:04 PM PST 24
Finished	Jan 10 01:11:16 PM PST 24
Peak memory	217740 kb
Host	smart-46ccc05f-72b8-430d-8aed-ad6a0d0e3208
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094349020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.20943 49020 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.2322915046
Short name	T1228
Test name
Test status
Simulation time	141085578 ps
CPU time	2.95 seconds
Started	Jan 10 01:10:27 PM PST 24
Finished	Jan 10 01:11:49 PM PST 24
Peak memory	216908 kb
Host	smart-1b5a2e67-8c14-4ee7-b12b-d96ce99464fc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322915046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.2322 915046 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_intg_err/latest

Test location	/workspace/coverage/default/11.kmac_entropy_mode_error.1396290551
Short name	T526
Test name
Test status
Simulation time	23274992 ps
CPU time	0.83 seconds
Started	Jan 10 12:50:48 PM PST 24
Finished	Jan 10 12:52:05 PM PST 24
Peak memory	218984 kb
Host	smart-5b4c7728-754a-49eb-b49b-9ad7e82d14c5
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1396290551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.1396290551 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/41.kmac_stress_all.2878737326
Short name	T321
Test name
Test status
Simulation time	87615385019 ps
CPU time	2391.07 seconds
Started	Jan 10 12:52:20 PM PST 24
Finished	Jan 10 01:33:38 PM PST 24
Peak memory	419708 kb
Host	smart-442c3acb-d37b-42bb-8115-f2332249dcb6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2878737326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.2878737326 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_stress_all/latest

Test location	/workspace/coverage/default/14.kmac_alert_test.399819468
Short name	T103
Test name
Test status
Simulation time	23964681 ps
CPU time	0.88 seconds
Started	Jan 10 12:51:16 PM PST 24
Finished	Jan 10 12:52:38 PM PST 24
Peak memory	218956 kb
Host	smart-cd53ee63-e73f-4c96-84ce-cfbced879e41
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399819468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.399819468 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_alert_test/latest

Test location	/workspace/coverage/default/10.kmac_lc_escalation.4207633491
Short name	T230
Test name
Test status
Simulation time	79492248 ps
CPU time	1.34 seconds
Started	Jan 10 12:50:48 PM PST 24
Finished	Jan 10 12:52:13 PM PST 24
Peak memory	220428 kb
Host	smart-0c0bec6e-22cb-4552-9aac-b532eb05443a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4207633491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.4207633491 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/10.kmac_lc_escalation/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3974821257
Short name	T1135
Test name
Test status
Simulation time	48150520 ps
CPU time	2.27 seconds
Started	Jan 10 01:10:24 PM PST 24
Finished	Jan 10 01:11:43 PM PST 24
Peak memory	217020 kb
Host	smart-2a6fc5fa-d92e-4bf6-a3f4-61ca2849b7cc
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974821257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma c_shadow_reg_errors_with_csr_rw.3974821257 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/10.kmac_app.1723958870
Short name	T101
Test name
Test status
Simulation time	33999400804 ps
CPU time	246.11 seconds
Started	Jan 10 12:50:47 PM PST 24
Finished	Jan 10 12:56:16 PM PST 24
Peak memory	247152 kb
Host	smart-4401d467-6525-42c7-a20f-f00e99fe1c40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1723958870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1723958870 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_app/latest

Test location	/workspace/coverage/default/11.kmac_stress_all.2583017067
Short name	T374
Test name
Test status
Simulation time	87293808013 ps
CPU time	1972.58 seconds
Started	Jan 10 12:50:53 PM PST 24
Finished	Jan 10 01:25:02 PM PST 24
Peak memory	407916 kb
Host	smart-5bb4f49e-71cf-48f5-ab0d-441d16dd90fa
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2583017067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.2583017067 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.4087674197
Short name	T118
Test name
Test status
Simulation time	1079395195 ps
CPU time	11.24 seconds
Started	Jan 10 01:10:18 PM PST 24
Finished	Jan 10 01:11:44 PM PST 24
Peak memory	217768 kb
Host	smart-a28a92fd-b88c-4b75-bb7c-50272fd742f3
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087674197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.4087674 197 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2074091096
Short name	T1223
Test name
Test status
Simulation time	6209099998 ps
CPU time	22.48 seconds
Started	Jan 10 01:10:19 PM PST 24
Finished	Jan 10 01:11:56 PM PST 24
Peak memory	217888 kb
Host	smart-48aee010-582a-4fc6-a380-aed4229c863d
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074091096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.2074091 096 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1989352635
Short name	T1225
Test name
Test status
Simulation time	236472385 ps
CPU time	1.11 seconds
Started	Jan 10 01:10:22 PM PST 24
Finished	Jan 10 01:11:40 PM PST 24
Peak memory	217700 kb
Host	smart-c6ed5e01-922d-48fd-8397-8d9a0b2c9687
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989352635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1989352 635 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.3659467038
Short name	T1138
Test name
Test status
Simulation time	19847578 ps
CPU time	1.76 seconds
Started	Jan 10 01:10:05 PM PST 24
Finished	Jan 10 01:11:16 PM PST 24
Peak memory	223028 kb
Host	smart-5483f343-bf0e-4e4c-a612-967624dcacb4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659467038 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.3659467038 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_rw.3310361949
Short name	T132
Test name
Test status
Simulation time	519509745 ps
CPU time	1.26 seconds
Started	Jan 10 01:10:18 PM PST 24
Finished	Jan 10 01:11:34 PM PST 24
Peak memory	217708 kb
Host	smart-8d1f0408-4bf0-4293-90a4-792a58a9c5d3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310361949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.3310361949 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_intr_test.3692909811
Short name	T64
Test name
Test status
Simulation time	33608521 ps
CPU time	0.78 seconds
Started	Jan 10 01:10:29 PM PST 24
Finished	Jan 10 01:11:51 PM PST 24
Peak memory	216736 kb
Host	smart-c75fce4b-f33c-4200-83fb-5fb5fb6ce0ed
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692909811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.3692909811 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.4136505930
Short name	T134
Test name
Test status
Simulation time	28668228 ps
CPU time	1.24 seconds
Started	Jan 10 01:10:13 PM PST 24
Finished	Jan 10 01:11:27 PM PST 24
Peak memory	217744 kb
Host	smart-e736f234-087c-4056-8996-948ca013fc5f
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136505930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia l_access.4136505930 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_walk.4286717756
Short name	T1230
Test name
Test status
Simulation time	31409767 ps
CPU time	0.75 seconds
Started	Jan 10 01:10:11 PM PST 24
Finished	Jan 10 01:11:24 PM PST 24
Peak memory	216656 kb
Host	smart-f35e3161-132c-4dbe-8d30-4746e29739ba
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286717756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.4286717756 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2183945881
Short name	T1218
Test name
Test status
Simulation time	187839019 ps
CPU time	2.79 seconds
Started	Jan 10 01:10:24 PM PST 24
Finished	Jan 10 01:11:44 PM PST 24
Peak memory	217752 kb
Host	smart-dc660ee2-5577-4f05-8a85-54703d170b42
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183945881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr _outstanding.2183945881 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3993790132
Short name	T95
Test name
Test status
Simulation time	313403986 ps
CPU time	1.44 seconds
Started	Jan 10 01:10:17 PM PST 24
Finished	Jan 10 01:11:36 PM PST 24
Peak memory	225160 kb
Host	smart-de90feb1-d46e-4672-b31c-15cca6798054
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993790132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_ errors.3993790132 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_errors.736013871
Short name	T61
Test name
Test status
Simulation time	66171894 ps
CPU time	2.34 seconds
Started	Jan 10 01:10:14 PM PST 24
Finished	Jan 10 01:11:34 PM PST 24
Peak memory	217012 kb
Host	smart-56556f12-b846-4216-a7b9-1b5c77c30f96
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736013871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.736013871 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.2007181583
Short name	T1190
Test name
Test status
Simulation time	84234402 ps
CPU time	4.85 seconds
Started	Jan 10 01:10:03 PM PST 24
Finished	Jan 10 01:11:17 PM PST 24
Peak memory	217064 kb
Host	smart-4d4afd99-40dc-47b9-aebf-a3c3292012fb
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007181583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.2007181 583 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.1268926374
Short name	T1136
Test name
Test status
Simulation time	159804697 ps
CPU time	9.13 seconds
Started	Jan 10 01:10:12 PM PST 24
Finished	Jan 10 01:11:33 PM PST 24
Peak memory	217908 kb
Host	smart-f4b5df62-5d01-4e05-82e1-b7292a6d09af
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268926374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.1268926 374 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.3806574036
Short name	T1189
Test name
Test status
Simulation time	104512768 ps
CPU time	1.05 seconds
Started	Jan 10 01:10:13 PM PST 24
Finished	Jan 10 01:11:27 PM PST 24
Peak memory	217532 kb
Host	smart-5ea8089f-576b-47ee-8809-490a3ff324c5
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806574036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.3806574 036 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.3320057796
Short name	T1181
Test name
Test status
Simulation time	33624912 ps
CPU time	1.43 seconds
Started	Jan 10 01:10:18 PM PST 24
Finished	Jan 10 01:11:33 PM PST 24
Peak memory	219564 kb
Host	smart-4b501859-8ece-405e-aca4-26e5b61ca029
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320057796 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.3320057796 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_rw.2202716964
Short name	T139
Test name
Test status
Simulation time	26427111 ps
CPU time	1.06 seconds
Started	Jan 10 01:10:15 PM PST 24
Finished	Jan 10 01:11:29 PM PST 24
Peak memory	217912 kb
Host	smart-97996991-f3b1-44d8-a637-974709b50ef7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202716964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2202716964 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_intr_test.2394275853
Short name	T1195
Test name
Test status
Simulation time	21136610 ps
CPU time	0.8 seconds
Started	Jan 10 01:10:07 PM PST 24
Finished	Jan 10 01:11:18 PM PST 24
Peak memory	217636 kb
Host	smart-44d24441-940e-4dda-bdd0-efb6e1a4dcb7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394275853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.2394275853 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_walk.2452126128
Short name	T1162
Test name
Test status
Simulation time	12676985 ps
CPU time	0.73 seconds
Started	Jan 10 01:10:10 PM PST 24
Finished	Jan 10 01:11:23 PM PST 24
Peak memory	217500 kb
Host	smart-6c6862bf-8268-4116-a11e-fa1ce88414c2
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452126128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.2452126128 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.2628906221
Short name	T130
Test name
Test status
Simulation time	94072850 ps
CPU time	1.69 seconds
Started	Jan 10 01:10:37 PM PST 24
Finished	Jan 10 01:12:02 PM PST 24
Peak memory	217740 kb
Host	smart-7a4cd0ff-8d65-4275-96e3-2979dd61a531
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628906221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr _outstanding.2628906221 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3004719825
Short name	T1196
Test name
Test status
Simulation time	38683166 ps
CPU time	1.16 seconds
Started	Jan 10 01:10:19 PM PST 24
Finished	Jan 10 01:11:35 PM PST 24
Peak memory	218068 kb
Host	smart-e865efcb-f55d-48af-bdcf-36b53b6ef188
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004719825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_ errors.3004719825 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.4006962086
Short name	T55
Test name
Test status
Simulation time	120065848 ps
CPU time	1.93 seconds
Started	Jan 10 01:10:15 PM PST 24
Finished	Jan 10 01:11:30 PM PST 24
Peak memory	220912 kb
Host	smart-b0b1ea81-261b-4378-a3bb-f6ce83c1c974
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006962086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac _shadow_reg_errors_with_csr_rw.4006962086 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_errors.2664250713
Short name	T1245
Test name
Test status
Simulation time	47297268 ps
CPU time	1.31 seconds
Started	Jan 10 01:10:19 PM PST 24
Finished	Jan 10 01:11:35 PM PST 24
Peak memory	217056 kb
Host	smart-81bae94c-de1e-4930-a0c5-fbe5641fe414
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664250713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.2664250713 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.235559924
Short name	T152
Test name
Test status
Simulation time	211908441 ps
CPU time	5.01 seconds
Started	Jan 10 01:10:21 PM PST 24
Finished	Jan 10 01:11:41 PM PST 24
Peak memory	217652 kb
Host	smart-3ea51304-0bd9-4109-bab0-9c7db9d70de1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235559924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.235559 924 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3467109337
Short name	T1243
Test name
Test status
Simulation time	42653342 ps
CPU time	1.77 seconds
Started	Jan 10 01:10:22 PM PST 24
Finished	Jan 10 01:11:40 PM PST 24
Peak memory	222432 kb
Host	smart-8149c8d7-cbc9-4012-8e92-a53e721bf4cd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467109337 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.3467109337 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_rw.4000456838
Short name	T122
Test name
Test status
Simulation time	128787277 ps
CPU time	1.25 seconds
Started	Jan 10 01:10:24 PM PST 24
Finished	Jan 10 01:11:43 PM PST 24
Peak memory	217716 kb
Host	smart-7acc1bcc-3f81-489d-8f4f-e1a29839d2b9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000456838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.4000456838 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_intr_test.2979550546
Short name	T1227
Test name
Test status
Simulation time	55076844 ps
CPU time	0.79 seconds
Started	Jan 10 01:10:29 PM PST 24
Finished	Jan 10 01:11:50 PM PST 24
Peak memory	216664 kb
Host	smart-b8915562-5ebf-4bd1-87d8-2d65968413d8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979550546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.2979550546 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3936685064
Short name	T1191
Test name
Test status
Simulation time	381022622 ps
CPU time	2.52 seconds
Started	Jan 10 01:10:20 PM PST 24
Finished	Jan 10 01:11:41 PM PST 24
Peak memory	217684 kb
Host	smart-ed5347b6-e081-400f-839f-82d22c770e3d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936685064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs r_outstanding.3936685064 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.932118456
Short name	T96
Test name
Test status
Simulation time	99473537 ps
CPU time	1.15 seconds
Started	Jan 10 01:10:21 PM PST 24
Finished	Jan 10 01:11:38 PM PST 24
Peak memory	225220 kb
Host	smart-69bf8774-c350-421e-9c85-1e2ce39c597f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932118456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_ errors.932118456 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_errors.2378136293
Short name	T1226
Test name
Test status
Simulation time	77313727 ps
CPU time	2.19 seconds
Started	Jan 10 01:10:23 PM PST 24
Finished	Jan 10 01:11:41 PM PST 24
Peak memory	218036 kb
Host	smart-6ebcce08-42c4-4a40-9a75-409746fb7590
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378136293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.2378136293 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.1100367347
Short name	T148
Test name
Test status
Simulation time	743417297 ps
CPU time	4.91 seconds
Started	Jan 10 01:10:24 PM PST 24
Finished	Jan 10 01:11:47 PM PST 24
Peak memory	217652 kb
Host	smart-52736993-648a-4c8e-b167-8bd7ea85c6a0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100367347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.1100 367347 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2497217898
Short name	T1151
Test name
Test status
Simulation time	20785139 ps
CPU time	1.36 seconds
Started	Jan 10 01:10:28 PM PST 24
Finished	Jan 10 01:11:48 PM PST 24
Peak memory	220216 kb
Host	smart-6246cd9b-0c62-4877-bedc-131903dec5c6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497217898 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.2497217898 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_rw.2795120673
Short name	T1209
Test name
Test status
Simulation time	142360391 ps
CPU time	1 seconds
Started	Jan 10 01:10:28 PM PST 24
Finished	Jan 10 01:11:50 PM PST 24
Peak memory	217556 kb
Host	smart-46e1d601-9e98-4c91-afba-4e4db8048d8a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795120673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2795120673 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3967508789
Short name	T165
Test name
Test status
Simulation time	671601219 ps
CPU time	2.32 seconds
Started	Jan 10 01:10:25 PM PST 24
Finished	Jan 10 01:11:45 PM PST 24
Peak memory	218016 kb
Host	smart-10e25687-464a-411b-b044-24ec3e74ccbf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967508789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs r_outstanding.3967508789 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.3505958000
Short name	T1175
Test name
Test status
Simulation time	101917749 ps
CPU time	1 seconds
Started	Jan 10 01:10:19 PM PST 24
Finished	Jan 10 01:11:35 PM PST 24
Peak memory	221544 kb
Host	smart-8c324226-e092-4538-8d5d-4f33fbbfde6f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505958000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg _errors.3505958000 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3008539196
Short name	T1183
Test name
Test status
Simulation time	247806406 ps
CPU time	2.9 seconds
Started	Jan 10 01:10:25 PM PST 24
Finished	Jan 10 01:11:45 PM PST 24
Peak memory	220664 kb
Host	smart-e4aa6f32-f8ad-4e05-957f-7cd66f1832cb
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008539196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma c_shadow_reg_errors_with_csr_rw.3008539196 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_errors.4166659070
Short name	T1199
Test name
Test status
Simulation time	81349288 ps
CPU time	2.7 seconds
Started	Jan 10 01:10:27 PM PST 24
Finished	Jan 10 01:11:47 PM PST 24
Peak memory	217132 kb
Host	smart-30672ded-6276-4c1c-90c7-91895483ceca
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166659070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.4166659070 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.3389602009
Short name	T1240
Test name
Test status
Simulation time	177888905 ps
CPU time	2.02 seconds
Started	Jan 10 01:10:31 PM PST 24
Finished	Jan 10 01:11:55 PM PST 24
Peak memory	223300 kb
Host	smart-23324444-de46-4c19-b95e-4f996d4a0bab
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389602009 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.3389602009 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_rw.1444559166
Short name	T1212
Test name
Test status
Simulation time	148305325 ps
CPU time	1.1 seconds
Started	Jan 10 01:10:22 PM PST 24
Finished	Jan 10 01:11:38 PM PST 24
Peak memory	217772 kb
Host	smart-c76accdc-ae35-4a2a-98bf-2830ab29422d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444559166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.1444559166 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2924129230
Short name	T1182
Test name
Test status
Simulation time	225692626 ps
CPU time	1.69 seconds
Started	Jan 10 01:10:35 PM PST 24
Finished	Jan 10 01:12:01 PM PST 24
Peak memory	217804 kb
Host	smart-2f581c4f-45e6-4ca6-980a-31222514a8e0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924129230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs r_outstanding.2924129230 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1235820394
Short name	T69
Test name
Test status
Simulation time	117009798 ps
CPU time	1.09 seconds
Started	Jan 10 01:10:23 PM PST 24
Finished	Jan 10 01:11:41 PM PST 24
Peak memory	217720 kb
Host	smart-d5239791-c660-4526-a344-7a903b8b6dae
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235820394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg _errors.1235820394 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.2298834672
Short name	T129
Test name
Test status
Simulation time	180996402 ps
CPU time	2.71 seconds
Started	Jan 10 01:10:32 PM PST 24
Finished	Jan 10 01:11:56 PM PST 24
Peak memory	220728 kb
Host	smart-fd970c78-5dfb-4c11-b86f-72298e567778
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298834672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma c_shadow_reg_errors_with_csr_rw.2298834672 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_errors.3077766214
Short name	T1143
Test name
Test status
Simulation time	327272461 ps
CPU time	1.86 seconds
Started	Jan 10 01:10:36 PM PST 24
Finished	Jan 10 01:12:01 PM PST 24
Peak memory	217732 kb
Host	smart-648b0acc-dd5b-48f5-85bc-13c51a3f10b4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077766214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.3077766214 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.967456057
Short name	T150
Test name
Test status
Simulation time	1670458021 ps
CPU time	4.83 seconds
Started	Jan 10 01:10:23 PM PST 24
Finished	Jan 10 01:11:44 PM PST 24
Peak memory	217748 kb
Host	smart-cedbee24-a367-41a6-93fc-a3a3db2699af
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967456057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.96745 6057 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.662349400
Short name	T1194
Test name
Test status
Simulation time	42834441 ps
CPU time	1.5 seconds
Started	Jan 10 01:10:31 PM PST 24
Finished	Jan 10 01:11:54 PM PST 24
Peak memory	219748 kb
Host	smart-d6df0480-1a5e-4d94-b84d-74e7ae05b1d4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662349400 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.662349400 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_rw.3332638174
Short name	T1123
Test name
Test status
Simulation time	109390647 ps
CPU time	1.19 seconds
Started	Jan 10 01:10:35 PM PST 24
Finished	Jan 10 01:12:00 PM PST 24
Peak memory	217768 kb
Host	smart-dd03189e-171f-46d1-aeda-e15c2062d56c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332638174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.3332638174 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_intr_test.3254839171
Short name	T140
Test name
Test status
Simulation time	30713391 ps
CPU time	0.83 seconds
Started	Jan 10 01:10:33 PM PST 24
Finished	Jan 10 01:11:57 PM PST 24
Peak memory	216816 kb
Host	smart-5a948993-5853-494f-a908-608e41d1edb9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254839171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.3254839171 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.900566293
Short name	T1159
Test name
Test status
Simulation time	252228652 ps
CPU time	1.51 seconds
Started	Jan 10 01:10:32 PM PST 24
Finished	Jan 10 01:11:55 PM PST 24
Peak memory	217752 kb
Host	smart-e108947b-b708-44ef-8f06-3fd57fab072f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900566293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr _outstanding.900566293 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2548668065
Short name	T1139
Test name
Test status
Simulation time	292589237 ps
CPU time	2.11 seconds
Started	Jan 10 01:10:37 PM PST 24
Finished	Jan 10 01:12:03 PM PST 24
Peak memory	220436 kb
Host	smart-9c2374b6-215b-48b4-a67e-6ceb06223f5f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548668065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma c_shadow_reg_errors_with_csr_rw.2548668065 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_errors.2711317308
Short name	T58
Test name
Test status
Simulation time	189619304 ps
CPU time	2.33 seconds
Started	Jan 10 01:10:15 PM PST 24
Finished	Jan 10 01:11:30 PM PST 24
Peak memory	217012 kb
Host	smart-3c2bb83e-ed78-4c88-9bfe-977e19564464
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711317308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.2711317308 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.2196816455
Short name	T1170
Test name
Test status
Simulation time	180578578 ps
CPU time	3.41 seconds
Started	Jan 10 01:10:25 PM PST 24
Finished	Jan 10 01:11:46 PM PST 24
Peak memory	217124 kb
Host	smart-80340c4a-7569-4cc6-a397-95206b79c1d7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196816455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.2196 816455 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2996321334
Short name	T1248
Test name
Test status
Simulation time	24845005 ps
CPU time	1.28 seconds
Started	Jan 10 01:10:26 PM PST 24
Finished	Jan 10 01:11:45 PM PST 24
Peak memory	218824 kb
Host	smart-876668fa-9fb5-424e-b16f-e596f9afbc03
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996321334 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.2996321334 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_rw.1488643705
Short name	T1188
Test name
Test status
Simulation time	29920360 ps
CPU time	1.15 seconds
Started	Jan 10 01:10:23 PM PST 24
Finished	Jan 10 01:11:41 PM PST 24
Peak memory	217744 kb
Host	smart-f743fe03-af55-4f17-b1e0-080a586707ef
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488643705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.1488643705 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_intr_test.198625130
Short name	T1142
Test name
Test status
Simulation time	17394534 ps
CPU time	0.86 seconds
Started	Jan 10 01:10:40 PM PST 24
Finished	Jan 10 01:12:05 PM PST 24
Peak memory	217484 kb
Host	smart-22020196-3542-4ef3-8b0b-74bd63aa75d0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198625130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.198625130 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.392945197
Short name	T1172
Test name
Test status
Simulation time	660108794 ps
CPU time	2.92 seconds
Started	Jan 10 01:10:39 PM PST 24
Finished	Jan 10 01:12:05 PM PST 24
Peak memory	217784 kb
Host	smart-2e805dd8-b632-41f3-8709-c86cb5a654ce
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392945197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr _outstanding.392945197 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2116802458
Short name	T94
Test name
Test status
Simulation time	50207428 ps
CPU time	1.36 seconds
Started	Jan 10 01:10:26 PM PST 24
Finished	Jan 10 01:11:44 PM PST 24
Peak memory	225232 kb
Host	smart-6caaad91-eeac-431c-bd99-9f4885e06fb9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116802458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg _errors.2116802458 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.4204477631
Short name	T138
Test name
Test status
Simulation time	128618563 ps
CPU time	1.9 seconds
Started	Jan 10 01:10:29 PM PST 24
Finished	Jan 10 01:11:52 PM PST 24
Peak memory	225268 kb
Host	smart-2d4f043c-6f47-46fc-927e-e9454696abe2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204477631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma c_shadow_reg_errors_with_csr_rw.4204477631 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_errors.714074045
Short name	T1133
Test name
Test status
Simulation time	176649488 ps
CPU time	2.74 seconds
Started	Jan 10 01:10:29 PM PST 24
Finished	Jan 10 01:11:53 PM PST 24
Peak memory	217768 kb
Host	smart-29b38adf-d4b2-436d-870b-fc1266187cd1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714074045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.714074045 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2509311545
Short name	T1201
Test name
Test status
Simulation time	43741559 ps
CPU time	1.17 seconds
Started	Jan 10 01:10:30 PM PST 24
Finished	Jan 10 01:11:53 PM PST 24
Peak memory	224864 kb
Host	smart-236c9ca2-0c3c-4d20-8f15-a47eedf41826
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509311545 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.2509311545 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_rw.892025899
Short name	T1241
Test name
Test status
Simulation time	22558163 ps
CPU time	0.93 seconds
Started	Jan 10 01:10:23 PM PST 24
Finished	Jan 10 01:11:41 PM PST 24
Peak memory	217476 kb
Host	smart-62449d3c-d2d9-4038-a93a-6c67a60a31eb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892025899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.892025899 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_intr_test.247241080
Short name	T1117
Test name
Test status
Simulation time	46853919 ps
CPU time	0.79 seconds
Started	Jan 10 01:10:23 PM PST 24
Finished	Jan 10 01:11:41 PM PST 24
Peak memory	217456 kb
Host	smart-8d401e46-c80e-4626-aced-b897e4815fea
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247241080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.247241080 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.29573068
Short name	T1204
Test name
Test status
Simulation time	40845408 ps
CPU time	2.23 seconds
Started	Jan 10 01:10:21 PM PST 24
Finished	Jan 10 01:11:41 PM PST 24
Peak memory	217712 kb
Host	smart-45f1993e-44eb-4720-8065-03f80b7b2b6e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29573068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_ outstanding.29573068 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.984851054
Short name	T1169
Test name
Test status
Simulation time	209843229 ps
CPU time	2.9 seconds
Started	Jan 10 01:10:25 PM PST 24
Finished	Jan 10 01:11:45 PM PST 24
Peak memory	222004 kb
Host	smart-14217d11-270c-43e7-97fd-05d1422461f8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984851054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac _shadow_reg_errors_with_csr_rw.984851054 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_errors.4186911785
Short name	T1124
Test name
Test status
Simulation time	29158064 ps
CPU time	1.93 seconds
Started	Jan 10 01:10:23 PM PST 24
Finished	Jan 10 01:11:41 PM PST 24
Peak memory	217784 kb
Host	smart-f5a7d2ad-66d8-4eeb-a222-ec823c940851
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186911785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.4186911785 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.201985155
Short name	T1153
Test name
Test status
Simulation time	116447970 ps
CPU time	2.86 seconds
Started	Jan 10 01:10:33 PM PST 24
Finished	Jan 10 01:11:58 PM PST 24
Peak memory	217812 kb
Host	smart-d98b1a17-8325-425b-9e4a-c126774811bb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201985155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.20198 5155 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3132091343
Short name	T1214
Test name
Test status
Simulation time	28326324 ps
CPU time	1.7 seconds
Started	Jan 10 01:10:23 PM PST 24
Finished	Jan 10 01:11:40 PM PST 24
Peak memory	220828 kb
Host	smart-ccd5eebf-114e-4e17-96a5-0c0ce812a14a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132091343 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.3132091343 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_rw.4060339235
Short name	T1145
Test name
Test status
Simulation time	66811732 ps
CPU time	0.97 seconds
Started	Jan 10 01:10:20 PM PST 24
Finished	Jan 10 01:11:40 PM PST 24
Peak memory	217508 kb
Host	smart-30d2a0b7-43c8-4f6a-b27a-88899373ff81
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060339235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.4060339235 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_intr_test.1333995327
Short name	T1177
Test name
Test status
Simulation time	88640838 ps
CPU time	0.85 seconds
Started	Jan 10 01:10:30 PM PST 24
Finished	Jan 10 01:11:52 PM PST 24
Peak memory	216712 kb
Host	smart-709ebf4e-55e6-4e61-b030-695a45c079be
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333995327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.1333995327 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1232677734
Short name	T1213
Test name
Test status
Simulation time	390977784 ps
CPU time	2.76 seconds
Started	Jan 10 01:10:24 PM PST 24
Finished	Jan 10 01:11:44 PM PST 24
Peak memory	217808 kb
Host	smart-956ea4a2-d692-4f69-8053-66e791c78889
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232677734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs r_outstanding.1232677734 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.3763123392
Short name	T93
Test name
Test status
Simulation time	104574526 ps
CPU time	1.57 seconds
Started	Jan 10 01:10:39 PM PST 24
Finished	Jan 10 01:12:04 PM PST 24
Peak memory	218920 kb
Host	smart-b0f9714f-4639-4073-8c70-92ab09338b04
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763123392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg _errors.3763123392 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.622045983
Short name	T90
Test name
Test status
Simulation time	31128738 ps
CPU time	1.9 seconds
Started	Jan 10 01:10:29 PM PST 24
Finished	Jan 10 01:11:52 PM PST 24
Peak memory	221904 kb
Host	smart-154fa4c5-3398-475d-bcd3-d5baf3adfc36
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622045983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac _shadow_reg_errors_with_csr_rw.622045983 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_errors.1279757258
Short name	T59
Test name
Test status
Simulation time	53438008 ps
CPU time	1.79 seconds
Started	Jan 10 01:10:22 PM PST 24
Finished	Jan 10 01:11:40 PM PST 24
Peak memory	217536 kb
Host	smart-fa959e47-3d34-42ec-be91-615ffe74e9ff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279757258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.1279757258 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.2191666034
Short name	T1249
Test name
Test status
Simulation time	3582000841 ps
CPU time	5.85 seconds
Started	Jan 10 01:10:23 PM PST 24
Finished	Jan 10 01:11:45 PM PST 24
Peak memory	218004 kb
Host	smart-a0646cc1-002a-4c19-9095-c52fb5c1d765
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191666034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.2191 666034 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1721949516
Short name	T1219
Test name
Test status
Simulation time	27079492 ps
CPU time	2.21 seconds
Started	Jan 10 01:10:28 PM PST 24
Finished	Jan 10 01:11:51 PM PST 24
Peak memory	225120 kb
Host	smart-4a7653c6-82cc-47ce-b908-84bf060959f1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721949516 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.1721949516 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_rw.1658028565
Short name	T1179
Test name
Test status
Simulation time	80260982 ps
CPU time	1.22 seconds
Started	Jan 10 01:10:24 PM PST 24
Finished	Jan 10 01:11:41 PM PST 24
Peak memory	217880 kb
Host	smart-05392c7c-764b-4226-97a4-699951b3b180
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658028565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.1658028565 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_intr_test.1780415528
Short name	T1217
Test name
Test status
Simulation time	21157061 ps
CPU time	0.83 seconds
Started	Jan 10 01:10:24 PM PST 24
Finished	Jan 10 01:11:41 PM PST 24
Peak memory	217616 kb
Host	smart-6f7cb8e9-f52c-4383-b952-4dc0771d796f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780415528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.1780415528 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.4076348127
Short name	T1164
Test name
Test status
Simulation time	89431536 ps
CPU time	1.67 seconds
Started	Jan 10 01:10:23 PM PST 24
Finished	Jan 10 01:11:41 PM PST 24
Peak memory	217872 kb
Host	smart-15af8bcc-270b-4bbb-b07d-d2f38afdc305
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076348127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs r_outstanding.4076348127 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.130502401
Short name	T1206
Test name
Test status
Simulation time	26237319 ps
CPU time	0.85 seconds
Started	Jan 10 01:10:29 PM PST 24
Finished	Jan 10 01:11:50 PM PST 24
Peak memory	217668 kb
Host	smart-a9dd4664-f7c5-4956-a5e7-84e441e0259d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130502401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_ errors.130502401 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_errors.1900508860
Short name	T1252
Test name
Test status
Simulation time	101237950 ps
CPU time	2.96 seconds
Started	Jan 10 01:10:18 PM PST 24
Finished	Jan 10 01:11:35 PM PST 24
Peak memory	218184 kb
Host	smart-b07abad4-92eb-4d70-9d15-5efcb5ab55f9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900508860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.1900508860 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.878828499
Short name	T1154
Test name
Test status
Simulation time	28364796 ps
CPU time	1.38 seconds
Started	Jan 10 01:10:49 PM PST 24
Finished	Jan 10 01:12:17 PM PST 24
Peak memory	220800 kb
Host	smart-80086533-7fe5-4629-bae7-895969374485
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878828499 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.878828499 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_rw.1507791764
Short name	T1251
Test name
Test status
Simulation time	43210099 ps
CPU time	1.26 seconds
Started	Jan 10 01:10:53 PM PST 24
Finished	Jan 10 01:12:22 PM PST 24
Peak memory	217828 kb
Host	smart-56fed701-f651-46f9-b6a9-bf6f3b4a313c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507791764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.1507791764 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_intr_test.4294787919
Short name	T1253
Test name
Test status
Simulation time	43563008 ps
CPU time	0.78 seconds
Started	Jan 10 01:10:50 PM PST 24
Finished	Jan 10 01:12:15 PM PST 24
Peak memory	217632 kb
Host	smart-2732c91e-f805-4926-9eb7-06d8850edb68
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294787919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.4294787919 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2638011491
Short name	T1118
Test name
Test status
Simulation time	41138960 ps
CPU time	2.29 seconds
Started	Jan 10 01:10:36 PM PST 24
Finished	Jan 10 01:12:01 PM PST 24
Peak memory	217844 kb
Host	smart-f5b9c84d-9fe5-47ac-801d-4f3dc10e9751
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638011491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs r_outstanding.2638011491 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1914189783
Short name	T1233
Test name
Test status
Simulation time	50935603 ps
CPU time	1.2 seconds
Started	Jan 10 01:10:35 PM PST 24
Finished	Jan 10 01:12:00 PM PST 24
Peak memory	225164 kb
Host	smart-d33af28a-3ad0-4ef7-9d3f-a1ceb737606d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914189783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg _errors.1914189783 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3593454694
Short name	T1236
Test name
Test status
Simulation time	2166411071 ps
CPU time	3.7 seconds
Started	Jan 10 01:10:49 PM PST 24
Finished	Jan 10 01:12:19 PM PST 24
Peak memory	221868 kb
Host	smart-3f8c2ac0-57c2-47d0-a80d-c251f19fb97b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593454694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma c_shadow_reg_errors_with_csr_rw.3593454694 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_errors.1112812920
Short name	T1160
Test name
Test status
Simulation time	306270398 ps
CPU time	2 seconds
Started	Jan 10 01:10:46 PM PST 24
Finished	Jan 10 01:12:11 PM PST 24
Peak memory	217844 kb
Host	smart-cf75a33d-fd03-4b01-81f7-bb696ae916bd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112812920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.1112812920 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.2033977223
Short name	T1250
Test name
Test status
Simulation time	396703257 ps
CPU time	5.15 seconds
Started	Jan 10 01:10:40 PM PST 24
Finished	Jan 10 01:12:09 PM PST 24
Peak memory	217816 kb
Host	smart-8ee78d2a-40cf-4d8a-970c-27c3585673f2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033977223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.2033 977223 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.4034009243
Short name	T54
Test name
Test status
Simulation time	18651199 ps
CPU time	1.23 seconds
Started	Jan 10 01:10:48 PM PST 24
Finished	Jan 10 01:12:12 PM PST 24
Peak memory	220068 kb
Host	smart-bf568a2e-4a56-454e-a236-5b5f73307f77
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034009243 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.4034009243 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_rw.548356095
Short name	T1210
Test name
Test status
Simulation time	67703788 ps
CPU time	1.13 seconds
Started	Jan 10 01:10:40 PM PST 24
Finished	Jan 10 01:12:05 PM PST 24
Peak memory	217052 kb
Host	smart-af470652-c65d-474b-8478-cffef3e17310
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548356095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.548356095 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_intr_test.3254661658
Short name	T1220
Test name
Test status
Simulation time	87769223 ps
CPU time	0.86 seconds
Started	Jan 10 01:10:45 PM PST 24
Finished	Jan 10 01:12:09 PM PST 24
Peak memory	217472 kb
Host	smart-24e768d9-84f0-4205-a0c8-da2d609e6655
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254661658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.3254661658 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.104146352
Short name	T1165
Test name
Test status
Simulation time	53373517 ps
CPU time	1.69 seconds
Started	Jan 10 01:10:42 PM PST 24
Finished	Jan 10 01:12:06 PM PST 24
Peak memory	217784 kb
Host	smart-cca32d87-502d-4bcd-b737-7d384124d918
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104146352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr _outstanding.104146352 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3502662680
Short name	T116
Test name
Test status
Simulation time	71451229 ps
CPU time	1.05 seconds
Started	Jan 10 01:10:55 PM PST 24
Finished	Jan 10 01:12:20 PM PST 24
Peak memory	218688 kb
Host	smart-7301b278-dd56-42a2-a032-d5163e57fa4d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502662680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg _errors.3502662680 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1002132113
Short name	T115
Test name
Test status
Simulation time	234073209 ps
CPU time	2.85 seconds
Started	Jan 10 01:10:50 PM PST 24
Finished	Jan 10 01:12:16 PM PST 24
Peak memory	220520 kb
Host	smart-764244b5-893b-4db7-bf90-8744a9e2d412
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002132113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma c_shadow_reg_errors_with_csr_rw.1002132113 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_errors.146441763
Short name	T1163
Test name
Test status
Simulation time	39627620 ps
CPU time	1.53 seconds
Started	Jan 10 01:10:46 PM PST 24
Finished	Jan 10 01:12:10 PM PST 24
Peak memory	217144 kb
Host	smart-7dc59d01-9a40-449e-b8b8-34c549276cd0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146441763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.146441763 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.524006058
Short name	T113
Test name
Test status
Simulation time	917880446 ps
CPU time	2.74 seconds
Started	Jan 10 01:10:39 PM PST 24
Finished	Jan 10 01:12:05 PM PST 24
Peak memory	217852 kb
Host	smart-4c92b90a-0c33-48ff-9b90-cf72e7f80c10
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524006058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.52400 6058 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.519441643
Short name	T1126
Test name
Test status
Simulation time	333428545 ps
CPU time	5.21 seconds
Started	Jan 10 01:10:20 PM PST 24
Finished	Jan 10 01:11:44 PM PST 24
Peak memory	217676 kb
Host	smart-a3f948b2-c862-4cad-bff8-35c0a69facf2
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519441643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.51944164 3 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.470838617
Short name	T1140
Test name
Test status
Simulation time	5543056540 ps
CPU time	23.51 seconds
Started	Jan 10 01:10:22 PM PST 24
Finished	Jan 10 01:12:02 PM PST 24
Peak memory	217896 kb
Host	smart-3bd130dd-c8c5-4406-87e8-e1c06098b740
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470838617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.47083861 7 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.4204739342
Short name	T131
Test name
Test status
Simulation time	21257260 ps
CPU time	0.96 seconds
Started	Jan 10 01:10:11 PM PST 24
Finished	Jan 10 01:11:24 PM PST 24
Peak memory	217568 kb
Host	smart-2ea6e9ef-62fd-4963-9625-70f478d8c842
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204739342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.4204739 342 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.3334019051
Short name	T1122
Test name
Test status
Simulation time	19437596 ps
CPU time	1.42 seconds
Started	Jan 10 01:10:18 PM PST 24
Finished	Jan 10 01:11:35 PM PST 24
Peak memory	220524 kb
Host	smart-8c185f21-a26b-4692-a49c-5087d1b975ec
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334019051 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.3334019051 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_rw.3885368116
Short name	T1173
Test name
Test status
Simulation time	87479589 ps
CPU time	1.06 seconds
Started	Jan 10 01:10:16 PM PST 24
Finished	Jan 10 01:11:43 PM PST 24
Peak memory	217792 kb
Host	smart-375322d3-b262-479d-8ffd-a8e575cd1b5d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885368116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.3885368116 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_intr_test.1150278588
Short name	T1130
Test name
Test status
Simulation time	12956233 ps
CPU time	0.78 seconds
Started	Jan 10 01:10:11 PM PST 24
Finished	Jan 10 01:11:24 PM PST 24
Peak memory	216816 kb
Host	smart-ca49584e-89ca-43b0-991a-03f786a31cc6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150278588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.1150278588 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.1294746710
Short name	T136
Test name
Test status
Simulation time	35260856 ps
CPU time	1.42 seconds
Started	Jan 10 01:10:25 PM PST 24
Finished	Jan 10 01:11:44 PM PST 24
Peak memory	217692 kb
Host	smart-16433425-06ad-4e35-b2a7-2422bce6e91c
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294746710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia l_access.1294746710 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_walk.929175313
Short name	T162
Test name
Test status
Simulation time	39811278 ps
CPU time	0.76 seconds
Started	Jan 10 01:10:13 PM PST 24
Finished	Jan 10 01:11:26 PM PST 24
Peak memory	216672 kb
Host	smart-5f33515b-47c5-48ea-9eb0-896adaa13fa3
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929175313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.929175313 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3949666169
Short name	T1146
Test name
Test status
Simulation time	32349474 ps
CPU time	1.56 seconds
Started	Jan 10 01:10:20 PM PST 24
Finished	Jan 10 01:11:40 PM PST 24
Peak memory	217852 kb
Host	smart-70b962de-9375-47b9-b988-49de5cb2fd0d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949666169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr _outstanding.3949666169 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2617815789
Short name	T1242
Test name
Test status
Simulation time	94131309 ps
CPU time	1.31 seconds
Started	Jan 10 01:10:20 PM PST 24
Finished	Jan 10 01:11:35 PM PST 24
Peak memory	218064 kb
Host	smart-49ef7775-4171-446d-be16-d87901a38679
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617815789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_ errors.2617815789 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.1583526984
Short name	T1186
Test name
Test status
Simulation time	56772508 ps
CPU time	1.71 seconds
Started	Jan 10 01:10:07 PM PST 24
Finished	Jan 10 01:11:19 PM PST 24
Peak memory	220672 kb
Host	smart-cceba021-6fbe-4219-a1e1-a4478b25a2f4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583526984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac _shadow_reg_errors_with_csr_rw.1583526984 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_errors.1467881957
Short name	T1255
Test name
Test status
Simulation time	40533169 ps
CPU time	1.5 seconds
Started	Jan 10 01:10:14 PM PST 24
Finished	Jan 10 01:11:28 PM PST 24
Peak memory	218080 kb
Host	smart-0f012ada-e107-41f2-8073-5fb9fe1d2908
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467881957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.1467881957 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.168927972
Short name	T1150
Test name
Test status
Simulation time	167973318 ps
CPU time	3.1 seconds
Started	Jan 10 01:10:16 PM PST 24
Finished	Jan 10 01:11:32 PM PST 24
Peak memory	217128 kb
Host	smart-8b49da25-06e8-45e6-bd23-20522c448161
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168927972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.168927 972 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.kmac_intr_test.1036184463
Short name	T1215
Test name
Test status
Simulation time	29769554 ps
CPU time	0.82 seconds
Started	Jan 10 01:10:36 PM PST 24
Finished	Jan 10 01:12:00 PM PST 24
Peak memory	217552 kb
Host	smart-c459a629-9d89-4b01-beb5-034a86a13f95
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036184463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.1036184463 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.kmac_intr_test.2514833308
Short name	T1166
Test name
Test status
Simulation time	27710161 ps
CPU time	0.81 seconds
Started	Jan 10 01:10:45 PM PST 24
Finished	Jan 10 01:12:08 PM PST 24
Peak memory	217064 kb
Host	smart-732296e0-c73b-4db3-b058-341a2bf2e69a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514833308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.2514833308 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.kmac_intr_test.4107427701
Short name	T1152
Test name
Test status
Simulation time	27783866 ps
CPU time	0.84 seconds
Started	Jan 10 01:10:43 PM PST 24
Finished	Jan 10 01:12:07 PM PST 24
Peak memory	216784 kb
Host	smart-3ce3ec55-23c9-4579-9457-c9092be4a4e7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107427701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.4107427701 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.kmac_intr_test.3956434498
Short name	T56
Test name
Test status
Simulation time	23313527 ps
CPU time	0.8 seconds
Started	Jan 10 01:10:47 PM PST 24
Finished	Jan 10 01:12:14 PM PST 24
Peak memory	217600 kb
Host	smart-0ea27c9a-e3e9-41a1-a4af-d47da8652410
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956434498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.3956434498 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.kmac_intr_test.408363697
Short name	T1144
Test name
Test status
Simulation time	184626935 ps
CPU time	0.85 seconds
Started	Jan 10 01:10:37 PM PST 24
Finished	Jan 10 01:12:01 PM PST 24
Peak memory	216820 kb
Host	smart-d45d720b-38cd-4f1c-864a-d1699924fb43
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408363697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.408363697 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.kmac_intr_test.1831651863
Short name	T1221
Test name
Test status
Simulation time	30718046 ps
CPU time	0.77 seconds
Started	Jan 10 01:10:51 PM PST 24
Finished	Jan 10 01:12:15 PM PST 24
Peak memory	216688 kb
Host	smart-e214dd4b-b4c5-4e3a-a2ea-c52ffd6ec283
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831651863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.1831651863 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.kmac_intr_test.2599016610
Short name	T1156
Test name
Test status
Simulation time	23550955 ps
CPU time	0.79 seconds
Started	Jan 10 01:10:47 PM PST 24
Finished	Jan 10 01:12:10 PM PST 24
Peak memory	217480 kb
Host	smart-50642d09-5634-4cfd-8e0f-1efa291d1329
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599016610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.2599016610 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.kmac_intr_test.545153860
Short name	T1176
Test name
Test status
Simulation time	27393081 ps
CPU time	0.78 seconds
Started	Jan 10 01:10:47 PM PST 24
Finished	Jan 10 01:12:14 PM PST 24
Peak memory	216968 kb
Host	smart-3ae63506-27e4-4ecb-a5b7-2b89f48f465a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545153860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.545153860 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.kmac_intr_test.2471690888
Short name	T1237
Test name
Test status
Simulation time	22129006 ps
CPU time	0.79 seconds
Started	Jan 10 01:10:47 PM PST 24
Finished	Jan 10 01:12:10 PM PST 24
Peak memory	217428 kb
Host	smart-7035cbf8-d21a-431c-850b-c36ff7a73d69
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471690888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.2471690888 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.kmac_intr_test.1577643875
Short name	T164
Test name
Test status
Simulation time	15805686 ps
CPU time	0.8 seconds
Started	Jan 10 01:10:51 PM PST 24
Finished	Jan 10 01:12:15 PM PST 24
Peak memory	217424 kb
Host	smart-76da3e28-133d-4b97-9534-c063d89f7a13
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577643875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.1577643875 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.3008991217
Short name	T1132
Test name
Test status
Simulation time	853379928 ps
CPU time	11.15 seconds
Started	Jan 10 01:10:23 PM PST 24
Finished	Jan 10 01:11:50 PM PST 24
Peak memory	217864 kb
Host	smart-bddb58ec-a37a-4a2f-85a0-73d237b03d83
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008991217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.3008991 217 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.1840572003
Short name	T1200
Test name
Test status
Simulation time	2631901594 ps
CPU time	23.92 seconds
Started	Jan 10 01:10:20 PM PST 24
Finished	Jan 10 01:12:03 PM PST 24
Peak memory	217924 kb
Host	smart-a81dc08c-9630-4646-9e2c-4aeddbab59f7
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840572003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.1840572 003 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.884710024
Short name	T163
Test name
Test status
Simulation time	43172668 ps
CPU time	0.93 seconds
Started	Jan 10 01:10:21 PM PST 24
Finished	Jan 10 01:11:37 PM PST 24
Peak memory	216644 kb
Host	smart-df073a66-cd96-49ab-b632-e5a4edae2024
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884710024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.88471002 4 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3686910990
Short name	T1229
Test name
Test status
Simulation time	173280583 ps
CPU time	1.21 seconds
Started	Jan 10 01:10:17 PM PST 24
Finished	Jan 10 01:11:36 PM PST 24
Peak memory	218772 kb
Host	smart-ac50f934-0ba3-48ee-9a3d-6a4224ba37d7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686910990 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.3686910990 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_rw.1334736431
Short name	T1120
Test name
Test status
Simulation time	17358410 ps
CPU time	1.09 seconds
Started	Jan 10 01:10:18 PM PST 24
Finished	Jan 10 01:11:33 PM PST 24
Peak memory	217780 kb
Host	smart-28804f6a-2fca-4d0b-ab91-a222472bb329
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334736431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.1334736431 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_intr_test.2893504085
Short name	T141
Test name
Test status
Simulation time	93097535 ps
CPU time	0.85 seconds
Started	Jan 10 01:10:21 PM PST 24
Finished	Jan 10 01:11:38 PM PST 24
Peak memory	217544 kb
Host	smart-dac4d8bd-1d5a-425c-8bbe-25615ffb0bdd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893504085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.2893504085 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.4286587316
Short name	T133
Test name
Test status
Simulation time	49580953 ps
CPU time	1.16 seconds
Started	Jan 10 01:10:24 PM PST 24
Finished	Jan 10 01:11:43 PM PST 24
Peak memory	217568 kb
Host	smart-615188c1-89b3-48ae-8e37-6807a2513706
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286587316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia l_access.4286587316 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_walk.2326515468
Short name	T1149
Test name
Test status
Simulation time	11810099 ps
CPU time	0.74 seconds
Started	Jan 10 01:10:19 PM PST 24
Finished	Jan 10 01:11:34 PM PST 24
Peak memory	217560 kb
Host	smart-a284b602-c96f-41be-9148-3b7790c4a471
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326515468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.2326515468 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3178448269
Short name	T1148
Test name
Test status
Simulation time	65966774 ps
CPU time	1.79 seconds
Started	Jan 10 01:10:17 PM PST 24
Finished	Jan 10 01:11:37 PM PST 24
Peak memory	217736 kb
Host	smart-8aa641b9-c64c-4832-bc80-e65777e23475
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178448269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr _outstanding.3178448269 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.2512983826
Short name	T1234
Test name
Test status
Simulation time	64625691 ps
CPU time	1.18 seconds
Started	Jan 10 01:10:10 PM PST 24
Finished	Jan 10 01:11:23 PM PST 24
Peak memory	225220 kb
Host	smart-b1de2604-86ca-4000-84b9-6576111d73c1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512983826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_ errors.2512983826 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.197612576
Short name	T1202
Test name
Test status
Simulation time	321126517 ps
CPU time	2.86 seconds
Started	Jan 10 01:10:27 PM PST 24
Finished	Jan 10 01:11:48 PM PST 24
Peak memory	221500 kb
Host	smart-8927d2b8-9b8e-4920-b0cc-fe20c7e06dc7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197612576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_ shadow_reg_errors_with_csr_rw.197612576 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_errors.1419849687
Short name	T1222
Test name
Test status
Simulation time	166936387 ps
CPU time	2.66 seconds
Started	Jan 10 01:10:18 PM PST 24
Finished	Jan 10 01:11:36 PM PST 24
Peak memory	217820 kb
Host	smart-772f1053-87b3-4947-bdb7-cddd1a3deb1b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419849687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.1419849687 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.1943255901
Short name	T127
Test name
Test status
Simulation time	144849436 ps
CPU time	2.79 seconds
Started	Jan 10 01:10:25 PM PST 24
Finished	Jan 10 01:11:45 PM PST 24
Peak memory	217700 kb
Host	smart-6eb9fc05-c379-4a80-b136-6bd5f3049149
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943255901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.19432 55901 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.kmac_intr_test.4213951736
Short name	T124
Test name
Test status
Simulation time	13212353 ps
CPU time	0.81 seconds
Started	Jan 10 01:10:36 PM PST 24
Finished	Jan 10 01:12:00 PM PST 24
Peak memory	217528 kb
Host	smart-27a860cf-6c83-4ef4-ba72-6aa98fab6c1d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213951736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.4213951736 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.kmac_intr_test.2019919122
Short name	T1127
Test name
Test status
Simulation time	15387618 ps
CPU time	0.81 seconds
Started	Jan 10 01:10:38 PM PST 24
Finished	Jan 10 01:12:02 PM PST 24
Peak memory	217604 kb
Host	smart-150f530f-4c58-40c9-9839-bafcecd925c7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019919122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.2019919122 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.kmac_intr_test.4084787682
Short name	T1147
Test name
Test status
Simulation time	29623701 ps
CPU time	0.81 seconds
Started	Jan 10 01:10:47 PM PST 24
Finished	Jan 10 01:12:10 PM PST 24
Peak memory	217604 kb
Host	smart-14cc88e2-d3e4-43a1-9020-902a23558498
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084787682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.4084787682 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.kmac_intr_test.1759619556
Short name	T1171
Test name
Test status
Simulation time	13730580 ps
CPU time	0.79 seconds
Started	Jan 10 01:10:50 PM PST 24
Finished	Jan 10 01:12:15 PM PST 24
Peak memory	217420 kb
Host	smart-c09d7434-b21a-4992-b55c-ff6b9dcc8b7f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759619556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.1759619556 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.kmac_intr_test.1955858103
Short name	T1193
Test name
Test status
Simulation time	20769219 ps
CPU time	0.79 seconds
Started	Jan 10 01:10:46 PM PST 24
Finished	Jan 10 01:12:10 PM PST 24
Peak memory	216908 kb
Host	smart-cbb81665-df7e-407a-bbca-1927a7635b39
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955858103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.1955858103 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.kmac_intr_test.1213192992
Short name	T1167
Test name
Test status
Simulation time	13588416 ps
CPU time	0.84 seconds
Started	Jan 10 01:10:37 PM PST 24
Finished	Jan 10 01:12:02 PM PST 24
Peak memory	217420 kb
Host	smart-7b5ca93c-be91-4ea0-ad55-8a1c6cc8a53e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213192992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.1213192992 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.kmac_intr_test.4186500247
Short name	T1198
Test name
Test status
Simulation time	124664064 ps
CPU time	0.8 seconds
Started	Jan 10 01:10:37 PM PST 24
Finished	Jan 10 01:12:01 PM PST 24
Peak memory	217564 kb
Host	smart-ba73f03c-517d-4edb-85cb-bc5bc9dcb85f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186500247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.4186500247 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.kmac_intr_test.2536363652
Short name	T1232
Test name
Test status
Simulation time	32482515 ps
CPU time	0.78 seconds
Started	Jan 10 01:10:46 PM PST 24
Finished	Jan 10 01:12:10 PM PST 24
Peak memory	217620 kb
Host	smart-3ee1a70c-b5a8-4be2-b59a-ebd21d60b1a6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536363652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.2536363652 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.kmac_intr_test.2173214205
Short name	T1180
Test name
Test status
Simulation time	54739044 ps
CPU time	0.83 seconds
Started	Jan 10 01:10:49 PM PST 24
Finished	Jan 10 01:12:16 PM PST 24
Peak memory	216748 kb
Host	smart-a6f72062-4e72-48c6-a2d9-9de39f6e8570
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173214205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.2173214205 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.kmac_intr_test.3557226096
Short name	T1208
Test name
Test status
Simulation time	15403640 ps
CPU time	0.82 seconds
Started	Jan 10 01:10:47 PM PST 24
Finished	Jan 10 01:12:14 PM PST 24
Peak memory	217624 kb
Host	smart-61fd580b-aa1d-4aa3-af10-23b3f65668fa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557226096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.3557226096 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.4130126278
Short name	T1238
Test name
Test status
Simulation time	158429800 ps
CPU time	8.64 seconds
Started	Jan 10 01:10:18 PM PST 24
Finished	Jan 10 01:11:42 PM PST 24
Peak memory	217812 kb
Host	smart-046b5b06-3aa7-48a6-8f85-8ffd65303e33
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130126278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.4130126 278 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.2598718424
Short name	T1121
Test name
Test status
Simulation time	39417015 ps
CPU time	1.01 seconds
Started	Jan 10 01:10:21 PM PST 24
Finished	Jan 10 01:11:38 PM PST 24
Peak memory	217616 kb
Host	smart-868cd84c-62c8-49c4-9f58-69b989d0cd4a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598718424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.2598718 424 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.432979097
Short name	T1187
Test name
Test status
Simulation time	108281926 ps
CPU time	1.67 seconds
Started	Jan 10 01:10:20 PM PST 24
Finished	Jan 10 01:11:40 PM PST 24
Peak memory	222772 kb
Host	smart-7c6a5d59-30da-46b5-bea1-af15256fd0d6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432979097 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.432979097 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_rw.4045433622
Short name	T1141
Test name
Test status
Simulation time	58259680 ps
CPU time	0.99 seconds
Started	Jan 10 01:10:17 PM PST 24
Finished	Jan 10 01:11:36 PM PST 24
Peak memory	217820 kb
Host	smart-5508bf63-fcce-42b9-8bd5-199e817724bb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045433622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.4045433622 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_intr_test.3988616075
Short name	T1254
Test name
Test status
Simulation time	42917484 ps
CPU time	0.8 seconds
Started	Jan 10 01:10:27 PM PST 24
Finished	Jan 10 01:11:45 PM PST 24
Peak memory	217536 kb
Host	smart-b7dc8a12-3e24-4a9e-a656-b381d653b5be
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988616075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.3988616075 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3196428701
Short name	T135
Test name
Test status
Simulation time	104445486 ps
CPU time	1.45 seconds
Started	Jan 10 01:10:20 PM PST 24
Finished	Jan 10 01:11:40 PM PST 24
Peak memory	217632 kb
Host	smart-a132cdce-93d4-46fa-86e7-f7ee7a658aa4
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196428701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia l_access.3196428701 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_walk.2568970038
Short name	T3
Test name
Test status
Simulation time	25850591 ps
CPU time	0.75 seconds
Started	Jan 10 01:10:21 PM PST 24
Finished	Jan 10 01:11:38 PM PST 24
Peak memory	216820 kb
Host	smart-f546a9b0-1535-4518-afa7-b9a1ded7ede9
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568970038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.2568970038 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2182985689
Short name	T67
Test name
Test status
Simulation time	91356066 ps
CPU time	2.35 seconds
Started	Jan 10 01:10:24 PM PST 24
Finished	Jan 10 01:11:44 PM PST 24
Peak memory	217764 kb
Host	smart-836b0475-aa33-490d-b360-e636c562eb26
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182985689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr _outstanding.2182985689 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.817577951
Short name	T1184
Test name
Test status
Simulation time	56144572 ps
CPU time	1.02 seconds
Started	Jan 10 01:10:20 PM PST 24
Finished	Jan 10 01:11:39 PM PST 24
Peak memory	224996 kb
Host	smart-6075a36d-4f4f-4abf-a05c-6e507da22c1a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817577951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_e rrors.817577951 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2403502224
Short name	T1207
Test name
Test status
Simulation time	136006087 ps
CPU time	3.36 seconds
Started	Jan 10 01:10:22 PM PST 24
Finished	Jan 10 01:11:41 PM PST 24
Peak memory	225264 kb
Host	smart-9bfeb0cf-6abc-4540-a487-83706a4e8890
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403502224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac _shadow_reg_errors_with_csr_rw.2403502224 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_errors.1345491843
Short name	T60
Test name
Test status
Simulation time	70523181 ps
CPU time	2.43 seconds
Started	Jan 10 01:10:24 PM PST 24
Finished	Jan 10 01:11:44 PM PST 24
Peak memory	217892 kb
Host	smart-81e7b3d9-8668-4ecb-bc19-d9bac0d4b94f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345491843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.1345491843 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.2107900652
Short name	T119
Test name
Test status
Simulation time	229036345 ps
CPU time	4.68 seconds
Started	Jan 10 01:10:20 PM PST 24
Finished	Jan 10 01:11:43 PM PST 24
Peak memory	217796 kb
Host	smart-0007f4f8-30d8-45a2-8108-c298a3412ffb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107900652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.21079 00652 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.kmac_intr_test.1260516635
Short name	T1125
Test name
Test status
Simulation time	44990712 ps
CPU time	0.8 seconds
Started	Jan 10 01:10:34 PM PST 24
Finished	Jan 10 01:11:58 PM PST 24
Peak memory	217580 kb
Host	smart-9539fd7e-3b2d-40d0-b273-07d3d97bfc2a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260516635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.1260516635 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.kmac_intr_test.119090439
Short name	T1239
Test name
Test status
Simulation time	71205015 ps
CPU time	0.8 seconds
Started	Jan 10 01:10:43 PM PST 24
Finished	Jan 10 01:12:06 PM PST 24
Peak memory	217452 kb
Host	smart-4be6101b-1df6-4c81-8efa-76e4b6285259
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119090439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.119090439 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.kmac_intr_test.3588186922
Short name	T2
Test name
Test status
Simulation time	20941218 ps
CPU time	0.83 seconds
Started	Jan 10 01:10:38 PM PST 24
Finished	Jan 10 01:12:02 PM PST 24
Peak memory	217524 kb
Host	smart-acbf52cf-7271-4f24-b277-d716a0685924
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588186922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.3588186922 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.kmac_intr_test.24204019
Short name	T1203
Test name
Test status
Simulation time	13020902 ps
CPU time	0.79 seconds
Started	Jan 10 01:10:38 PM PST 24
Finished	Jan 10 01:12:03 PM PST 24
Peak memory	217540 kb
Host	smart-32549d11-620d-446c-8b64-9ffb74d21592
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24204019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.24204019 +enable_mas king=1 +sw_key_masked=0
Directory	/workspace/43.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.kmac_intr_test.3524227738
Short name	T1235
Test name
Test status
Simulation time	53129138 ps
CPU time	0.87 seconds
Started	Jan 10 01:10:47 PM PST 24
Finished	Jan 10 01:12:11 PM PST 24
Peak memory	217436 kb
Host	smart-93b96eec-316c-47d9-a159-468e6abb8505
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524227738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.3524227738 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.kmac_intr_test.2314129789
Short name	T70
Test name
Test status
Simulation time	13492848 ps
CPU time	0.87 seconds
Started	Jan 10 01:10:48 PM PST 24
Finished	Jan 10 01:12:13 PM PST 24
Peak memory	216832 kb
Host	smart-b91db887-e576-4da8-bf52-b6f9e6b44854
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314129789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.2314129789 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.kmac_intr_test.4224077055
Short name	T1168
Test name
Test status
Simulation time	12912542 ps
CPU time	0.79 seconds
Started	Jan 10 01:10:54 PM PST 24
Finished	Jan 10 01:12:22 PM PST 24
Peak memory	217700 kb
Host	smart-d8a06021-1a28-4638-a5f4-8eeb247280ca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224077055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.4224077055 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.kmac_intr_test.749313224
Short name	T1224
Test name
Test status
Simulation time	33362001 ps
CPU time	0.78 seconds
Started	Jan 10 01:10:51 PM PST 24
Finished	Jan 10 01:12:15 PM PST 24
Peak memory	217428 kb
Host	smart-36d4b069-af08-49f5-ba53-001ae4450539
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749313224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.749313224 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.kmac_intr_test.293211241
Short name	T1244
Test name
Test status
Simulation time	161423517 ps
CPU time	0.81 seconds
Started	Jan 10 01:10:45 PM PST 24
Finished	Jan 10 01:12:09 PM PST 24
Peak memory	216824 kb
Host	smart-f0bd52dc-ffb1-4938-87f4-259244de4894
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293211241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.293211241 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3908524182
Short name	T62
Test name
Test status
Simulation time	101985251 ps
CPU time	2.21 seconds
Started	Jan 10 01:10:30 PM PST 24
Finished	Jan 10 01:11:54 PM PST 24
Peak memory	224820 kb
Host	smart-5a523b02-6e5f-45ae-9f46-47533dc1103a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908524182 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.3908524182 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_rw.4282304430
Short name	T1161
Test name
Test status
Simulation time	33049239 ps
CPU time	1.04 seconds
Started	Jan 10 01:10:10 PM PST 24
Finished	Jan 10 01:11:23 PM PST 24
Peak memory	217704 kb
Host	smart-510a89bb-46e7-4dc6-99c5-ceef39d8ca0c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282304430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.4282304430 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_intr_test.1473756793
Short name	T154
Test name
Test status
Simulation time	70097134 ps
CPU time	0.76 seconds
Started	Jan 10 01:10:14 PM PST 24
Finished	Jan 10 01:11:29 PM PST 24
Peak memory	217624 kb
Host	smart-e29375fb-2f44-4023-a6f7-0f3b134b77c9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473756793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.1473756793 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2533255985
Short name	T1129
Test name
Test status
Simulation time	42440314 ps
CPU time	2.37 seconds
Started	Jan 10 01:10:11 PM PST 24
Finished	Jan 10 01:11:26 PM PST 24
Peak memory	217148 kb
Host	smart-52c7c95a-e303-488b-84bf-6d1de038a0ae
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533255985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr _outstanding.2533255985 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.152364875
Short name	T66
Test name
Test status
Simulation time	33037714 ps
CPU time	1.06 seconds
Started	Jan 10 01:10:14 PM PST 24
Finished	Jan 10 01:11:28 PM PST 24
Peak memory	221864 kb
Host	smart-a08a5f9a-c4ba-4cc1-b7a1-644af7d35164
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152364875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_e rrors.152364875 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1236088426
Short name	T92
Test name
Test status
Simulation time	871269465 ps
CPU time	3.16 seconds
Started	Jan 10 01:10:20 PM PST 24
Finished	Jan 10 01:11:42 PM PST 24
Peak memory	225228 kb
Host	smart-82aebe8a-7f8f-4b88-8434-178af660c289
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236088426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac _shadow_reg_errors_with_csr_rw.1236088426 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_errors.1017091641
Short name	T1216
Test name
Test status
Simulation time	135930506 ps
CPU time	2.64 seconds
Started	Jan 10 01:10:18 PM PST 24
Finished	Jan 10 01:11:35 PM PST 24
Peak memory	217804 kb
Host	smart-b6b2ba29-1905-45d6-ae0c-ddb389d92848
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017091641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.1017091641 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2153959179
Short name	T120
Test name
Test status
Simulation time	193486673 ps
CPU time	2.37 seconds
Started	Jan 10 01:10:23 PM PST 24
Finished	Jan 10 01:11:41 PM PST 24
Peak memory	217852 kb
Host	smart-f92be4b0-fd01-441b-9349-f82325c435e3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153959179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.21539 59179 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2449516672
Short name	T1158
Test name
Test status
Simulation time	21649063 ps
CPU time	1.27 seconds
Started	Jan 10 01:10:21 PM PST 24
Finished	Jan 10 01:11:38 PM PST 24
Peak memory	220480 kb
Host	smart-349490e7-4e2c-4df5-a48c-20adabb7eed6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449516672 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.2449516672 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_rw.3453373121
Short name	T68
Test name
Test status
Simulation time	150566062 ps
CPU time	0.98 seconds
Started	Jan 10 01:10:30 PM PST 24
Finished	Jan 10 01:11:52 PM PST 24
Peak memory	221324 kb
Host	smart-0002b4b2-2a99-49d5-b16f-e64304758349
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453373121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3453373121 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_intr_test.3833252046
Short name	T125
Test name
Test status
Simulation time	14434501 ps
CPU time	0.82 seconds
Started	Jan 10 01:10:20 PM PST 24
Finished	Jan 10 01:11:39 PM PST 24
Peak memory	216760 kb
Host	smart-5109c92d-bf03-46c5-a0de-c26bc3f2f5d6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833252046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.3833252046 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2204503980
Short name	T50
Test name
Test status
Simulation time	401696419 ps
CPU time	1.65 seconds
Started	Jan 10 01:10:28 PM PST 24
Finished	Jan 10 01:11:48 PM PST 24
Peak memory	217996 kb
Host	smart-6f269cd5-c8c4-439e-894a-4066fc2d7afb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204503980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr _outstanding.2204503980 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1697245851
Short name	T91
Test name
Test status
Simulation time	60321421 ps
CPU time	1.37 seconds
Started	Jan 10 01:10:21 PM PST 24
Finished	Jan 10 01:11:37 PM PST 24
Peak memory	218412 kb
Host	smart-32060c10-132d-4b14-9143-a9f913b00f89
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697245851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_ errors.1697245851 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3921344012
Short name	T1247
Test name
Test status
Simulation time	106877063 ps
CPU time	3.04 seconds
Started	Jan 10 01:10:09 PM PST 24
Finished	Jan 10 01:11:23 PM PST 24
Peak memory	222004 kb
Host	smart-32369980-bfc8-4371-829d-6adfc85bd046
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921344012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac _shadow_reg_errors_with_csr_rw.3921344012 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_errors.1900285442
Short name	T1131
Test name
Test status
Simulation time	92597670 ps
CPU time	2.74 seconds
Started	Jan 10 01:10:26 PM PST 24
Finished	Jan 10 01:11:46 PM PST 24
Peak memory	217052 kb
Host	smart-e4dc587b-5e79-4b7c-bd6b-20c8afdfc630
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900285442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.1900285442 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.1735155082
Short name	T149
Test name
Test status
Simulation time	707079466 ps
CPU time	4.08 seconds
Started	Jan 10 01:10:18 PM PST 24
Finished	Jan 10 01:11:36 PM PST 24
Peak memory	217136 kb
Host	smart-d59d7410-8c6c-485d-baf5-3acf1353408b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735155082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.17351 55082 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1653117404
Short name	T57
Test name
Test status
Simulation time	21055774 ps
CPU time	1.34 seconds
Started	Jan 10 01:10:20 PM PST 24
Finished	Jan 10 01:11:40 PM PST 24
Peak memory	220340 kb
Host	smart-6ce50603-4a29-45bb-9771-c0c7b0691e88
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653117404 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.1653117404 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_rw.1258863872
Short name	T1185
Test name
Test status
Simulation time	13307922 ps
CPU time	0.91 seconds
Started	Jan 10 01:10:15 PM PST 24
Finished	Jan 10 01:11:30 PM PST 24
Peak memory	217564 kb
Host	smart-c987550c-4d0e-434b-97ad-640d336c45ae
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258863872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.1258863872 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_intr_test.2717131354
Short name	T1205
Test name
Test status
Simulation time	206804575 ps
CPU time	0.78 seconds
Started	Jan 10 01:10:21 PM PST 24
Finished	Jan 10 01:11:40 PM PST 24
Peak memory	216796 kb
Host	smart-4368e94b-813d-4ec9-8020-92e9e2f67a72
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717131354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.2717131354 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.4288224110
Short name	T1192
Test name
Test status
Simulation time	328953244 ps
CPU time	1.64 seconds
Started	Jan 10 01:10:15 PM PST 24
Finished	Jan 10 01:11:30 PM PST 24
Peak memory	217820 kb
Host	smart-5c8817f8-4818-4d77-81c6-f408c3f98a20
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288224110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr _outstanding.4288224110 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2508996094
Short name	T97
Test name
Test status
Simulation time	57961982 ps
CPU time	1.09 seconds
Started	Jan 10 01:10:23 PM PST 24
Finished	Jan 10 01:11:40 PM PST 24
Peak memory	217780 kb
Host	smart-5f71d33a-d6b8-4e61-a19e-f795a5d7a128
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508996094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_ errors.2508996094 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1573368078
Short name	T1174
Test name
Test status
Simulation time	76860571 ps
CPU time	1.94 seconds
Started	Jan 10 01:10:20 PM PST 24
Finished	Jan 10 01:11:41 PM PST 24
Peak memory	225280 kb
Host	smart-4446621d-2642-477b-9d3a-21585ca42d27
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573368078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac _shadow_reg_errors_with_csr_rw.1573368078 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_errors.1835409278
Short name	T1119
Test name
Test status
Simulation time	131731163 ps
CPU time	2.47 seconds
Started	Jan 10 01:10:15 PM PST 24
Finished	Jan 10 01:11:31 PM PST 24
Peak memory	217928 kb
Host	smart-42908afc-db09-49be-a425-749dcf5a1293
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835409278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.1835409278 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.2949226145
Short name	T147
Test name
Test status
Simulation time	473229964 ps
CPU time	4.25 seconds
Started	Jan 10 01:10:14 PM PST 24
Finished	Jan 10 01:11:36 PM PST 24
Peak memory	216956 kb
Host	smart-f6514046-a178-4853-ba7c-e027b5c67f24
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949226145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.29492 26145 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.12897028
Short name	T1246
Test name
Test status
Simulation time	34200186 ps
CPU time	1.78 seconds
Started	Jan 10 01:10:20 PM PST 24
Finished	Jan 10 01:11:41 PM PST 24
Peak memory	222992 kb
Host	smart-e4b99b7c-084f-466b-8d27-2a42406cb5ea
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12897028 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.12897028 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_rw.647500738
Short name	T1137
Test name
Test status
Simulation time	16242947 ps
CPU time	0.94 seconds
Started	Jan 10 01:10:24 PM PST 24
Finished	Jan 10 01:11:42 PM PST 24
Peak memory	217476 kb
Host	smart-1ec61f49-8987-4c51-8ea6-9438090f1294
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647500738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.647500738 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_intr_test.4068188991
Short name	T1155
Test name
Test status
Simulation time	17881179 ps
CPU time	0.83 seconds
Started	Jan 10 01:10:21 PM PST 24
Finished	Jan 10 01:11:37 PM PST 24
Peak memory	217436 kb
Host	smart-57195009-6daf-4a5f-ae37-4e59a14595ff
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068188991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.4068188991 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.149846792
Short name	T126
Test name
Test status
Simulation time	204403437 ps
CPU time	1.69 seconds
Started	Jan 10 01:10:15 PM PST 24
Finished	Jan 10 01:11:30 PM PST 24
Peak memory	217732 kb
Host	smart-0b7cd8ef-dde6-43d5-85e8-562417c9e209
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149846792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_ outstanding.149846792 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2917494455
Short name	T52
Test name
Test status
Simulation time	43315188 ps
CPU time	1.01 seconds
Started	Jan 10 01:10:22 PM PST 24
Finished	Jan 10 01:11:39 PM PST 24
Peak memory	217604 kb
Host	smart-37f4e32b-e2bd-473c-90ad-044bd1b5eea6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917494455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_ errors.2917494455 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2666473537
Short name	T1211
Test name
Test status
Simulation time	406098108 ps
CPU time	3.08 seconds
Started	Jan 10 01:10:11 PM PST 24
Finished	Jan 10 01:11:26 PM PST 24
Peak memory	216996 kb
Host	smart-bf25b704-7227-4da5-80a6-2f19fc637604
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666473537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac _shadow_reg_errors_with_csr_rw.2666473537 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_errors.627898883
Short name	T1116
Test name
Test status
Simulation time	80299181 ps
CPU time	2.88 seconds
Started	Jan 10 01:10:15 PM PST 24
Finished	Jan 10 01:11:31 PM PST 24
Peak memory	217984 kb
Host	smart-6785dbce-4182-4897-924f-37ccb256ecf3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627898883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.627898883 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.2196044070
Short name	T151
Test name
Test status
Simulation time	525373880 ps
CPU time	2.52 seconds
Started	Jan 10 01:10:21 PM PST 24
Finished	Jan 10 01:11:40 PM PST 24
Peak memory	216996 kb
Host	smart-5bc1e715-6089-44fa-b92b-9774f17a3ac6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196044070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.21960 44070 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1416903384
Short name	T1178
Test name
Test status
Simulation time	102154601 ps
CPU time	2.23 seconds
Started	Jan 10 01:10:19 PM PST 24
Finished	Jan 10 01:11:36 PM PST 24
Peak memory	221868 kb
Host	smart-b13efbfd-1e15-4760-9dd7-da76201b8786
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416903384 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.1416903384 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_rw.537963068
Short name	T123
Test name
Test status
Simulation time	84726674 ps
CPU time	1.14 seconds
Started	Jan 10 01:10:28 PM PST 24
Finished	Jan 10 01:11:49 PM PST 24
Peak memory	217876 kb
Host	smart-f65e8534-5fd4-4ca7-8730-619be38b63b2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537963068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.537963068 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_intr_test.1534584846
Short name	T63
Test name
Test status
Simulation time	21013702 ps
CPU time	0.78 seconds
Started	Jan 10 01:10:27 PM PST 24
Finished	Jan 10 01:11:45 PM PST 24
Peak memory	216648 kb
Host	smart-866b46fe-b1d0-4950-9ae0-aa4e85cbe749
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534584846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.1534584846 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.1858193061
Short name	T1128
Test name
Test status
Simulation time	206023865 ps
CPU time	1.72 seconds
Started	Jan 10 01:10:16 PM PST 24
Finished	Jan 10 01:11:36 PM PST 24
Peak memory	217816 kb
Host	smart-d612d39d-eee9-4dc4-9afa-671735bbcd26
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858193061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr _outstanding.1858193061 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1874388547
Short name	T1197
Test name
Test status
Simulation time	47518265 ps
CPU time	1.29 seconds
Started	Jan 10 01:10:17 PM PST 24
Finished	Jan 10 01:11:37 PM PST 24
Peak memory	218452 kb
Host	smart-4b636ad7-2193-4713-9428-fe0bca4ffb20
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874388547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_ errors.1874388547 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2748964050
Short name	T1157
Test name
Test status
Simulation time	2032817900 ps
CPU time	2.86 seconds
Started	Jan 10 01:10:12 PM PST 24
Finished	Jan 10 01:11:27 PM PST 24
Peak memory	220748 kb
Host	smart-a45b7076-5e2a-4dd0-a43f-9e64d394895d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748964050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac _shadow_reg_errors_with_csr_rw.2748964050 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_errors.2282986112
Short name	T1231
Test name
Test status
Simulation time	672107389 ps
CPU time	2.99 seconds
Started	Jan 10 01:10:27 PM PST 24
Finished	Jan 10 01:11:49 PM PST 24
Peak memory	217208 kb
Host	smart-7f7d104e-2227-42c1-a790-2b6b2bee084a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282986112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.2282986112 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.584100971
Short name	T1134
Test name
Test status
Simulation time	605996918 ps
CPU time	3.4 seconds
Started	Jan 10 01:10:26 PM PST 24
Finished	Jan 10 01:11:46 PM PST 24
Peak memory	217852 kb
Host	smart-cb7dc5c5-dc4d-4222-8cd9-f9dd0cde80cd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584100971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.584100 971 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_intg_err/latest

Test location	/workspace/coverage/default/0.kmac_alert_test.1053170895
Short name	T737
Test name
Test status
Simulation time	33357419 ps
CPU time	0.84 seconds
Started	Jan 10 12:50:04 PM PST 24
Finished	Jan 10 12:51:42 PM PST 24
Peak memory	220308 kb
Host	smart-8bcb4301-87f1-4802-a70f-4f6d1ecf2363
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053170895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.1053170895 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_alert_test/latest

Test location	/workspace/coverage/default/0.kmac_app.989949644
Short name	T346
Test name
Test status
Simulation time	15416456351 ps
CPU time	199.39 seconds
Started	Jan 10 12:50:07 PM PST 24
Finished	Jan 10 12:55:28 PM PST 24
Peak memory	245624 kb
Host	smart-5d4717c7-8f29-4ed6-960f-9a0d7284e286
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=989949644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.989949644 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_app/latest

Test location	/workspace/coverage/default/0.kmac_app_with_partial_data.3200395912
Short name	T805
Test name
Test status
Simulation time	19617694993 ps
CPU time	408.53 seconds
Started	Jan 10 12:50:06 PM PST 24
Finished	Jan 10 12:58:18 PM PST 24
Peak memory	255220 kb
Host	smart-5ee61965-8fb8-4231-a885-842006741372
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3200395912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.3200395912 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/0.kmac_burst_write.1461800134
Short name	T260
Test name
Test status
Simulation time	16092345244 ps
CPU time	1517.91 seconds
Started	Jan 10 12:50:06 PM PST 24
Finished	Jan 10 01:16:47 PM PST 24
Peak memory	243848 kb
Host	smart-01d36504-d6f4-4ae7-beb0-39ac958feb76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1461800134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.1461800134 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_burst_write/latest

Test location	/workspace/coverage/default/0.kmac_entropy_mode_error.741113443
Short name	T757
Test name
Test status
Simulation time	19609109 ps
CPU time	0.8 seconds
Started	Jan 10 12:50:05 PM PST 24
Finished	Jan 10 12:51:54 PM PST 24
Peak memory	219076 kb
Host	smart-adf5f54e-073e-4f5f-9e83-0389b27faf75
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=741113443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.741113443 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/0.kmac_entropy_ready_error.2263843289
Short name	T687
Test name
Test status
Simulation time	9522190200 ps
CPU time	53.64 seconds
Started	Jan 10 12:49:52 PM PST 24
Finished	Jan 10 12:52:11 PM PST 24
Peak memory	221876 kb
Host	smart-e01aa48b-7cc9-45e3-8e0a-902f771908ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2263843289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.2263843289 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/0.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/0.kmac_entropy_refresh.764166657
Short name	T1008
Test name
Test status
Simulation time	3733236449 ps
CPU time	111.29 seconds
Started	Jan 10 12:50:13 PM PST 24
Finished	Jan 10 12:53:36 PM PST 24
Peak memory	237408 kb
Host	smart-8b27efa0-47da-46a5-bcdc-7e05aab44648
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=764166657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.764166657 +enable_masking=1 +sw_ key_masked=0
Directory	/workspace/0.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/0.kmac_error.450628471
Short name	T1098
Test name
Test status
Simulation time	13321927659 ps
CPU time	186.66 seconds
Started	Jan 10 12:50:13 PM PST 24
Finished	Jan 10 12:54:51 PM PST 24
Peak memory	258720 kb
Host	smart-013ffea4-12ad-4e7b-8d72-e21936cf7bc1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=450628471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.450628471 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_error/latest

Test location	/workspace/coverage/default/0.kmac_key_error.2825557239
Short name	T584
Test name
Test status
Simulation time	2921554599 ps
CPU time	4.56 seconds
Started	Jan 10 12:50:03 PM PST 24
Finished	Jan 10 12:51:52 PM PST 24
Peak memory	219400 kb
Host	smart-cfbcce05-28b9-40bc-951c-074fef5c0aac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2825557239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.2825557239 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_key_error/latest

Test location	/workspace/coverage/default/0.kmac_lc_escalation.3370569841
Short name	T236
Test name
Test status
Simulation time	173728728 ps
CPU time	1.42 seconds
Started	Jan 10 12:50:07 PM PST 24
Finished	Jan 10 12:51:41 PM PST 24
Peak memory	220452 kb
Host	smart-a263fac5-d649-4a96-b385-bd4146058caa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3370569841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.3370569841 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/0.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/0.kmac_long_msg_and_output.3226636069
Short name	T524
Test name
Test status
Simulation time	50902973175 ps
CPU time	1507.97 seconds
Started	Jan 10 12:49:54 PM PST 24
Finished	Jan 10 01:16:29 PM PST 24
Peak memory	342992 kb
Host	smart-20e7ae37-fe20-4852-92d3-7abcbf2e742a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226636069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an d_output.3226636069 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/0.kmac_mubi.3822357654
Short name	T638
Test name
Test status
Simulation time	6321007440 ps
CPU time	126.09 seconds
Started	Jan 10 12:50:05 PM PST 24
Finished	Jan 10 12:53:59 PM PST 24
Peak memory	239156 kb
Host	smart-7b832e0d-458e-4bbc-bd95-fd612777fa58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3822357654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.3822357654 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_mubi/latest

Test location	/workspace/coverage/default/0.kmac_sec_cm.1498531777
Short name	T9
Test name
Test status
Simulation time	7995287255 ps
CPU time	49.12 seconds
Started	Jan 10 12:50:15 PM PST 24
Finished	Jan 10 12:52:34 PM PST 24
Peak memory	262792 kb
Host	smart-186146a3-e50f-4c81-8d44-9b52b00cb65f
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498531777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.1498531777 +enable_maski ng=1 +sw_key_masked=0
Directory	/workspace/0.kmac_sec_cm/latest

Test location	/workspace/coverage/default/0.kmac_sideload.3933510804
Short name	T1076
Test name
Test status
Simulation time	43840618275 ps
CPU time	440.55 seconds
Started	Jan 10 12:50:01 PM PST 24
Finished	Jan 10 12:58:54 PM PST 24
Peak memory	258748 kb
Host	smart-f73d1a55-2f8c-47f0-83f3-abe3d87217a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3933510804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.3933510804 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_sideload/latest

Test location	/workspace/coverage/default/0.kmac_smoke.3851780062
Short name	T367
Test name
Test status
Simulation time	3413621098 ps
CPU time	31.76 seconds
Started	Jan 10 12:50:00 PM PST 24
Finished	Jan 10 12:52:04 PM PST 24
Peak memory	227564 kb
Host	smart-898839ab-e653-488b-b1dc-9cc4ef185465
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3851780062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.3851780062 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_smoke/latest

Test location	/workspace/coverage/default/0.kmac_stress_all.568634311
Short name	T703
Test name
Test status
Simulation time	7482358673 ps
CPU time	711.17 seconds
Started	Jan 10 12:50:04 PM PST 24
Finished	Jan 10 01:03:59 PM PST 24
Peak memory	312492 kb
Host	smart-bbb52e65-1790-4a51-9309-d2b6d5c43a8b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=568634311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.568634311 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_stress_all/latest

Test location	/workspace/coverage/default/0.kmac_stress_all_with_rand_reset.1075047985
Short name	T1103
Test name
Test status
Simulation time	83421994536 ps
CPU time	1444.51 seconds
Started	Jan 10 12:50:04 PM PST 24
Finished	Jan 10 01:15:44 PM PST 24
Peak memory	322832 kb
Host	smart-9213ddbd-89c4-4284-af58-aaed59d8c7fd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1075047985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_rand_reset.1075047985 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_kmac.283639659
Short name	T314
Test name
Test status
Simulation time	268352221 ps
CPU time	6.25 seconds
Started	Jan 10 12:50:04 PM PST 24
Finished	Jan 10 12:51:54 PM PST 24
Peak memory	219268 kb
Host	smart-9d8c6727-fd20-46de-ab47-b36dfa41181f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283639659 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.kmac_test_vectors_kmac.283639659 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_kmac_xof.2754574448
Short name	T249
Test name
Test status
Simulation time	931187643 ps
CPU time	5.69 seconds
Started	Jan 10 12:50:04 PM PST 24
Finished	Jan 10 12:51:45 PM PST 24
Peak memory	220768 kb
Host	smart-049ab441-3a45-46cc-ba0a-e8224806c5bd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754574448 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.2754574448 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_224.4245621628
Short name	T1087
Test name
Test status
Simulation time	194052104813 ps
CPU time	2305.3 seconds
Started	Jan 10 12:49:57 PM PST 24
Finished	Jan 10 01:29:58 PM PST 24
Peak memory	399492 kb
Host	smart-ede192b1-5226-4cbd-829f-eb44146a28c3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4245621628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.4245621628 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_256.2356616585
Short name	T340
Test name
Test status
Simulation time	64756436456 ps
CPU time	1999.7 seconds
Started	Jan 10 12:50:06 PM PST 24
Finished	Jan 10 01:25:03 PM PST 24
Peak memory	398072 kb
Host	smart-a2209d82-b364-460c-aa0b-c46a5c159c00
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2356616585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.2356616585 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_384.3779752459
Short name	T408
Test name
Test status
Simulation time	56137082917 ps
CPU time	1613.87 seconds
Started	Jan 10 12:50:06 PM PST 24
Finished	Jan 10 01:18:51 PM PST 24
Peak memory	344296 kb
Host	smart-906d67a5-e1c8-401c-a13a-e4646c0bc496
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3779752459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.3779752459 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_512.2846876863
Short name	T654
Test name
Test status
Simulation time	43396999403 ps
CPU time	1082.41 seconds
Started	Jan 10 12:50:07 PM PST 24
Finished	Jan 10 01:09:46 PM PST 24
Peak memory	298516 kb
Host	smart-13af8732-e1da-4dc6-8a95-5ccdc05103dc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2846876863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.2846876863 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_shake_128.2842990495
Short name	T577
Test name
Test status
Simulation time	127429447989 ps
CPU time	5058.01 seconds
Started	Jan 10 12:50:07 PM PST 24
Finished	Jan 10 02:15:48 PM PST 24
Peak memory	659296 kb
Host	smart-804970fe-d548-4585-ad79-e01cf0454ca6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2842990495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.2842990495 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_shake_256.3108227942
Short name	T376
Test name
Test status
Simulation time	61611732360 ps
CPU time	4512.82 seconds
Started	Jan 10 12:50:07 PM PST 24
Finished	Jan 10 02:06:57 PM PST 24
Peak memory	569652 kb
Host	smart-b52faaf4-76fd-43f2-b9af-f0860a0f51f1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3108227942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.3108227942 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/1.kmac_alert_test.4286183061
Short name	T595
Test name
Test status
Simulation time	17437888 ps
CPU time	0.81 seconds
Started	Jan 10 12:51:54 PM PST 24
Finished	Jan 10 12:53:07 PM PST 24
Peak memory	218776 kb
Host	smart-9da59267-3902-4bc2-aebd-b3ab5637aecf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286183061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.4286183061 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_alert_test/latest

Test location	/workspace/coverage/default/1.kmac_app.722872254
Short name	T424
Test name
Test status
Simulation time	4042953909 ps
CPU time	128.53 seconds
Started	Jan 10 12:50:39 PM PST 24
Finished	Jan 10 12:54:37 PM PST 24
Peak memory	244004 kb
Host	smart-e2228b4a-1057-4943-b4ba-d6ffdcaf4b3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=722872254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.722872254 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_app/latest

Test location	/workspace/coverage/default/1.kmac_app_with_partial_data.2034121514
Short name	T304
Test name
Test status
Simulation time	25592102876 ps
CPU time	169.55 seconds
Started	Jan 10 12:50:07 PM PST 24
Finished	Jan 10 12:54:28 PM PST 24
Peak memory	241728 kb
Host	smart-43ac862c-26db-43ba-b19f-c9cfafc3f6b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2034121514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.2034121514 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/1.kmac_burst_write.2671481562
Short name	T173
Test name
Test status
Simulation time	21976905609 ps
CPU time	820.67 seconds
Started	Jan 10 12:51:36 PM PST 24
Finished	Jan 10 01:06:33 PM PST 24
Peak memory	243116 kb
Host	smart-084897f8-1ce2-49c5-8644-26f9abb74586
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2671481562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.2671481562 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_burst_write/latest

Test location	/workspace/coverage/default/1.kmac_edn_timeout_error.2550738755
Short name	T719
Test name
Test status
Simulation time	266251961 ps
CPU time	1.42 seconds
Started	Jan 10 12:50:08 PM PST 24
Finished	Jan 10 12:52:09 PM PST 24
Peak memory	219192 kb
Host	smart-a76137f7-be37-4fe2-8c88-f5f21eabe10f
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2550738755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.2550738755 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/1.kmac_entropy_mode_error.2885841922
Short name	T268
Test name
Test status
Simulation time	4256587597 ps
CPU time	26.54 seconds
Started	Jan 10 12:50:05 PM PST 24
Finished	Jan 10 12:52:14 PM PST 24
Peak memory	234820 kb
Host	smart-9457d471-de52-4402-acc2-5e9ab0245079
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2885841922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.2885841922 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/1.kmac_entropy_ready_error.175128033
Short name	T28
Test name
Test status
Simulation time	4997564869 ps
CPU time	52.63 seconds
Started	Jan 10 12:50:06 PM PST 24
Finished	Jan 10 12:52:41 PM PST 24
Peak memory	221580 kb
Host	smart-6a9c8fd3-de2d-424d-ac56-945073be0558
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=175128033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.175128033 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspace/1.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/1.kmac_entropy_refresh.700307285
Short name	T410
Test name
Test status
Simulation time	11362907964 ps
CPU time	146.32 seconds
Started	Jan 10 12:50:08 PM PST 24
Finished	Jan 10 12:54:26 PM PST 24
Peak memory	243944 kb
Host	smart-a279c2e4-02a3-4d00-9e53-cf5771df4297
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=700307285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.700307285 +enable_masking=1 +sw_ key_masked=0
Directory	/workspace/1.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/1.kmac_error.775194889
Short name	T1077
Test name
Test status
Simulation time	42996002631 ps
CPU time	254.84 seconds
Started	Jan 10 12:50:09 PM PST 24
Finished	Jan 10 12:56:02 PM PST 24
Peak memory	260188 kb
Host	smart-b2ae6cff-f5b5-41df-8ef3-f23cbc3b83b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=775194889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.775194889 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_error/latest

Test location	/workspace/coverage/default/1.kmac_key_error.2017197266
Short name	T590
Test name
Test status
Simulation time	498188863 ps
CPU time	3.56 seconds
Started	Jan 10 12:50:08 PM PST 24
Finished	Jan 10 12:51:55 PM PST 24
Peak memory	219260 kb
Host	smart-9257d6ba-0ca8-4ca5-9d13-0ac7f5612b93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2017197266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.2017197266 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_key_error/latest

Test location	/workspace/coverage/default/1.kmac_lc_escalation.2024271748
Short name	T337
Test name
Test status
Simulation time	81935233 ps
CPU time	1.29 seconds
Started	Jan 10 12:50:14 PM PST 24
Finished	Jan 10 12:51:51 PM PST 24
Peak memory	220304 kb
Host	smart-0d2a9d3b-cac1-48d0-9a6f-f0db3db68b7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2024271748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.2024271748 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/1.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/1.kmac_long_msg_and_output.2812539048
Short name	T240
Test name
Test status
Simulation time	90853532227 ps
CPU time	3047.94 seconds
Started	Jan 10 12:50:15 PM PST 24
Finished	Jan 10 01:42:33 PM PST 24
Peak memory	472580 kb
Host	smart-e3b20a0f-39e6-4402-92b0-91c87711625a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812539048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an d_output.2812539048 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/1.kmac_mubi.3851073835
Short name	T429
Test name
Test status
Simulation time	52109144821 ps
CPU time	307.16 seconds
Started	Jan 10 12:50:06 PM PST 24
Finished	Jan 10 12:56:47 PM PST 24
Peak memory	250704 kb
Host	smart-85ca6e33-220c-4c11-a3f2-6e09409bb1f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3851073835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.3851073835 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_mubi/latest

Test location	/workspace/coverage/default/1.kmac_sideload.548111385
Short name	T928
Test name
Test status
Simulation time	23242787889 ps
CPU time	195.35 seconds
Started	Jan 10 12:50:12 PM PST 24
Finished	Jan 10 12:55:14 PM PST 24
Peak memory	243892 kb
Host	smart-ed6a39b1-42a6-40d3-a247-ca125a1489c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=548111385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.548111385 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_sideload/latest

Test location	/workspace/coverage/default/1.kmac_smoke.40744662
Short name	T969
Test name
Test status
Simulation time	4668165883 ps
CPU time	64.66 seconds
Started	Jan 10 12:50:12 PM PST 24
Finished	Jan 10 12:52:40 PM PST 24
Peak memory	227384 kb
Host	smart-84591b7e-be5c-428a-b1bc-5a6060082a38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=40744662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.40744662 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_smoke/latest

Test location	/workspace/coverage/default/1.kmac_stress_all.460305025
Short name	T373
Test name
Test status
Simulation time	27762036363 ps
CPU time	353.23 seconds
Started	Jan 10 12:50:06 PM PST 24
Finished	Jan 10 12:57:32 PM PST 24
Peak memory	285064 kb
Host	smart-06e52d3c-446f-4b21-ae69-cae65656d8fc
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=460305025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.460305025 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_stress_all/latest

Test location	/workspace/coverage/default/1.kmac_stress_all_with_rand_reset.2714123030
Short name	T884
Test name
Test status
Simulation time	222677359597 ps
CPU time	493.38 seconds
Started	Jan 10 12:50:05 PM PST 24
Finished	Jan 10 01:00:16 PM PST 24
Peak memory	276860 kb
Host	smart-25bf783b-021f-4234-b761-5a8a47e42afb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2714123030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all_with_rand_reset.2714123030 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_kmac.329176787
Short name	T631
Test name
Test status
Simulation time	1324548147 ps
CPU time	6.71 seconds
Started	Jan 10 12:50:22 PM PST 24
Finished	Jan 10 12:52:04 PM PST 24
Peak memory	220712 kb
Host	smart-12ccef57-1db2-4fc0-a783-3442302c4833
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329176787 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.kmac_test_vectors_kmac.329176787 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_kmac_xof.3986307769
Short name	T721
Test name
Test status
Simulation time	387411115 ps
CPU time	5.53 seconds
Started	Jan 10 12:52:03 PM PST 24
Finished	Jan 10 12:53:23 PM PST 24
Peak memory	220640 kb
Host	smart-8568ac92-fc58-4e45-beb0-b6c83ac487a8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986307769 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.3986307769 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_224.2089065781
Short name	T950
Test name
Test status
Simulation time	69888187914 ps
CPU time	2212.64 seconds
Started	Jan 10 12:50:10 PM PST 24
Finished	Jan 10 01:28:35 PM PST 24
Peak memory	400400 kb
Host	smart-ff27d4a3-1ffa-4eab-a761-fc9e189a442a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2089065781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.2089065781 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_256.2880486984
Short name	T795
Test name
Test status
Simulation time	160097581662 ps
CPU time	2072.82 seconds
Started	Jan 10 12:50:08 PM PST 24
Finished	Jan 10 01:26:41 PM PST 24
Peak memory	376288 kb
Host	smart-11326bab-b4d2-445d-8bc8-e2b7b1a91b8c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2880486984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.2880486984 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_384.2874117095
Short name	T4
Test name
Test status
Simulation time	272560569726 ps
CPU time	1850.24 seconds
Started	Jan 10 12:50:06 PM PST 24
Finished	Jan 10 01:22:30 PM PST 24
Peak memory	342580 kb
Host	smart-9747a309-313b-4cdd-bc39-df5b0c617afa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2874117095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.2874117095 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_512.2684524101
Short name	T112
Test name
Test status
Simulation time	50818824517 ps
CPU time	1147.67 seconds
Started	Jan 10 12:50:15 PM PST 24
Finished	Jan 10 01:10:43 PM PST 24
Peak memory	305692 kb
Host	smart-41682e52-bca4-4c3e-b544-36b750ccea54
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2684524101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.2684524101 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_shake_128.2057341389
Short name	T1011
Test name
Test status
Simulation time	253583207879 ps
CPU time	5004.34 seconds
Started	Jan 10 12:50:03 PM PST 24
Finished	Jan 10 02:14:51 PM PST 24
Peak memory	668924 kb
Host	smart-6a7fa415-ab70-4d00-adfc-e3f95fa27ea3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2057341389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.2057341389 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_shake_256.1665691908
Short name	T285
Test name
Test status
Simulation time	62979268645 ps
CPU time	4609.69 seconds
Started	Jan 10 12:50:01 PM PST 24
Finished	Jan 10 02:08:32 PM PST 24
Peak memory	578856 kb
Host	smart-13003ae2-cb90-4dd4-8c2b-cff116336ad0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1665691908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.1665691908 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/10.kmac_alert_test.2117110258
Short name	T801
Test name
Test status
Simulation time	59415225 ps
CPU time	0.82 seconds
Started	Jan 10 12:51:12 PM PST 24
Finished	Jan 10 12:52:31 PM PST 24
Peak memory	218936 kb
Host	smart-7f319dcd-2107-4b0c-8409-f5eddccbbfcc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117110258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.2117110258 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_alert_test/latest

Test location	/workspace/coverage/default/10.kmac_burst_write.690648515
Short name	T600
Test name
Test status
Simulation time	41246687041 ps
CPU time	395.51 seconds
Started	Jan 10 12:50:53 PM PST 24
Finished	Jan 10 12:58:52 PM PST 24
Peak memory	234364 kb
Host	smart-d275f48a-f494-4d86-afae-e3c8b52f140f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=690648515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.690648515 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_burst_write/latest

Test location	/workspace/coverage/default/10.kmac_edn_timeout_error.2031892571
Short name	T975
Test name
Test status
Simulation time	471341335 ps
CPU time	34.32 seconds
Started	Jan 10 12:50:36 PM PST 24
Finished	Jan 10 12:52:32 PM PST 24
Peak memory	228904 kb
Host	smart-92ff09e1-f74f-4303-84d6-64cf8292e4a1
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2031892571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.2031892571 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/10.kmac_entropy_mode_error.236577516
Short name	T1079
Test name
Test status
Simulation time	67989381 ps
CPU time	1.07 seconds
Started	Jan 10 12:50:45 PM PST 24
Finished	Jan 10 12:52:27 PM PST 24
Peak memory	219288 kb
Host	smart-43516668-5daa-472c-b233-5eb4cf852d58
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=236577516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.236577516 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/10.kmac_entropy_refresh.2527447742
Short name	T368
Test name
Test status
Simulation time	8235408108 ps
CPU time	380.11 seconds
Started	Jan 10 12:51:14 PM PST 24
Finished	Jan 10 12:58:54 PM PST 24
Peak memory	256080 kb
Host	smart-3844de6c-e395-4fd7-82f4-7413f789d01e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2527447742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.2527447742 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/10.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/10.kmac_error.4053773355
Short name	T1105
Test name
Test status
Simulation time	6759358240 ps
CPU time	117.14 seconds
Started	Jan 10 12:51:13 PM PST 24
Finished	Jan 10 12:54:25 PM PST 24
Peak memory	252064 kb
Host	smart-308d752e-dae7-421b-988c-c46f1d4c06aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4053773355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.4053773355 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_error/latest

Test location	/workspace/coverage/default/10.kmac_key_error.3326994560
Short name	T25
Test name
Test status
Simulation time	3145417959 ps
CPU time	4.23 seconds
Started	Jan 10 12:50:37 PM PST 24
Finished	Jan 10 12:52:00 PM PST 24
Peak memory	219316 kb
Host	smart-ef1a2d09-adef-4eb7-8241-1bcb6febf4ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3326994560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.3326994560 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_key_error/latest

Test location	/workspace/coverage/default/10.kmac_long_msg_and_output.702359205
Short name	T1026
Test name
Test status
Simulation time	36039982804 ps
CPU time	891.91 seconds
Started	Jan 10 12:51:18 PM PST 24
Finished	Jan 10 01:07:40 PM PST 24
Peak memory	296988 kb
Host	smart-808df24e-9d57-485d-b969-d0561af4bff8
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702359205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_an d_output.702359205 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/10.kmac_sideload.1300448282
Short name	T908
Test name
Test status
Simulation time	17946686128 ps
CPU time	411.59 seconds
Started	Jan 10 12:50:59 PM PST 24
Finished	Jan 10 12:59:16 PM PST 24
Peak memory	255380 kb
Host	smart-15231167-0666-42bd-bafa-d4cc094164bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1300448282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.1300448282 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_sideload/latest

Test location	/workspace/coverage/default/10.kmac_smoke.1670270396
Short name	T996
Test name
Test status
Simulation time	1821811183 ps
CPU time	33.34 seconds
Started	Jan 10 12:50:35 PM PST 24
Finished	Jan 10 12:52:22 PM PST 24
Peak memory	225008 kb
Host	smart-fa208b45-1dd6-4498-b7d8-c58704e85a30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1670270396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.1670270396 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_smoke/latest

Test location	/workspace/coverage/default/10.kmac_stress_all.2743281273
Short name	T440
Test name
Test status
Simulation time	546494685368 ps
CPU time	1615.12 seconds
Started	Jan 10 12:50:48 PM PST 24
Finished	Jan 10 01:18:59 PM PST 24
Peak memory	350660 kb
Host	smart-524a3885-d19c-4ee4-aa47-7f7dfd03bd67
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2743281273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.2743281273 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_stress_all/latest

Test location	/workspace/coverage/default/10.kmac_stress_all_with_rand_reset.3046766911
Short name	T189
Test name
Test status
Simulation time	5316365934 ps
CPU time	172.49 seconds
Started	Jan 10 12:50:51 PM PST 24
Finished	Jan 10 12:55:07 PM PST 24
Peak memory	256328 kb
Host	smart-f3331383-c7a6-4db6-999c-549d8a056dcc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3046766911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all_with_rand_reset.3046766911 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_kmac.344939035
Short name	T984
Test name
Test status
Simulation time	129995519 ps
CPU time	5.69 seconds
Started	Jan 10 12:50:57 PM PST 24
Finished	Jan 10 12:53:04 PM PST 24
Peak memory	219444 kb
Host	smart-20be6aff-4977-4b2f-8ad9-31154e5823a3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344939035 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 10.kmac_test_vectors_kmac.344939035 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_kmac_xof.3100222839
Short name	T966
Test name
Test status
Simulation time	1032129293 ps
CPU time	6.97 seconds
Started	Jan 10 12:50:44 PM PST 24
Finished	Jan 10 12:52:14 PM PST 24
Peak memory	220708 kb
Host	smart-e5938ac3-9cf4-4e01-8fac-12bf5fd44717
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100222839 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_kmac_xof.3100222839 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_224.3677256304
Short name	T635
Test name
Test status
Simulation time	129239213237 ps
CPU time	2151.45 seconds
Started	Jan 10 12:51:13 PM PST 24
Finished	Jan 10 01:28:25 PM PST 24
Peak memory	398296 kb
Host	smart-2046ba75-10e0-40bc-9243-d0f0f6af4649
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3677256304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.3677256304 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_256.2626223013
Short name	T826
Test name
Test status
Simulation time	181805038479 ps
CPU time	2181.4 seconds
Started	Jan 10 12:50:42 PM PST 24
Finished	Jan 10 01:28:28 PM PST 24
Peak memory	392244 kb
Host	smart-8ff6c7f9-e9ab-4459-b362-db5bffcab637
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2626223013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.2626223013 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_384.2148743980
Short name	T490
Test name
Test status
Simulation time	38958221924 ps
CPU time	1402.05 seconds
Started	Jan 10 12:50:47 PM PST 24
Finished	Jan 10 01:15:26 PM PST 24
Peak memory	345320 kb
Host	smart-80a10a5d-366b-4b7c-9347-1e7f1e84dd72
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2148743980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.2148743980 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_512.1550247756
Short name	T980
Test name
Test status
Simulation time	35951462835 ps
CPU time	1299.59 seconds
Started	Jan 10 12:50:41 PM PST 24
Finished	Jan 10 01:13:34 PM PST 24
Peak memory	307480 kb
Host	smart-fed1d350-82f2-4eb5-8a0b-a0d6c49d74d2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1550247756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.1550247756 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_shake_128.3732384561
Short name	T443
Test name
Test status
Simulation time	227590926148 ps
CPU time	5735.06 seconds
Started	Jan 10 12:50:57 PM PST 24
Finished	Jan 10 02:27:50 PM PST 24
Peak memory	653496 kb
Host	smart-a21f2ddc-bf02-49c2-a537-cbf705943796
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3732384561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.3732384561 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_shake_256.980543312
Short name	T500
Test name
Test status
Simulation time	815189014572 ps
CPU time	5324.47 seconds
Started	Jan 10 12:50:38 PM PST 24
Finished	Jan 10 02:20:48 PM PST 24
Peak memory	585880 kb
Host	smart-11e223bd-29dd-47c3-9c98-08e64a238128
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=980543312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.980543312 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/11.kmac_alert_test.2670130870
Short name	T328
Test name
Test status
Simulation time	123705583 ps
CPU time	0.84 seconds
Started	Jan 10 12:50:52 PM PST 24
Finished	Jan 10 12:52:28 PM PST 24
Peak memory	220320 kb
Host	smart-bef8b7cb-b58b-4de7-9b77-7a9c9d41073e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670130870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.2670130870 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_alert_test/latest

Test location	/workspace/coverage/default/11.kmac_app.191129400
Short name	T414
Test name
Test status
Simulation time	5006406697 ps
CPU time	100.27 seconds
Started	Jan 10 12:51:04 PM PST 24
Finished	Jan 10 12:54:06 PM PST 24
Peak memory	233752 kb
Host	smart-69f8685f-7969-4f62-af6a-29cba21d0081
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=191129400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.191129400 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_app/latest

Test location	/workspace/coverage/default/11.kmac_burst_write.1211955209
Short name	T288
Test name
Test status
Simulation time	108715084744 ps
CPU time	1227.4 seconds
Started	Jan 10 12:50:54 PM PST 24
Finished	Jan 10 01:12:35 PM PST 24
Peak memory	240792 kb
Host	smart-946603c6-08e4-483e-b4ff-e358dd7e861c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1211955209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.1211955209 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_burst_write/latest

Test location	/workspace/coverage/default/11.kmac_edn_timeout_error.3933360301
Short name	T1090
Test name
Test status
Simulation time	405990566 ps
CPU time	33.38 seconds
Started	Jan 10 12:51:18 PM PST 24
Finished	Jan 10 12:53:25 PM PST 24
Peak memory	243652 kb
Host	smart-24299c1b-5bd8-43a8-bfe7-db6b537b0b5d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3933360301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.3933360301 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/11.kmac_entropy_refresh.2928321027
Short name	T276
Test name
Test status
Simulation time	68083381080 ps
CPU time	334.68 seconds
Started	Jan 10 12:50:47 PM PST 24
Finished	Jan 10 12:58:03 PM PST 24
Peak memory	252044 kb
Host	smart-a36b80c9-4d72-4d25-8708-b0bdb9d61e39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2928321027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.2928321027 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/11.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/11.kmac_error.1496587710
Short name	T681
Test name
Test status
Simulation time	7239964237 ps
CPU time	455.1 seconds
Started	Jan 10 12:51:14 PM PST 24
Finished	Jan 10 01:00:03 PM PST 24
Peak memory	275040 kb
Host	smart-842df6d6-7942-4a77-9d22-3b38e603e065
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1496587710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.1496587710 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_error/latest

Test location	/workspace/coverage/default/11.kmac_key_error.2203894352
Short name	T891
Test name
Test status
Simulation time	215423370 ps
CPU time	1.88 seconds
Started	Jan 10 12:51:21 PM PST 24
Finished	Jan 10 12:52:42 PM PST 24
Peak memory	219200 kb
Host	smart-0f072709-8971-4ae9-af99-91bff2ada5c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2203894352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.2203894352 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_key_error/latest

Test location	/workspace/coverage/default/11.kmac_lc_escalation.3692966078
Short name	T251
Test name
Test status
Simulation time	122819164 ps
CPU time	1.43 seconds
Started	Jan 10 12:51:20 PM PST 24
Finished	Jan 10 12:52:40 PM PST 24
Peak memory	220356 kb
Host	smart-38e522cf-f1a9-49f1-b32b-8308e9e68c1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3692966078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.3692966078 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/11.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/11.kmac_long_msg_and_output.3707431129
Short name	T300
Test name
Test status
Simulation time	6329633195 ps
CPU time	151.67 seconds
Started	Jan 10 12:50:44 PM PST 24
Finished	Jan 10 12:54:39 PM PST 24
Peak memory	242124 kb
Host	smart-eacc7921-52be-4946-abc5-f652b9e8b4c5
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707431129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a nd_output.3707431129 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/11.kmac_sideload.2660803942
Short name	T169
Test name
Test status
Simulation time	17386304176 ps
CPU time	135.62 seconds
Started	Jan 10 12:50:59 PM PST 24
Finished	Jan 10 12:54:28 PM PST 24
Peak memory	238724 kb
Host	smart-683106ec-484d-4444-b26e-d9ef60d54e92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2660803942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.2660803942 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_sideload/latest

Test location	/workspace/coverage/default/11.kmac_smoke.2246468328
Short name	T1022
Test name
Test status
Simulation time	1261161076 ps
CPU time	23.13 seconds
Started	Jan 10 12:50:47 PM PST 24
Finished	Jan 10 12:52:51 PM PST 24
Peak memory	221848 kb
Host	smart-1c79b824-5a3d-4fd0-8d16-de1ca4fc3074
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2246468328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.2246468328 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_smoke/latest

Test location	/workspace/coverage/default/11.kmac_stress_all_with_rand_reset.2705660453
Short name	T978
Test name
Test status
Simulation time	52053591851 ps
CPU time	976.67 seconds
Started	Jan 10 12:50:55 PM PST 24
Finished	Jan 10 01:08:36 PM PST 24
Peak memory	293420 kb
Host	smart-73389c82-1f4e-4f22-b59d-a714aa17900c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2705660453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all_with_rand_reset.2705660453 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_kmac.743341785
Short name	T992
Test name
Test status
Simulation time	186602065 ps
CPU time	5.33 seconds
Started	Jan 10 12:51:25 PM PST 24
Finished	Jan 10 12:52:55 PM PST 24
Peak memory	219232 kb
Host	smart-617f8116-9886-401a-a34f-03b4afb18c6d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743341785 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 11.kmac_test_vectors_kmac.743341785 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_kmac_xof.1710361819
Short name	T735
Test name
Test status
Simulation time	105729743 ps
CPU time	5.11 seconds
Started	Jan 10 12:50:47 PM PST 24
Finished	Jan 10 12:52:15 PM PST 24
Peak memory	219184 kb
Host	smart-01221953-9c0a-4f62-a3d3-a8e0e8ee3a69
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710361819 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_kmac_xof.1710361819 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_224.1093848998
Short name	T1055
Test name
Test status
Simulation time	651278382087 ps
CPU time	2442.26 seconds
Started	Jan 10 12:50:57 PM PST 24
Finished	Jan 10 01:32:57 PM PST 24
Peak memory	400968 kb
Host	smart-ff14ab2e-0c3d-447d-b7ad-34dd47b3a559
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1093848998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.1093848998 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_256.773028424
Short name	T282
Test name
Test status
Simulation time	145396520114 ps
CPU time	2089.62 seconds
Started	Jan 10 12:50:55 PM PST 24
Finished	Jan 10 01:27:09 PM PST 24
Peak memory	377016 kb
Host	smart-468da039-bcc1-47f0-9c27-49d2fff04c15
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=773028424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.773028424 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_384.1430083310
Short name	T711
Test name
Test status
Simulation time	60675388340 ps
CPU time	1541.28 seconds
Started	Jan 10 12:50:54 PM PST 24
Finished	Jan 10 01:18:01 PM PST 24
Peak memory	346704 kb
Host	smart-9b20cd13-b396-4ee3-afa8-994a67688195
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1430083310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.1430083310 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_512.2677993928
Short name	T196
Test name
Test status
Simulation time	206177500057 ps
CPU time	1302.43 seconds
Started	Jan 10 12:51:19 PM PST 24
Finished	Jan 10 01:14:23 PM PST 24
Peak memory	304232 kb
Host	smart-48db92a7-fa80-46e1-ac4b-7441b2c9af7a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2677993928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.2677993928 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_shake_128.2248294108
Short name	T365
Test name
Test status
Simulation time	62701322830 ps
CPU time	4773.57 seconds
Started	Jan 10 12:50:47 PM PST 24
Finished	Jan 10 02:11:39 PM PST 24
Peak memory	660940 kb
Host	smart-047e2dba-1262-4591-8b22-3c1c1dcbaf28
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2248294108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.2248294108 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_shake_256.1139689729
Short name	T903
Test name
Test status
Simulation time	163005120522 ps
CPU time	4897.7 seconds
Started	Jan 10 12:50:51 PM PST 24
Finished	Jan 10 02:13:45 PM PST 24
Peak memory	570612 kb
Host	smart-35f396bd-32a7-4e8b-830f-ca08123efea0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1139689729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.1139689729 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/12.kmac_alert_test.1955393054
Short name	T482
Test name
Test status
Simulation time	58554706 ps
CPU time	0.84 seconds
Started	Jan 10 12:51:03 PM PST 24
Finished	Jan 10 12:52:27 PM PST 24
Peak memory	219228 kb
Host	smart-1f42ae6b-1a0c-4ac6-b4d9-74c8068ab62a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955393054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.1955393054 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_alert_test/latest

Test location	/workspace/coverage/default/12.kmac_app.1529770361
Short name	T535
Test name
Test status
Simulation time	16266588753 ps
CPU time	377.06 seconds
Started	Jan 10 12:50:47 PM PST 24
Finished	Jan 10 12:58:17 PM PST 24
Peak memory	255212 kb
Host	smart-e217376b-4769-450a-b02b-f59205b421e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1529770361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.1529770361 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_app/latest

Test location	/workspace/coverage/default/12.kmac_burst_write.3908242298
Short name	T378
Test name
Test status
Simulation time	73909065228 ps
CPU time	657.58 seconds
Started	Jan 10 12:50:58 PM PST 24
Finished	Jan 10 01:03:12 PM PST 24
Peak memory	236300 kb
Host	smart-42828c88-4471-4e80-93d3-140405e700af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3908242298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.3908242298 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_burst_write/latest

Test location	/workspace/coverage/default/12.kmac_edn_timeout_error.3522721433
Short name	T253
Test name
Test status
Simulation time	6763458824 ps
CPU time	36.28 seconds
Started	Jan 10 12:51:04 PM PST 24
Finished	Jan 10 12:52:58 PM PST 24
Peak memory	243828 kb
Host	smart-952459f8-c95f-4b91-b628-29e187c93e8f
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3522721433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.3522721433 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/12.kmac_entropy_mode_error.2349057386
Short name	T1046
Test name
Test status
Simulation time	43683408 ps
CPU time	1.22 seconds
Started	Jan 10 12:50:59 PM PST 24
Finished	Jan 10 12:52:34 PM PST 24
Peak memory	219236 kb
Host	smart-fa57b31f-2050-427f-9000-e03d0a68afbc
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2349057386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.2349057386 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/12.kmac_entropy_refresh.791041872
Short name	T79
Test name
Test status
Simulation time	882859316 ps
CPU time	24.96 seconds
Started	Jan 10 12:51:10 PM PST 24
Finished	Jan 10 12:52:57 PM PST 24
Peak memory	240304 kb
Host	smart-2af65d03-f7f8-4545-805a-e4cb3ac7bcf9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=791041872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.791041872 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/12.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/12.kmac_error.3157956214
Short name	T670
Test name
Test status
Simulation time	13855645121 ps
CPU time	454.35 seconds
Started	Jan 10 12:50:58 PM PST 24
Finished	Jan 10 12:59:49 PM PST 24
Peak memory	259512 kb
Host	smart-c494c7b0-2e54-4cc8-ab23-e0814e1235b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3157956214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.3157956214 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_error/latest

Test location	/workspace/coverage/default/12.kmac_key_error.3501522162
Short name	T552
Test name
Test status
Simulation time	6676068586 ps
CPU time	8.33 seconds
Started	Jan 10 12:51:13 PM PST 24
Finished	Jan 10 12:52:41 PM PST 24
Peak memory	219380 kb
Host	smart-aaec772b-e8e3-4850-ae38-427172d76da5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3501522162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3501522162 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_key_error/latest

Test location	/workspace/coverage/default/12.kmac_lc_escalation.2574730415
Short name	T949
Test name
Test status
Simulation time	67520344 ps
CPU time	1.38 seconds
Started	Jan 10 12:50:59 PM PST 24
Finished	Jan 10 12:52:30 PM PST 24
Peak memory	221368 kb
Host	smart-4cafe0ea-e6c5-4b34-a6f0-60a6c7a9481e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2574730415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.2574730415 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/12.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/12.kmac_long_msg_and_output.1100612622
Short name	T664
Test name
Test status
Simulation time	50060082468 ps
CPU time	1724.01 seconds
Started	Jan 10 12:50:49 PM PST 24
Finished	Jan 10 01:21:20 PM PST 24
Peak memory	361788 kb
Host	smart-7a0619a9-b2be-4e4c-ab14-12dfe0be8cb5
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100612622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a nd_output.1100612622 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/12.kmac_sideload.705924657
Short name	T997
Test name
Test status
Simulation time	85889637292 ps
CPU time	518.81 seconds
Started	Jan 10 12:51:15 PM PST 24
Finished	Jan 10 01:01:24 PM PST 24
Peak memory	260780 kb
Host	smart-405f4e96-ff5a-4d47-bc19-f2cdc7c843dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=705924657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.705924657 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_sideload/latest

Test location	/workspace/coverage/default/12.kmac_smoke.1094407072
Short name	T1078
Test name
Test status
Simulation time	991492712 ps
CPU time	5.92 seconds
Started	Jan 10 12:51:16 PM PST 24
Finished	Jan 10 12:52:42 PM PST 24
Peak memory	227364 kb
Host	smart-62c1727f-9d08-4a1e-93ea-b844136ea77c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1094407072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.1094407072 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_smoke/latest

Test location	/workspace/coverage/default/12.kmac_stress_all.1942717037
Short name	T396
Test name
Test status
Simulation time	15525451780 ps
CPU time	520.25 seconds
Started	Jan 10 12:51:04 PM PST 24
Finished	Jan 10 01:01:05 PM PST 24
Peak memory	284820 kb
Host	smart-13d3a1cf-e705-46de-9511-406b12ba1947
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1942717037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.1942717037 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_stress_all/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_kmac.3058934815
Short name	T673
Test name
Test status
Simulation time	241925200 ps
CPU time	6.22 seconds
Started	Jan 10 12:51:13 PM PST 24
Finished	Jan 10 12:52:35 PM PST 24
Peak memory	219276 kb
Host	smart-a032cbb8-44ac-4163-b634-2ba19261ffc6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058934815 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 12.kmac_test_vectors_kmac.3058934815 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_kmac_xof.2621875268
Short name	T900
Test name
Test status
Simulation time	1170181801 ps
CPU time	6.42 seconds
Started	Jan 10 12:50:50 PM PST 24
Finished	Jan 10 12:52:08 PM PST 24
Peak memory	220608 kb
Host	smart-a96f3f20-51a7-4d2f-b8bd-eed165c6e796
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621875268 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_kmac_xof.2621875268 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_224.214875918
Short name	T456
Test name
Test status
Simulation time	137581578455 ps
CPU time	2109.69 seconds
Started	Jan 10 12:50:50 PM PST 24
Finished	Jan 10 01:27:12 PM PST 24
Peak memory	392284 kb
Host	smart-65e6c562-b11e-4a35-b36e-98faa0552dad
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=214875918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.214875918 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_256.2548631375
Short name	T642
Test name
Test status
Simulation time	1540213424502 ps
CPU time	2744.93 seconds
Started	Jan 10 12:51:18 PM PST 24
Finished	Jan 10 01:38:29 PM PST 24
Peak memory	390972 kb
Host	smart-4ef2395f-49ea-4633-9b7b-19fcb0d48767
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2548631375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.2548631375 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_384.2752243231
Short name	T377
Test name
Test status
Simulation time	255745075221 ps
CPU time	1658.4 seconds
Started	Jan 10 12:50:56 PM PST 24
Finished	Jan 10 01:19:54 PM PST 24
Peak memory	341472 kb
Host	smart-00a58a93-28f5-4cc2-8d17-118a99402397
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2752243231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.2752243231 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_512.2240349033
Short name	T929
Test name
Test status
Simulation time	176435924305 ps
CPU time	1378.3 seconds
Started	Jan 10 12:50:54 PM PST 24
Finished	Jan 10 01:15:09 PM PST 24
Peak memory	303196 kb
Host	smart-20eff25d-da31-4b56-91f2-e14629743a84
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2240349033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.2240349033 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_shake_128.3951163581
Short name	T752
Test name
Test status
Simulation time	178472302585 ps
CPU time	5797.79 seconds
Started	Jan 10 12:50:56 PM PST 24
Finished	Jan 10 02:28:54 PM PST 24
Peak memory	658132 kb
Host	smart-74721950-253a-4be0-b73c-2d804890db87
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3951163581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.3951163581 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_shake_256.3742527742
Short name	T348
Test name
Test status
Simulation time	447395994133 ps
CPU time	5525.84 seconds
Started	Jan 10 12:50:53 PM PST 24
Finished	Jan 10 02:24:11 PM PST 24
Peak memory	588060 kb
Host	smart-c42c9404-ce28-40cf-bc71-badd1dd9d84e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3742527742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.3742527742 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/13.kmac_alert_test.230145480
Short name	T930
Test name
Test status
Simulation time	18837356 ps
CPU time	0.88 seconds
Started	Jan 10 12:51:02 PM PST 24
Finished	Jan 10 12:52:21 PM PST 24
Peak memory	219096 kb
Host	smart-57d05586-2e30-4394-8549-f1f76ebad416
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230145480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.230145480 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_alert_test/latest

Test location	/workspace/coverage/default/13.kmac_app.179578134
Short name	T1036
Test name
Test status
Simulation time	50623497114 ps
CPU time	279.75 seconds
Started	Jan 10 12:51:12 PM PST 24
Finished	Jan 10 12:57:09 PM PST 24
Peak memory	250416 kb
Host	smart-227a5b37-ae99-4ced-8b0a-18d41dab5890
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=179578134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.179578134 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_app/latest

Test location	/workspace/coverage/default/13.kmac_burst_write.133074588
Short name	T700
Test name
Test status
Simulation time	96303424721 ps
CPU time	937.12 seconds
Started	Jan 10 12:50:55 PM PST 24
Finished	Jan 10 01:07:48 PM PST 24
Peak memory	243844 kb
Host	smart-21b67b13-1364-40c8-8f62-2ae0e499c8ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=133074588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.133074588 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_burst_write/latest

Test location	/workspace/coverage/default/13.kmac_edn_timeout_error.3899765926
Short name	T927
Test name
Test status
Simulation time	13253367943 ps
CPU time	57.59 seconds
Started	Jan 10 12:51:14 PM PST 24
Finished	Jan 10 12:53:31 PM PST 24
Peak memory	239636 kb
Host	smart-9b4df1a8-eca4-4b1c-9963-dc92aba8681a
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3899765926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.3899765926 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/13.kmac_entropy_mode_error.3491451755
Short name	T636
Test name
Test status
Simulation time	43220698 ps
CPU time	0.84 seconds
Started	Jan 10 12:50:56 PM PST 24
Finished	Jan 10 12:52:22 PM PST 24
Peak memory	219056 kb
Host	smart-ca974025-188a-434b-b408-b78391ff22f5
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3491451755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.3491451755 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/13.kmac_entropy_refresh.2313322986
Short name	T621
Test name
Test status
Simulation time	12192681057 ps
CPU time	264.02 seconds
Started	Jan 10 12:50:57 PM PST 24
Finished	Jan 10 12:56:44 PM PST 24
Peak memory	249248 kb
Host	smart-08790d41-18ff-402f-8401-d6bc3009ca0d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2313322986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.2313322986 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/13.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/13.kmac_error.3956454816
Short name	T38
Test name
Test status
Simulation time	21075012942 ps
CPU time	399.75 seconds
Started	Jan 10 12:51:19 PM PST 24
Finished	Jan 10 12:59:27 PM PST 24
Peak memory	260192 kb
Host	smart-cf37d19f-e79d-4ffb-a44d-fb09e25efdf2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3956454816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.3956454816 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_error/latest

Test location	/workspace/coverage/default/13.kmac_key_error.3348799009
Short name	T452
Test name
Test status
Simulation time	515458445 ps
CPU time	3.9 seconds
Started	Jan 10 12:51:01 PM PST 24
Finished	Jan 10 12:52:30 PM PST 24
Peak memory	219136 kb
Host	smart-f5c91b5e-fbd1-4e4c-a490-5742ff986d4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3348799009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.3348799009 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_key_error/latest

Test location	/workspace/coverage/default/13.kmac_lc_escalation.3022388382
Short name	T344
Test name
Test status
Simulation time	278701999 ps
CPU time	1.55 seconds
Started	Jan 10 12:51:05 PM PST 24
Finished	Jan 10 12:52:24 PM PST 24
Peak memory	222424 kb
Host	smart-3646d810-cb28-47ac-99eb-169c3fb92965
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3022388382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.3022388382 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/13.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/13.kmac_long_msg_and_output.3414925773
Short name	T820
Test name
Test status
Simulation time	50477708300 ps
CPU time	1328 seconds
Started	Jan 10 12:51:03 PM PST 24
Finished	Jan 10 01:14:29 PM PST 24
Peak memory	323092 kb
Host	smart-2769c7cd-fb92-4c67-996f-315ff644bb20
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414925773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a nd_output.3414925773 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/13.kmac_smoke.2285394339
Short name	T1097
Test name
Test status
Simulation time	1241380892 ps
CPU time	45.87 seconds
Started	Jan 10 12:51:12 PM PST 24
Finished	Jan 10 12:53:29 PM PST 24
Peak memory	227468 kb
Host	smart-54290cc0-a80c-4842-87e4-7e38fd603d48
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2285394339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.2285394339 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_smoke/latest

Test location	/workspace/coverage/default/13.kmac_stress_all.1188163711
Short name	T747
Test name
Test status
Simulation time	32557837269 ps
CPU time	1034.74 seconds
Started	Jan 10 12:51:01 PM PST 24
Finished	Jan 10 01:09:33 PM PST 24
Peak memory	352380 kb
Host	smart-5034f993-e0e0-45f5-b745-ee3b49d595df
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1188163711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.1188163711 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_stress_all/latest

Test location	/workspace/coverage/default/13.kmac_stress_all_with_rand_reset.21260618
Short name	T42
Test name
Test status
Simulation time	35822304817 ps
CPU time	595.64 seconds
Started	Jan 10 12:50:58 PM PST 24
Finished	Jan 10 01:02:06 PM PST 24
Peak memory	274804 kb
Host	smart-c613d90f-1cd8-40ad-b6dc-1ae4327f5f3e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=21260618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all_with_rand_reset.21260618 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_kmac.241203731
Short name	T651
Test name
Test status
Simulation time	133412374 ps
CPU time	5.77 seconds
Started	Jan 10 12:50:55 PM PST 24
Finished	Jan 10 12:52:18 PM PST 24
Peak memory	219296 kb
Host	smart-19819393-e625-4730-baa8-5d42f3c74bf5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241203731 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 13.kmac_test_vectors_kmac.241203731 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_kmac_xof.839886192
Short name	T899
Test name
Test status
Simulation time	848217638 ps
CPU time	5.68 seconds
Started	Jan 10 12:50:55 PM PST 24
Finished	Jan 10 12:52:29 PM PST 24
Peak memory	219244 kb
Host	smart-b8d4561d-9b11-4134-8f8f-7461a16e7ccb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839886192 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 13.kmac_test_vectors_kmac_xof.839886192 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_224.1141069766
Short name	T609
Test name
Test status
Simulation time	41904577127 ps
CPU time	1922.45 seconds
Started	Jan 10 12:50:59 PM PST 24
Finished	Jan 10 01:24:27 PM PST 24
Peak memory	400500 kb
Host	smart-4e579c97-e9b2-44b1-959c-f300499763ed
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1141069766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.1141069766 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_256.2496815777
Short name	T275
Test name
Test status
Simulation time	116131523638 ps
CPU time	1738.45 seconds
Started	Jan 10 12:51:25 PM PST 24
Finished	Jan 10 01:21:43 PM PST 24
Peak memory	369516 kb
Host	smart-308f0604-e25f-4dca-906c-7d39a7e30ce1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2496815777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.2496815777 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_384.2750507612
Short name	T287
Test name
Test status
Simulation time	199236790163 ps
CPU time	1732.52 seconds
Started	Jan 10 12:50:58 PM PST 24
Finished	Jan 10 01:21:07 PM PST 24
Peak memory	344780 kb
Host	smart-ca1a569e-7ee7-48d0-881e-7744efb1e512
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2750507612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.2750507612 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_512.572425099
Short name	T427
Test name
Test status
Simulation time	11511578912 ps
CPU time	1091.42 seconds
Started	Jan 10 12:51:27 PM PST 24
Finished	Jan 10 01:10:57 PM PST 24
Peak memory	302148 kb
Host	smart-e901ce39-c43b-4506-b48e-88c4ff845f81
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=572425099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.572425099 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_shake_128.3918467619
Short name	T357
Test name
Test status
Simulation time	382977790946 ps
CPU time	4969.45 seconds
Started	Jan 10 12:50:59 PM PST 24
Finished	Jan 10 02:15:14 PM PST 24
Peak memory	665960 kb
Host	smart-bd32f800-06db-4b14-9614-3bf4a6632ae2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3918467619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.3918467619 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_shake_256.3697003555
Short name	T1082
Test name
Test status
Simulation time	869333549146 ps
CPU time	4177.19 seconds
Started	Jan 10 12:51:12 PM PST 24
Finished	Jan 10 02:02:08 PM PST 24
Peak memory	568208 kb
Host	smart-6588457e-020d-4e68-bdd4-80d5a3c2c025
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3697003555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.3697003555 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/14.kmac_app.1930417846
Short name	T707
Test name
Test status
Simulation time	9821698240 ps
CPU time	136.91 seconds
Started	Jan 10 12:51:07 PM PST 24
Finished	Jan 10 12:54:39 PM PST 24
Peak memory	239020 kb
Host	smart-add8777b-3d1e-46ab-9aaf-9bc70fa575e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1930417846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.1930417846 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_app/latest

Test location	/workspace/coverage/default/14.kmac_burst_write.345749559
Short name	T690
Test name
Test status
Simulation time	11664192927 ps
CPU time	267.67 seconds
Started	Jan 10 12:50:59 PM PST 24
Finished	Jan 10 12:56:40 PM PST 24
Peak memory	232104 kb
Host	smart-8f15782b-ef00-4b47-aa87-307145afea0d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=345749559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.345749559 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_burst_write/latest

Test location	/workspace/coverage/default/14.kmac_edn_timeout_error.1970549903
Short name	T1060
Test name
Test status
Simulation time	2463415757 ps
CPU time	27.57 seconds
Started	Jan 10 12:51:06 PM PST 24
Finished	Jan 10 12:53:13 PM PST 24
Peak memory	228780 kb
Host	smart-f4ea5427-d123-48fd-bf19-565d8ae1edd1
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1970549903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.1970549903 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/14.kmac_entropy_mode_error.598459712
Short name	T398
Test name
Test status
Simulation time	19443121 ps
CPU time	0.9 seconds
Started	Jan 10 12:51:03 PM PST 24
Finished	Jan 10 12:52:17 PM PST 24
Peak memory	219144 kb
Host	smart-0bec1cdd-7b52-4cd7-8197-0d5c0b901316
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=598459712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.598459712 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/14.kmac_entropy_refresh.3521274449
Short name	T1095
Test name
Test status
Simulation time	12820012413 ps
CPU time	250.75 seconds
Started	Jan 10 12:50:59 PM PST 24
Finished	Jan 10 12:56:25 PM PST 24
Peak memory	247032 kb
Host	smart-b82f7de8-b17f-4460-918a-24ffaee32ea7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3521274449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.3521274449 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/14.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/14.kmac_error.1873824152
Short name	T560
Test name
Test status
Simulation time	26149501146 ps
CPU time	166.67 seconds
Started	Jan 10 12:51:02 PM PST 24
Finished	Jan 10 12:55:07 PM PST 24
Peak memory	252952 kb
Host	smart-40ed15f0-b8ef-4696-a498-19330f1980b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1873824152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.1873824152 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_error/latest

Test location	/workspace/coverage/default/14.kmac_key_error.2998665540
Short name	T853
Test name
Test status
Simulation time	470723361 ps
CPU time	3.15 seconds
Started	Jan 10 12:51:01 PM PST 24
Finished	Jan 10 12:52:42 PM PST 24
Peak memory	219168 kb
Host	smart-94572ddc-de19-4578-98a8-7100fd3287ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2998665540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.2998665540 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_key_error/latest

Test location	/workspace/coverage/default/14.kmac_lc_escalation.1596516011
Short name	T460
Test name
Test status
Simulation time	3374023686 ps
CPU time	43.41 seconds
Started	Jan 10 12:50:57 PM PST 24
Finished	Jan 10 12:52:58 PM PST 24
Peak memory	240196 kb
Host	smart-2225ed5a-6fd7-44f0-9b55-22a31f80e17b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1596516011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.1596516011 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/14.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/14.kmac_long_msg_and_output.3478099957
Short name	T197
Test name
Test status
Simulation time	49425024388 ps
CPU time	1810.65 seconds
Started	Jan 10 12:51:02 PM PST 24
Finished	Jan 10 01:22:32 PM PST 24
Peak memory	365376 kb
Host	smart-8c9a7a7c-fd58-4582-bf6a-63c953f07515
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478099957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a nd_output.3478099957 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/14.kmac_sideload.315607941
Short name	T923
Test name
Test status
Simulation time	4859208536 ps
CPU time	31.12 seconds
Started	Jan 10 12:50:53 PM PST 24
Finished	Jan 10 12:52:48 PM PST 24
Peak memory	227504 kb
Host	smart-b426bfe3-6baa-495c-bf0f-9a25a79450cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=315607941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.315607941 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_sideload/latest

Test location	/workspace/coverage/default/14.kmac_smoke.3234859460
Short name	T279
Test name
Test status
Simulation time	4249330875 ps
CPU time	33.74 seconds
Started	Jan 10 12:51:03 PM PST 24
Finished	Jan 10 12:52:55 PM PST 24
Peak memory	227544 kb
Host	smart-443788b8-dd14-4f83-8f0e-818533116909
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3234859460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.3234859460 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_smoke/latest

Test location	/workspace/coverage/default/14.kmac_stress_all.4116121410
Short name	T588
Test name
Test status
Simulation time	37325060778 ps
CPU time	1239.37 seconds
Started	Jan 10 12:50:56 PM PST 24
Finished	Jan 10 01:13:06 PM PST 24
Peak memory	355780 kb
Host	smart-b579955e-bdeb-4ff2-86ad-73a3434ab5af
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4116121410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.4116121410 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_stress_all/latest

Test location	/workspace/coverage/default/14.kmac_stress_all_with_rand_reset.3015021282
Short name	T142
Test name
Test status
Simulation time	15372697663 ps
CPU time	277.41 seconds
Started	Jan 10 12:51:01 PM PST 24
Finished	Jan 10 12:57:16 PM PST 24
Peak memory	259876 kb
Host	smart-ca413e23-ff7c-47b7-a137-f4cf6f7be820
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3015021282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all_with_rand_reset.3015021282 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_kmac.3763513862
Short name	T960
Test name
Test status
Simulation time	220398066 ps
CPU time	6.02 seconds
Started	Jan 10 12:51:01 PM PST 24
Finished	Jan 10 12:52:24 PM PST 24
Peak memory	220840 kb
Host	smart-d31eba47-e607-49f2-8195-9dc2a041b92a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763513862 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.kmac_test_vectors_kmac.3763513862 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_kmac_xof.260787164
Short name	T167
Test name
Test status
Simulation time	1248374326 ps
CPU time	5.93 seconds
Started	Jan 10 12:50:58 PM PST 24
Finished	Jan 10 12:52:29 PM PST 24
Peak memory	219392 kb
Host	smart-09d719a5-de8e-4280-b525-d5a8f99c1e8b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260787164 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 14.kmac_test_vectors_kmac_xof.260787164 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_224.249658624
Short name	T1054
Test name
Test status
Simulation time	85729898784 ps
CPU time	1909.38 seconds
Started	Jan 10 12:50:56 PM PST 24
Finished	Jan 10 01:24:11 PM PST 24
Peak memory	404132 kb
Host	smart-6353f9a6-a5ae-4ec3-aa72-2a56097abf5b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=249658624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.249658624 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_256.1943263599
Short name	T194
Test name
Test status
Simulation time	399145728745 ps
CPU time	2473.45 seconds
Started	Jan 10 12:51:36 PM PST 24
Finished	Jan 10 01:34:06 PM PST 24
Peak memory	404592 kb
Host	smart-623a5f00-5e43-4e55-b87b-290c8d90d5e2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1943263599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.1943263599 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_384.2596995004
Short name	T525
Test name
Test status
Simulation time	287434690495 ps
CPU time	1778.24 seconds
Started	Jan 10 12:51:03 PM PST 24
Finished	Jan 10 01:21:54 PM PST 24
Peak memory	334244 kb
Host	smart-c582fd91-f3a2-468b-9c1f-831c96529738
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2596995004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.2596995004 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_512.428017519
Short name	T379
Test name
Test status
Simulation time	89675898446 ps
CPU time	1212.49 seconds
Started	Jan 10 12:51:04 PM PST 24
Finished	Jan 10 01:12:41 PM PST 24
Peak memory	301020 kb
Host	smart-1e150bff-a210-489f-a198-d359b8594724
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=428017519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.428017519 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_shake_128.3310289177
Short name	T622
Test name
Test status
Simulation time	746256261830 ps
CPU time	5829.43 seconds
Started	Jan 10 12:50:54 PM PST 24
Finished	Jan 10 02:29:18 PM PST 24
Peak memory	670020 kb
Host	smart-7650544f-7690-4e41-8ad9-f629fec5a0bc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3310289177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.3310289177 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_shake_256.2602186008
Short name	T218
Test name
Test status
Simulation time	368226498348 ps
CPU time	4825.18 seconds
Started	Jan 10 12:51:03 PM PST 24
Finished	Jan 10 02:12:41 PM PST 24
Peak memory	575160 kb
Host	smart-41d6812a-bb6d-4ea9-86c9-dbebb2920989
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2602186008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.2602186008 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/15.kmac_alert_test.2556698436
Short name	T876
Test name
Test status
Simulation time	23451079 ps
CPU time	0.87 seconds
Started	Jan 10 12:51:10 PM PST 24
Finished	Jan 10 12:52:37 PM PST 24
Peak memory	219040 kb
Host	smart-280ff9ae-00f2-48d1-acf2-2b31faa40f37
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556698436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.2556698436 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_alert_test/latest

Test location	/workspace/coverage/default/15.kmac_app.2706785199
Short name	T898
Test name
Test status
Simulation time	6289523876 ps
CPU time	173.83 seconds
Started	Jan 10 12:50:59 PM PST 24
Finished	Jan 10 12:55:17 PM PST 24
Peak memory	240664 kb
Host	smart-0a748573-6ab8-4a82-b478-e33d8a524ebb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2706785199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.2706785199 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_app/latest

Test location	/workspace/coverage/default/15.kmac_burst_write.2362256413
Short name	T20
Test name
Test status
Simulation time	15239777023 ps
CPU time	1489.37 seconds
Started	Jan 10 12:51:03 PM PST 24
Finished	Jan 10 01:17:11 PM PST 24
Peak memory	242216 kb
Host	smart-72a61c63-2ff1-4acc-a5f2-2253279362d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2362256413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.2362256413 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_burst_write/latest

Test location	/workspace/coverage/default/15.kmac_edn_timeout_error.966580445
Short name	T878
Test name
Test status
Simulation time	81635196 ps
CPU time	1.11 seconds
Started	Jan 10 12:51:14 PM PST 24
Finished	Jan 10 12:52:34 PM PST 24
Peak memory	219164 kb
Host	smart-c17db43a-7592-4f55-b52a-7f9f1099bb3f
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=966580445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.966580445 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/15.kmac_entropy_mode_error.1900363039
Short name	T842
Test name
Test status
Simulation time	55644518 ps
CPU time	1.16 seconds
Started	Jan 10 12:51:21 PM PST 24
Finished	Jan 10 12:52:41 PM PST 24
Peak memory	219156 kb
Host	smart-d011e1c8-7e4e-4809-a1d0-10380dc3c842
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1900363039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.1900363039 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/15.kmac_entropy_refresh.1160460103
Short name	T831
Test name
Test status
Simulation time	12711725879 ps
CPU time	269.1 seconds
Started	Jan 10 12:51:07 PM PST 24
Finished	Jan 10 12:57:01 PM PST 24
Peak memory	247468 kb
Host	smart-a94271b0-b295-4560-997e-08b9fa2481f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1160460103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.1160460103 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/15.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/15.kmac_error.1660643475
Short name	T548
Test name
Test status
Simulation time	4900459741 ps
CPU time	392.13 seconds
Started	Jan 10 12:50:55 PM PST 24
Finished	Jan 10 12:58:44 PM PST 24
Peak memory	269416 kb
Host	smart-61dadbb5-5dd7-4ddb-b79a-70337eadfb16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1660643475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.1660643475 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_error/latest

Test location	/workspace/coverage/default/15.kmac_key_error.3180894191
Short name	T106
Test name
Test status
Simulation time	3111825545 ps
CPU time	4.27 seconds
Started	Jan 10 12:51:03 PM PST 24
Finished	Jan 10 12:52:26 PM PST 24
Peak memory	219216 kb
Host	smart-ca9fb979-205a-4458-92d4-bf18899f56ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3180894191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.3180894191 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_key_error/latest

Test location	/workspace/coverage/default/15.kmac_lc_escalation.1320351086
Short name	T471
Test name
Test status
Simulation time	252650016 ps
CPU time	8.74 seconds
Started	Jan 10 12:51:17 PM PST 24
Finished	Jan 10 12:52:45 PM PST 24
Peak memory	227484 kb
Host	smart-00568a6f-c95a-4228-9d43-b0df065b59fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1320351086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.1320351086 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/15.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/15.kmac_long_msg_and_output.719769232
Short name	T1030
Test name
Test status
Simulation time	38984212325 ps
CPU time	2032.32 seconds
Started	Jan 10 12:51:13 PM PST 24
Finished	Jan 10 01:26:26 PM PST 24
Peak memory	411536 kb
Host	smart-5ce63f1a-72cb-47d4-be89-d626cd120d6e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719769232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_an d_output.719769232 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/15.kmac_smoke.767068110
Short name	T888
Test name
Test status
Simulation time	628061692 ps
CPU time	23.48 seconds
Started	Jan 10 12:50:56 PM PST 24
Finished	Jan 10 12:52:45 PM PST 24
Peak memory	225420 kb
Host	smart-a6c4ffbc-e96c-4dde-9577-c49496690773
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=767068110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.767068110 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_smoke/latest

Test location	/workspace/coverage/default/15.kmac_stress_all.2503822376
Short name	T1106
Test name
Test status
Simulation time	11815629796 ps
CPU time	230.91 seconds
Started	Jan 10 12:51:50 PM PST 24
Finished	Jan 10 12:57:06 PM PST 24
Peak memory	260224 kb
Host	smart-216071ae-f133-4148-866e-1cf9d733cbe8
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2503822376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.2503822376 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_stress_all/latest

Test location	/workspace/coverage/default/15.kmac_stress_all_with_rand_reset.1318472731
Short name	T902
Test name
Test status
Simulation time	115126893007 ps
CPU time	567.4 seconds
Started	Jan 10 12:51:18 PM PST 24
Finished	Jan 10 01:02:12 PM PST 24
Peak memory	276724 kb
Host	smart-9e139c6f-534a-42d1-a35f-642d7c0a5424
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1318472731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all_with_rand_reset.1318472731 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_kmac.3445244961
Short name	T388
Test name
Test status
Simulation time	435053394 ps
CPU time	7.32 seconds
Started	Jan 10 12:51:00 PM PST 24
Finished	Jan 10 12:52:33 PM PST 24
Peak memory	220664 kb
Host	smart-fdfaec4a-474a-4792-b010-8c0ed9dc2197
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445244961 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.kmac_test_vectors_kmac.3445244961 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_kmac_xof.1336971966
Short name	T291
Test name
Test status
Simulation time	228965276 ps
CPU time	5.88 seconds
Started	Jan 10 12:51:04 PM PST 24
Finished	Jan 10 12:52:39 PM PST 24
Peak memory	219440 kb
Host	smart-dbed7491-3e4b-48f5-96cc-27b75b3875b5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336971966 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_kmac_xof.1336971966 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_384.677099499
Short name	T1081
Test name
Test status
Simulation time	60780768530 ps
CPU time	1554.88 seconds
Started	Jan 10 12:51:32 PM PST 24
Finished	Jan 10 01:18:46 PM PST 24
Peak memory	347960 kb
Host	smart-3e4b1d1e-f32a-4ed5-aa09-7c31b4f022d6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=677099499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.677099499 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_512.3839995998
Short name	T1086
Test name
Test status
Simulation time	485953356496 ps
CPU time	1482.11 seconds
Started	Jan 10 12:51:02 PM PST 24
Finished	Jan 10 01:16:57 PM PST 24
Peak memory	300600 kb
Host	smart-e696fb85-223b-4cae-865d-1e343d8cd8a8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3839995998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.3839995998 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_shake_128.1760450231
Short name	T662
Test name
Test status
Simulation time	267968806084 ps
CPU time	5581.98 seconds
Started	Jan 10 12:51:08 PM PST 24
Finished	Jan 10 02:25:55 PM PST 24
Peak memory	665236 kb
Host	smart-bb9150b7-492b-45da-91b2-0676e657766a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1760450231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.1760450231 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_shake_256.665047351
Short name	T204
Test name
Test status
Simulation time	208895481435 ps
CPU time	4131.6 seconds
Started	Jan 10 12:51:07 PM PST 24
Finished	Jan 10 02:01:14 PM PST 24
Peak memory	571180 kb
Host	smart-e39e8035-d5c8-4071-bf85-3f55cdb70a32
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=665047351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.665047351 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/16.kmac_alert_test.1420584987
Short name	T830
Test name
Test status
Simulation time	13310863 ps
CPU time	0.82 seconds
Started	Jan 10 12:51:02 PM PST 24
Finished	Jan 10 12:52:16 PM PST 24
Peak memory	220332 kb
Host	smart-f0c38a16-52c3-46ec-98c0-e928851abbde
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420584987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.1420584987 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_alert_test/latest

Test location	/workspace/coverage/default/16.kmac_app.2769965868
Short name	T18
Test name
Test status
Simulation time	12141435572 ps
CPU time	324.74 seconds
Started	Jan 10 12:51:12 PM PST 24
Finished	Jan 10 12:58:08 PM PST 24
Peak memory	252948 kb
Host	smart-b4052eed-2012-4600-aeaf-e85e802344c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2769965868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.2769965868 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_app/latest

Test location	/workspace/coverage/default/16.kmac_burst_write.3712630498
Short name	T356
Test name
Test status
Simulation time	15887505271 ps
CPU time	814.82 seconds
Started	Jan 10 12:51:12 PM PST 24
Finished	Jan 10 01:06:33 PM PST 24
Peak memory	243932 kb
Host	smart-c45a1439-4fc7-4df5-b65b-4dc2bb5cb489
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3712630498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.3712630498 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_burst_write/latest

Test location	/workspace/coverage/default/16.kmac_edn_timeout_error.179489099
Short name	T680
Test name
Test status
Simulation time	238161721 ps
CPU time	4.17 seconds
Started	Jan 10 12:51:23 PM PST 24
Finished	Jan 10 12:52:42 PM PST 24
Peak memory	221716 kb
Host	smart-1b023489-8924-4887-8c79-b3cf153153b7
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=179489099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.179489099 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/16.kmac_entropy_mode_error.2511726245
Short name	T783
Test name
Test status
Simulation time	25039073 ps
CPU time	1.15 seconds
Started	Jan 10 12:51:04 PM PST 24
Finished	Jan 10 12:52:26 PM PST 24
Peak memory	219328 kb
Host	smart-10bb0ca6-dec0-459f-a8fc-06f9e328bc6c
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2511726245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.2511726245 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/16.kmac_entropy_refresh.3601005248
Short name	T936
Test name
Test status
Simulation time	44181265310 ps
CPU time	377.46 seconds
Started	Jan 10 12:51:01 PM PST 24
Finished	Jan 10 12:58:44 PM PST 24
Peak memory	257932 kb
Host	smart-6160fbf1-b840-44e0-aecf-6685300618ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3601005248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.3601005248 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/16.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/16.kmac_error.3370876566
Short name	T958
Test name
Test status
Simulation time	27359913304 ps
CPU time	238.51 seconds
Started	Jan 10 12:51:45 PM PST 24
Finished	Jan 10 12:56:58 PM PST 24
Peak memory	254084 kb
Host	smart-a5404021-0c69-4f0f-a4d5-831d3441efdc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3370876566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.3370876566 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_error/latest

Test location	/workspace/coverage/default/16.kmac_key_error.1165294981
Short name	T478
Test name
Test status
Simulation time	920212482 ps
CPU time	4.96 seconds
Started	Jan 10 12:51:12 PM PST 24
Finished	Jan 10 12:52:52 PM PST 24
Peak memory	219188 kb
Host	smart-c0472c32-5f63-4de4-ae63-dfd8b9e42029
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1165294981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.1165294981 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_key_error/latest

Test location	/workspace/coverage/default/16.kmac_lc_escalation.3846647477
Short name	T916
Test name
Test status
Simulation time	137113416 ps
CPU time	1.41 seconds
Started	Jan 10 12:51:01 PM PST 24
Finished	Jan 10 12:52:28 PM PST 24
Peak memory	220316 kb
Host	smart-a4e211a6-cb85-462e-8cf1-a58cef2d3361
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3846647477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.3846647477 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/16.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/16.kmac_long_msg_and_output.3753573257
Short name	T369
Test name
Test status
Simulation time	268005335807 ps
CPU time	1960.9 seconds
Started	Jan 10 12:51:29 PM PST 24
Finished	Jan 10 01:25:24 PM PST 24
Peak memory	368136 kb
Host	smart-7cee23eb-798e-4fe5-b296-46996583fcd6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753573257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a nd_output.3753573257 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/16.kmac_sideload.1570946869
Short name	T759
Test name
Test status
Simulation time	5693579071 ps
CPU time	97.97 seconds
Started	Jan 10 12:51:13 PM PST 24
Finished	Jan 10 12:54:18 PM PST 24
Peak memory	242916 kb
Host	smart-7614ab8d-bf5a-4a1d-9f00-5a7fb9b355a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1570946869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.1570946869 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_sideload/latest

Test location	/workspace/coverage/default/16.kmac_smoke.4284753425
Short name	T360
Test name
Test status
Simulation time	602867148 ps
CPU time	24.91 seconds
Started	Jan 10 12:51:07 PM PST 24
Finished	Jan 10 12:53:23 PM PST 24
Peak memory	227180 kb
Host	smart-fcd02014-f7d7-497e-9d2e-350cc8d1743b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4284753425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.4284753425 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_smoke/latest

Test location	/workspace/coverage/default/16.kmac_stress_all.1051427113
Short name	T785
Test name
Test status
Simulation time	22986989626 ps
CPU time	1094.23 seconds
Started	Jan 10 12:51:02 PM PST 24
Finished	Jan 10 01:10:41 PM PST 24
Peak memory	314632 kb
Host	smart-217a4efd-bc30-446d-a413-4451316685ee
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1051427113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.1051427113 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_stress_all/latest

Test location	/workspace/coverage/default/16.kmac_stress_all_with_rand_reset.2957262783
Short name	T1080
Test name
Test status
Simulation time	78659330682 ps
CPU time	1279.54 seconds
Started	Jan 10 12:51:18 PM PST 24
Finished	Jan 10 01:14:07 PM PST 24
Peak memory	276932 kb
Host	smart-09e7cddd-2032-4204-bcf1-02bc1286ac55
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2957262783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all_with_rand_reset.2957262783 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_kmac.521475989
Short name	T536
Test name
Test status
Simulation time	788109339 ps
CPU time	5.77 seconds
Started	Jan 10 12:51:19 PM PST 24
Finished	Jan 10 12:52:49 PM PST 24
Peak memory	220796 kb
Host	smart-0980d5b5-def6-4b58-9e8c-26603c574be1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521475989 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 16.kmac_test_vectors_kmac.521475989 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_kmac_xof.2855784568
Short name	T787
Test name
Test status
Simulation time	1020942443 ps
CPU time	6.15 seconds
Started	Jan 10 12:51:13 PM PST 24
Finished	Jan 10 12:52:41 PM PST 24
Peak memory	220508 kb
Host	smart-32a1ada9-abc2-4116-8290-4a36c28a3692
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855784568 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_kmac_xof.2855784568 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_224.622480544
Short name	T507
Test name
Test status
Simulation time	276558100676 ps
CPU time	2115.27 seconds
Started	Jan 10 12:51:10 PM PST 24
Finished	Jan 10 01:27:47 PM PST 24
Peak memory	399764 kb
Host	smart-626ccd65-927c-492b-a68f-085d6f5291e7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=622480544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.622480544 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_256.1183150827
Short name	T382
Test name
Test status
Simulation time	25993155213 ps
CPU time	1853.78 seconds
Started	Jan 10 12:51:03 PM PST 24
Finished	Jan 10 01:23:15 PM PST 24
Peak memory	391788 kb
Host	smart-5a7494c2-b2e1-47e4-8ecf-f8e4eb63d73b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1183150827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.1183150827 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_384.3751428096
Short name	T203
Test name
Test status
Simulation time	72648188230 ps
CPU time	1783.08 seconds
Started	Jan 10 12:51:09 PM PST 24
Finished	Jan 10 01:22:13 PM PST 24
Peak memory	345968 kb
Host	smart-93f11e51-0c28-4d5c-9d8e-198eec98e5a5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3751428096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.3751428096 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_512.345544403
Short name	T907
Test name
Test status
Simulation time	32611083353 ps
CPU time	1175.86 seconds
Started	Jan 10 12:51:19 PM PST 24
Finished	Jan 10 01:12:16 PM PST 24
Peak memory	299232 kb
Host	smart-caea05e9-2b55-48de-82ad-fa7801eaefa3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=345544403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.345544403 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_shake_128.1609382075
Short name	T762
Test name
Test status
Simulation time	119560615514 ps
CPU time	4955.19 seconds
Started	Jan 10 12:51:00 PM PST 24
Finished	Jan 10 02:15:02 PM PST 24
Peak memory	642692 kb
Host	smart-8beddfaa-5227-46ff-a8be-d3bbb2798608
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1609382075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.1609382075 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_shake_256.201589327
Short name	T564
Test name
Test status
Simulation time	227935917697 ps
CPU time	5347.05 seconds
Started	Jan 10 12:51:18 PM PST 24
Finished	Jan 10 02:21:48 PM PST 24
Peak memory	569068 kb
Host	smart-d5363d3f-760c-47cd-bfc9-5e8bbd8403cd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=201589327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.201589327 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/17.kmac_alert_test.2679354814
Short name	T1096
Test name
Test status
Simulation time	14422060 ps
CPU time	0.84 seconds
Started	Jan 10 12:51:17 PM PST 24
Finished	Jan 10 12:52:37 PM PST 24
Peak memory	219208 kb
Host	smart-57805fc7-cebd-4607-abe2-e7cca3ff0ebf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679354814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.2679354814 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_alert_test/latest

Test location	/workspace/coverage/default/17.kmac_app.338923110
Short name	T272
Test name
Test status
Simulation time	12094253799 ps
CPU time	167.48 seconds
Started	Jan 10 12:51:13 PM PST 24
Finished	Jan 10 12:55:21 PM PST 24
Peak memory	239916 kb
Host	smart-6f2f691e-aa05-4706-89ba-82516cdc2fa0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=338923110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.338923110 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_app/latest

Test location	/workspace/coverage/default/17.kmac_burst_write.1882279641
Short name	T964
Test name
Test status
Simulation time	84955138453 ps
CPU time	939.32 seconds
Started	Jan 10 12:51:19 PM PST 24
Finished	Jan 10 01:08:19 PM PST 24
Peak memory	243944 kb
Host	smart-3bab0dd2-009e-4b86-8bc5-6aab6ae87f8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1882279641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.1882279641 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_burst_write/latest

Test location	/workspace/coverage/default/17.kmac_edn_timeout_error.116436275
Short name	T78
Test name
Test status
Simulation time	32112102 ps
CPU time	1.03 seconds
Started	Jan 10 12:51:28 PM PST 24
Finished	Jan 10 12:52:45 PM PST 24
Peak memory	219168 kb
Host	smart-0e8f9298-27a7-4110-8b60-c26b6ef1a6a2
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=116436275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.116436275 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/17.kmac_entropy_mode_error.3571864841
Short name	T745
Test name
Test status
Simulation time	160863198 ps
CPU time	1.11 seconds
Started	Jan 10 12:51:10 PM PST 24
Finished	Jan 10 12:52:41 PM PST 24
Peak memory	219280 kb
Host	smart-e36b050a-6600-4daa-bd3b-9ba2feed7eeb
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3571864841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.3571864841 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/17.kmac_entropy_refresh.2422156375
Short name	T990
Test name
Test status
Simulation time	30950922980 ps
CPU time	120.7 seconds
Started	Jan 10 12:51:10 PM PST 24
Finished	Jan 10 12:54:48 PM PST 24
Peak memory	237332 kb
Host	smart-11ec36e6-60ef-4b8b-9901-b6832aa07e6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2422156375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.2422156375 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/17.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/17.kmac_error.3282163370
Short name	T36
Test name
Test status
Simulation time	5166942303 ps
CPU time	405.1 seconds
Started	Jan 10 12:51:01 PM PST 24
Finished	Jan 10 12:59:11 PM PST 24
Peak memory	259160 kb
Host	smart-d17ea6e2-41e2-4bb9-82cb-1349d2f353b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3282163370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.3282163370 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_error/latest

Test location	/workspace/coverage/default/17.kmac_key_error.2062333624
Short name	T224
Test name
Test status
Simulation time	460844765 ps
CPU time	2.95 seconds
Started	Jan 10 12:51:09 PM PST 24
Finished	Jan 10 12:52:37 PM PST 24
Peak memory	219300 kb
Host	smart-99c4d983-9f55-43f0-84b4-90d108f6b375
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2062333624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.2062333624 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_key_error/latest

Test location	/workspace/coverage/default/17.kmac_lc_escalation.3857129278
Short name	T625
Test name
Test status
Simulation time	3256173476 ps
CPU time	17.57 seconds
Started	Jan 10 12:51:09 PM PST 24
Finished	Jan 10 12:52:48 PM PST 24
Peak memory	228896 kb
Host	smart-1eb5baa9-6860-4c93-a0ea-d2aca5235e71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3857129278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.3857129278 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/17.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/17.kmac_long_msg_and_output.1802624186
Short name	T505
Test name
Test status
Simulation time	85887316096 ps
CPU time	1160.17 seconds
Started	Jan 10 12:51:02 PM PST 24
Finished	Jan 10 01:11:47 PM PST 24
Peak memory	318744 kb
Host	smart-383885b6-7f85-4dd0-bd00-17e29afb0f51
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802624186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a nd_output.1802624186 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/17.kmac_sideload.3155457556
Short name	T894
Test name
Test status
Simulation time	2427036714 ps
CPU time	15.19 seconds
Started	Jan 10 12:51:02 PM PST 24
Finished	Jan 10 12:52:36 PM PST 24
Peak memory	227164 kb
Host	smart-0e1f5e87-2922-4d29-a398-c05f1fff115f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3155457556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.3155457556 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_sideload/latest

Test location	/workspace/coverage/default/17.kmac_smoke.1560583663
Short name	T799
Test name
Test status
Simulation time	27298318243 ps
CPU time	90.56 seconds
Started	Jan 10 12:51:16 PM PST 24
Finished	Jan 10 12:54:07 PM PST 24
Peak memory	227512 kb
Host	smart-be0bfb62-a474-4a2a-8d32-29839e75d702
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1560583663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.1560583663 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_smoke/latest

Test location	/workspace/coverage/default/17.kmac_stress_all.913061593
Short name	T519
Test name
Test status
Simulation time	18540287591 ps
CPU time	1674.06 seconds
Started	Jan 10 12:51:20 PM PST 24
Finished	Jan 10 01:20:34 PM PST 24
Peak memory	374908 kb
Host	smart-80224145-2d0a-4947-9b69-93f7c09eff11
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=913061593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.913061593 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_stress_all/latest

Test location	/workspace/coverage/default/17.kmac_stress_all_with_rand_reset.157688352
Short name	T44
Test name
Test status
Simulation time	144887439349 ps
CPU time	919 seconds
Started	Jan 10 12:51:15 PM PST 24
Finished	Jan 10 01:08:04 PM PST 24
Peak memory	301484 kb
Host	smart-e457e798-5cb2-4d8b-8b04-e124ba1714ba
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=157688352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all_with_rand_reset.157688352 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_kmac.52789968
Short name	T810
Test name
Test status
Simulation time	122146801 ps
CPU time	5.67 seconds
Started	Jan 10 12:51:07 PM PST 24
Finished	Jan 10 12:53:04 PM PST 24
Peak memory	219112 kb
Host	smart-c8613fee-427c-48c7-b37b-3024bb96a5d2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52789968 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 17.kmac_test_vectors_kmac.52789968 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_kmac_xof.1932560999
Short name	T200
Test name
Test status
Simulation time	156981268 ps
CPU time	5.93 seconds
Started	Jan 10 12:51:01 PM PST 24
Finished	Jan 10 12:52:29 PM PST 24
Peak memory	219296 kb
Host	smart-1e508248-5252-4090-9d41-0ba969e4e9e2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932560999 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_kmac_xof.1932560999 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_224.1749165633
Short name	T626
Test name
Test status
Simulation time	561210556927 ps
CPU time	2487.64 seconds
Started	Jan 10 12:51:12 PM PST 24
Finished	Jan 10 01:34:11 PM PST 24
Peak memory	392844 kb
Host	smart-08bcc025-1b41-4209-86c5-82ad48b7f208
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1749165633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.1749165633 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_256.3635106234
Short name	T247
Test name
Test status
Simulation time	74193576619 ps
CPU time	2066.34 seconds
Started	Jan 10 12:51:14 PM PST 24
Finished	Jan 10 01:26:55 PM PST 24
Peak memory	380984 kb
Host	smart-c3fb319c-ae64-4e7e-a8ef-1bfd89c2af00
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3635106234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.3635106234 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_384.945901919
Short name	T811
Test name
Test status
Simulation time	186869976800 ps
CPU time	1644 seconds
Started	Jan 10 12:51:01 PM PST 24
Finished	Jan 10 01:19:47 PM PST 24
Peak memory	336416 kb
Host	smart-5501c646-e29a-4682-8eb6-b4ec004c1494
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=945901919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.945901919 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_512.1811098977
Short name	T483
Test name
Test status
Simulation time	11077276293 ps
CPU time	1109.49 seconds
Started	Jan 10 12:51:18 PM PST 24
Finished	Jan 10 01:11:17 PM PST 24
Peak memory	301788 kb
Host	smart-61df45e9-7e19-4ddc-afda-2c1e00dc525d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1811098977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.1811098977 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_shake_128.121406765
Short name	T187
Test name
Test status
Simulation time	270201901879 ps
CPU time	6285.6 seconds
Started	Jan 10 12:51:15 PM PST 24
Finished	Jan 10 02:37:36 PM PST 24
Peak memory	669788 kb
Host	smart-5a4ca164-fab6-4caa-8a5c-b066c881d9cf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=121406765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.121406765 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_shake_256.3055318089
Short name	T1025
Test name
Test status
Simulation time	800395315940 ps
CPU time	4981.38 seconds
Started	Jan 10 12:51:02 PM PST 24
Finished	Jan 10 02:15:29 PM PST 24
Peak memory	583112 kb
Host	smart-8806b0b3-64ae-4b6d-a32c-55eab795aec3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3055318089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.3055318089 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/18.kmac_alert_test.452848789
Short name	T102
Test name
Test status
Simulation time	52613834 ps
CPU time	0.83 seconds
Started	Jan 10 12:51:38 PM PST 24
Finished	Jan 10 12:53:02 PM PST 24
Peak memory	220248 kb
Host	smart-2d2a383e-2dae-46ba-803a-6d29e0f61760
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452848789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.452848789 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_alert_test/latest

Test location	/workspace/coverage/default/18.kmac_app.2099801672
Short name	T998
Test name
Test status
Simulation time	9149865726 ps
CPU time	218.93 seconds
Started	Jan 10 12:51:35 PM PST 24
Finished	Jan 10 12:56:31 PM PST 24
Peak memory	244484 kb
Host	smart-4d0624f2-f151-44d6-b9af-b995b71d5f36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2099801672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.2099801672 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_app/latest

Test location	/workspace/coverage/default/18.kmac_burst_write.4113621001
Short name	T652
Test name
Test status
Simulation time	172980894099 ps
CPU time	358.17 seconds
Started	Jan 10 12:51:05 PM PST 24
Finished	Jan 10 12:58:17 PM PST 24
Peak memory	241968 kb
Host	smart-91441cd5-c04f-450b-ac7d-1e9da5de0007
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4113621001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.4113621001 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_burst_write/latest

Test location	/workspace/coverage/default/18.kmac_edn_timeout_error.4164049280
Short name	T561
Test name
Test status
Simulation time	258343846 ps
CPU time	22.03 seconds
Started	Jan 10 12:51:09 PM PST 24
Finished	Jan 10 12:52:53 PM PST 24
Peak memory	227308 kb
Host	smart-e2a61bcf-cdc1-435b-9095-c63bc48b061d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4164049280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.4164049280 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/18.kmac_entropy_mode_error.172924157
Short name	T84
Test name
Test status
Simulation time	116754900 ps
CPU time	1.04 seconds
Started	Jan 10 12:51:06 PM PST 24
Finished	Jan 10 12:52:25 PM PST 24
Peak memory	219260 kb
Host	smart-67a084e8-868c-461e-8623-b9976456b965
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=172924157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.172924157 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/18.kmac_error.425904470
Short name	T364
Test name
Test status
Simulation time	27316940227 ps
CPU time	132.45 seconds
Started	Jan 10 12:51:27 PM PST 24
Finished	Jan 10 12:55:03 PM PST 24
Peak memory	252108 kb
Host	smart-f0134335-3add-4dd4-a45f-6b5fcce551c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=425904470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.425904470 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_error/latest

Test location	/workspace/coverage/default/18.kmac_key_error.113911404
Short name	T1029
Test name
Test status
Simulation time	514389879 ps
CPU time	3.78 seconds
Started	Jan 10 12:51:08 PM PST 24
Finished	Jan 10 12:52:26 PM PST 24
Peak memory	219260 kb
Host	smart-7b12206b-5ed1-4d89-9273-1ba2c3bfc9e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113911404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.113911404 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_key_error/latest

Test location	/workspace/coverage/default/18.kmac_lc_escalation.1424366350
Short name	T1009
Test name
Test status
Simulation time	4353898785 ps
CPU time	15.01 seconds
Started	Jan 10 12:51:04 PM PST 24
Finished	Jan 10 12:52:40 PM PST 24
Peak memory	227660 kb
Host	smart-e6b9e634-705d-4ccf-b052-bd23f5c99b6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1424366350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.1424366350 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/18.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/18.kmac_sideload.4229671259
Short name	T686
Test name
Test status
Simulation time	9910747022 ps
CPU time	392.97 seconds
Started	Jan 10 12:51:13 PM PST 24
Finished	Jan 10 12:59:14 PM PST 24
Peak memory	255056 kb
Host	smart-ceec46fe-6301-4ea0-98ce-c170359eff43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4229671259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.4229671259 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_sideload/latest

Test location	/workspace/coverage/default/18.kmac_smoke.1011601038
Short name	T633
Test name
Test status
Simulation time	1588470649 ps
CPU time	22.21 seconds
Started	Jan 10 12:51:07 PM PST 24
Finished	Jan 10 12:52:51 PM PST 24
Peak memory	225224 kb
Host	smart-70baa601-ae85-4f82-92bb-d34174aa7696
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1011601038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.1011601038 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_smoke/latest

Test location	/workspace/coverage/default/18.kmac_stress_all.2838896733
Short name	T863
Test name
Test status
Simulation time	244251002591 ps
CPU time	1945.36 seconds
Started	Jan 10 12:51:36 PM PST 24
Finished	Jan 10 01:25:22 PM PST 24
Peak memory	425328 kb
Host	smart-e1a33c96-eba2-4d43-b0e5-df5b3f20fd15
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2838896733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.2838896733 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_stress_all/latest

Test location	/workspace/coverage/default/18.kmac_stress_all_with_rand_reset.3516059904
Short name	T768
Test name
Test status
Simulation time	29178311275 ps
CPU time	1273.97 seconds
Started	Jan 10 12:51:09 PM PST 24
Finished	Jan 10 01:13:40 PM PST 24
Peak memory	307084 kb
Host	smart-fe414bb9-4096-4b8d-a01f-97958047135f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3516059904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all_with_rand_reset.3516059904 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_kmac.3131674188
Short name	T696
Test name
Test status
Simulation time	1131532413 ps
CPU time	5.86 seconds
Started	Jan 10 12:51:14 PM PST 24
Finished	Jan 10 12:52:39 PM PST 24
Peak memory	220932 kb
Host	smart-06671aba-99a5-4671-9c5c-9bc5f0ae39ae
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131674188 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 18.kmac_test_vectors_kmac.3131674188 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_kmac_xof.3355514448
Short name	T422
Test name
Test status
Simulation time	200295774 ps
CPU time	6.29 seconds
Started	Jan 10 12:51:13 PM PST 24
Finished	Jan 10 12:52:40 PM PST 24
Peak memory	220728 kb
Host	smart-55c6ba96-e71d-4b9b-9fbf-68beeb1e25a9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355514448 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_kmac_xof.3355514448 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_224.3695786482
Short name	T727
Test name
Test status
Simulation time	195764383070 ps
CPU time	1910.8 seconds
Started	Jan 10 12:51:14 PM PST 24
Finished	Jan 10 01:24:24 PM PST 24
Peak memory	399856 kb
Host	smart-0e90afd7-33e6-4ff1-a576-752ea7011d19
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3695786482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.3695786482 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_256.4133495771
Short name	T956
Test name
Test status
Simulation time	19988869381 ps
CPU time	1700.33 seconds
Started	Jan 10 12:51:22 PM PST 24
Finished	Jan 10 01:21:03 PM PST 24
Peak memory	380208 kb
Host	smart-07d27422-208a-4fed-a45b-78ef9b4952b3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4133495771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.4133495771 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_384.3817971692
Short name	T485
Test name
Test status
Simulation time	29348204706 ps
CPU time	1460.46 seconds
Started	Jan 10 12:51:05 PM PST 24
Finished	Jan 10 01:16:50 PM PST 24
Peak memory	340668 kb
Host	smart-ca662edc-a698-4b5d-9a0a-707e89585139
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3817971692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.3817971692 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_512.1684101320
Short name	T833
Test name
Test status
Simulation time	34300869591 ps
CPU time	1279.04 seconds
Started	Jan 10 12:51:14 PM PST 24
Finished	Jan 10 01:13:52 PM PST 24
Peak memory	303604 kb
Host	smart-68eaa7da-673e-47ab-baa9-d1c983ddfae5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1684101320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.1684101320 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_shake_128.2134064957
Short name	T499
Test name
Test status
Simulation time	159676998679 ps
CPU time	5223.2 seconds
Started	Jan 10 12:51:51 PM PST 24
Finished	Jan 10 02:20:08 PM PST 24
Peak memory	654520 kb
Host	smart-6500f22d-c139-4642-9b7f-b34d459c4ec1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2134064957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.2134064957 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_shake_256.2907806053
Short name	T914
Test name
Test status
Simulation time	233141154765 ps
CPU time	4333.81 seconds
Started	Jan 10 12:51:09 PM PST 24
Finished	Jan 10 02:04:59 PM PST 24
Peak memory	576840 kb
Host	smart-7f8b2b04-ff66-4cd5-bb2c-0356f765a395
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2907806053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.2907806053 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/19.kmac_alert_test.4257201533
Short name	T821
Test name
Test status
Simulation time	31145737 ps
CPU time	0.83 seconds
Started	Jan 10 12:51:15 PM PST 24
Finished	Jan 10 12:52:35 PM PST 24
Peak memory	219052 kb
Host	smart-d3497656-2cf5-420f-9aa8-a70246bd72e9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257201533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.4257201533 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_alert_test/latest

Test location	/workspace/coverage/default/19.kmac_app.1622357774
Short name	T883
Test name
Test status
Simulation time	729389863 ps
CPU time	40.71 seconds
Started	Jan 10 12:51:35 PM PST 24
Finished	Jan 10 12:53:30 PM PST 24
Peak memory	229024 kb
Host	smart-3de228cb-683b-4b64-a00b-07087784e33d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1622357774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.1622357774 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_app/latest

Test location	/workspace/coverage/default/19.kmac_burst_write.908664685
Short name	T390
Test name
Test status
Simulation time	11518534504 ps
CPU time	502.44 seconds
Started	Jan 10 12:51:38 PM PST 24
Finished	Jan 10 01:01:14 PM PST 24
Peak memory	235424 kb
Host	smart-6fef5ab4-aa77-4506-94f4-3e43e913f147
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=908664685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.908664685 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_burst_write/latest

Test location	/workspace/coverage/default/19.kmac_edn_timeout_error.3253941843
Short name	T580
Test name
Test status
Simulation time	222360432 ps
CPU time	1.05 seconds
Started	Jan 10 12:52:01 PM PST 24
Finished	Jan 10 12:53:26 PM PST 24
Peak memory	219000 kb
Host	smart-ccea49ec-1857-4c8d-b63a-0258dbe2e647
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3253941843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.3253941843 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/19.kmac_entropy_mode_error.3504844159
Short name	T85
Test name
Test status
Simulation time	18412345 ps
CPU time	0.9 seconds
Started	Jan 10 12:51:15 PM PST 24
Finished	Jan 10 12:52:46 PM PST 24
Peak memory	219004 kb
Host	smart-4ab8b61e-5eea-48d9-88d1-6c8702cacbc1
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3504844159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.3504844159 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/19.kmac_entropy_refresh.2163116594
Short name	T511
Test name
Test status
Simulation time	315825335 ps
CPU time	2.88 seconds
Started	Jan 10 12:51:08 PM PST 24
Finished	Jan 10 12:52:30 PM PST 24
Peak memory	225568 kb
Host	smart-54235e06-e5df-435c-9a4f-7214f2c2956c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2163116594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.2163116594 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/19.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/19.kmac_error.2661209487
Short name	T597
Test name
Test status
Simulation time	18718022543 ps
CPU time	105.99 seconds
Started	Jan 10 12:51:15 PM PST 24
Finished	Jan 10 12:54:20 PM PST 24
Peak memory	244988 kb
Host	smart-37cc4456-4d39-44c2-bf0e-73dd3cb4a97e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2661209487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.2661209487 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_error/latest

Test location	/workspace/coverage/default/19.kmac_key_error.861816856
Short name	T823
Test name
Test status
Simulation time	1531214581 ps
CPU time	3.02 seconds
Started	Jan 10 12:51:06 PM PST 24
Finished	Jan 10 12:52:22 PM PST 24
Peak memory	219264 kb
Host	smart-44f24ebd-8705-48ca-9862-186dce2fc966
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=861816856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.861816856 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_key_error/latest

Test location	/workspace/coverage/default/19.kmac_lc_escalation.3094731218
Short name	T991
Test name
Test status
Simulation time	146269518 ps
CPU time	1.42 seconds
Started	Jan 10 12:51:24 PM PST 24
Finished	Jan 10 12:52:57 PM PST 24
Peak memory	220304 kb
Host	smart-2f329304-9818-497a-8071-e5cf683f99e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3094731218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.3094731218 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/19.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/19.kmac_long_msg_and_output.3098770833
Short name	T177
Test name
Test status
Simulation time	63116858687 ps
CPU time	1583.98 seconds
Started	Jan 10 12:51:07 PM PST 24
Finished	Jan 10 01:19:39 PM PST 24
Peak memory	346128 kb
Host	smart-3b289c2f-acdf-4d9c-b411-4290db143a65
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098770833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a nd_output.3098770833 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/19.kmac_sideload.742451274
Short name	T905
Test name
Test status
Simulation time	5817758390 ps
CPU time	117.64 seconds
Started	Jan 10 12:51:32 PM PST 24
Finished	Jan 10 12:54:44 PM PST 24
Peak memory	237100 kb
Host	smart-5a8d43f6-a6fa-4ed2-8d56-072e7f90059c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=742451274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.742451274 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_sideload/latest

Test location	/workspace/coverage/default/19.kmac_smoke.1284230016
Short name	T161
Test name
Test status
Simulation time	1684258363 ps
CPU time	64.43 seconds
Started	Jan 10 12:51:42 PM PST 24
Finished	Jan 10 12:54:09 PM PST 24
Peak memory	227396 kb
Host	smart-8a4ea3cc-05eb-474c-8991-0753eaf7a526
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1284230016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.1284230016 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_smoke/latest

Test location	/workspace/coverage/default/19.kmac_stress_all.4044670152
Short name	T238
Test name
Test status
Simulation time	1883431754 ps
CPU time	36.56 seconds
Started	Jan 10 12:51:18 PM PST 24
Finished	Jan 10 12:53:21 PM PST 24
Peak memory	228908 kb
Host	smart-9ba319ba-b0b3-4adb-b0a9-4e1af6407c7f
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4044670152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.4044670152 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_stress_all/latest

Test location	/workspace/coverage/default/19.kmac_stress_all_with_rand_reset.2134921902
Short name	T817
Test name
Test status
Simulation time	35456327448 ps
CPU time	760.59 seconds
Started	Jan 10 12:51:20 PM PST 24
Finished	Jan 10 01:05:21 PM PST 24
Peak memory	301508 kb
Host	smart-f8305fd0-771d-4f29-aaf1-8bb7bbdefdd6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2134921902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all_with_rand_reset.2134921902 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_kmac.2349449827
Short name	T976
Test name
Test status
Simulation time	495438454 ps
CPU time	5.83 seconds
Started	Jan 10 12:51:32 PM PST 24
Finished	Jan 10 12:52:56 PM PST 24
Peak memory	220768 kb
Host	smart-a3d80003-0302-4a1c-b62e-112dd2231f76
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349449827 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.kmac_test_vectors_kmac.2349449827 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_kmac_xof.2320913792
Short name	T513
Test name
Test status
Simulation time	712615303 ps
CPU time	5.89 seconds
Started	Jan 10 12:51:10 PM PST 24
Finished	Jan 10 12:52:42 PM PST 24
Peak memory	220796 kb
Host	smart-a7caf834-9b1c-4eee-81d8-812bddad101d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320913792 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_kmac_xof.2320913792 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_224.3692766086
Short name	T780
Test name
Test status
Simulation time	56214827018 ps
CPU time	1798.78 seconds
Started	Jan 10 12:51:20 PM PST 24
Finished	Jan 10 01:22:38 PM PST 24
Peak memory	390788 kb
Host	smart-33bfca42-d64d-4089-a664-be22f06c4d90
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3692766086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.3692766086 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_256.1363943778
Short name	T227
Test name
Test status
Simulation time	378573087600 ps
CPU time	2145.68 seconds
Started	Jan 10 12:51:12 PM PST 24
Finished	Jan 10 01:28:33 PM PST 24
Peak memory	378080 kb
Host	smart-80ffd7c3-c6a5-4c4e-b412-93bf1f14500a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1363943778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.1363943778 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_384.3529609529
Short name	T943
Test name
Test status
Simulation time	319962708281 ps
CPU time	1760.07 seconds
Started	Jan 10 12:51:17 PM PST 24
Finished	Jan 10 01:22:18 PM PST 24
Peak memory	342204 kb
Host	smart-c0e401b3-6e76-4be2-a0e4-d473d761c2a2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3529609529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.3529609529 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_512.1586345088
Short name	T411
Test name
Test status
Simulation time	45514926635 ps
CPU time	1146.4 seconds
Started	Jan 10 12:51:20 PM PST 24
Finished	Jan 10 01:11:46 PM PST 24
Peak memory	302496 kb
Host	smart-9c629ad8-6538-4080-94ea-c816d84a48c2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1586345088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.1586345088 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_shake_128.2406092755
Short name	T948
Test name
Test status
Simulation time	60958466522 ps
CPU time	4873.31 seconds
Started	Jan 10 12:51:43 PM PST 24
Finished	Jan 10 02:14:21 PM PST 24
Peak memory	662860 kb
Host	smart-c35f6b09-a78f-4dd3-93de-e8ced0c0020c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2406092755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.2406092755 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_shake_256.1304036165
Short name	T761
Test name
Test status
Simulation time	55961102130 ps
CPU time	4510.54 seconds
Started	Jan 10 12:51:16 PM PST 24
Finished	Jan 10 02:07:43 PM PST 24
Peak memory	578948 kb
Host	smart-f9db7b46-0cc7-4511-8f55-1ec730afe83c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1304036165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.1304036165 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/2.kmac_alert_test.341590202
Short name	T772
Test name
Test status
Simulation time	11246325 ps
CPU time	0.8 seconds
Started	Jan 10 12:51:38 PM PST 24
Finished	Jan 10 12:52:52 PM PST 24
Peak memory	219144 kb
Host	smart-53ef5beb-e730-4f8c-bc13-d06faf7a3e19
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341590202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.341590202 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_alert_test/latest

Test location	/workspace/coverage/default/2.kmac_app.4081866380
Short name	T840
Test name
Test status
Simulation time	10994673827 ps
CPU time	289.14 seconds
Started	Jan 10 12:50:14 PM PST 24
Finished	Jan 10 12:56:39 PM PST 24
Peak memory	250532 kb
Host	smart-3f70b0d4-8ebc-46b3-bab5-fbe96b0347b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4081866380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.4081866380 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_app/latest

Test location	/workspace/coverage/default/2.kmac_app_with_partial_data.3101493469
Short name	T1007
Test name
Test status
Simulation time	19373769435 ps
CPU time	408.91 seconds
Started	Jan 10 12:51:36 PM PST 24
Finished	Jan 10 12:59:41 PM PST 24
Peak memory	254524 kb
Host	smart-7ff5179e-78b3-467e-8a56-deba17bb8840
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3101493469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.3101493469 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/2.kmac_burst_write.4040245526
Short name	T862
Test name
Test status
Simulation time	30006789167 ps
CPU time	1049.34 seconds
Started	Jan 10 12:50:12 PM PST 24
Finished	Jan 10 01:09:20 PM PST 24
Peak memory	239984 kb
Host	smart-5da8578a-15d4-45f4-85ae-7505d9db15dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4040245526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.4040245526 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_burst_write/latest

Test location	/workspace/coverage/default/2.kmac_edn_timeout_error.3242017770
Short name	T366
Test name
Test status
Simulation time	61909682 ps
CPU time	1.01 seconds
Started	Jan 10 12:50:15 PM PST 24
Finished	Jan 10 12:51:49 PM PST 24
Peak memory	219104 kb
Host	smart-1731aee6-debf-4396-a270-5bf9f4f846e0
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3242017770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.3242017770 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/2.kmac_entropy_mode_error.1363358147
Short name	T818
Test name
Test status
Simulation time	271729283 ps
CPU time	8.01 seconds
Started	Jan 10 12:50:23 PM PST 24
Finished	Jan 10 12:51:50 PM PST 24
Peak memory	223016 kb
Host	smart-f55d442b-0861-4bc0-ad35-00a65081e739
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1363358147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.1363358147 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/2.kmac_entropy_ready_error.3598638238
Short name	T27
Test name
Test status
Simulation time	1868982262 ps
CPU time	19.04 seconds
Started	Jan 10 12:50:14 PM PST 24
Finished	Jan 10 12:52:09 PM PST 24
Peak memory	219312 kb
Host	smart-3c5101d8-51b9-472c-b250-2bc15dae2386
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3598638238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.3598638238 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/2.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/2.kmac_entropy_refresh.154650068
Short name	T756
Test name
Test status
Simulation time	35101070434 ps
CPU time	300.1 seconds
Started	Jan 10 12:50:11 PM PST 24
Finished	Jan 10 12:56:33 PM PST 24
Peak memory	248624 kb
Host	smart-1febf0df-c07a-45a3-84ec-a3106c44a851
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=154650068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.154650068 +enable_masking=1 +sw_ key_masked=0
Directory	/workspace/2.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/2.kmac_error.1885987694
Short name	T1034
Test name
Test status
Simulation time	15091517556 ps
CPU time	489.65 seconds
Started	Jan 10 12:50:12 PM PST 24
Finished	Jan 10 01:00:05 PM PST 24
Peak memory	263656 kb
Host	smart-835e1c84-f1de-42f7-add9-5181da0ac7d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1885987694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.1885987694 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_error/latest

Test location	/workspace/coverage/default/2.kmac_key_error.4070788234
Short name	T465
Test name
Test status
Simulation time	745365335 ps
CPU time	4.76 seconds
Started	Jan 10 12:50:27 PM PST 24
Finished	Jan 10 12:52:00 PM PST 24
Peak memory	219252 kb
Host	smart-038527f0-410b-4f4c-aec7-4369999b5c38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4070788234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.4070788234 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_key_error/latest

Test location	/workspace/coverage/default/2.kmac_lc_escalation.2979214338
Short name	T262
Test name
Test status
Simulation time	26731568 ps
CPU time	1.35 seconds
Started	Jan 10 12:50:15 PM PST 24
Finished	Jan 10 12:51:37 PM PST 24
Peak memory	220784 kb
Host	smart-3fefb713-3501-4962-93c0-ea7cc955d026
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2979214338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.2979214338 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/2.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/2.kmac_long_msg_and_output.4258414505
Short name	T641
Test name
Test status
Simulation time	110489619343 ps
CPU time	2800.39 seconds
Started	Jan 10 12:50:06 PM PST 24
Finished	Jan 10 01:38:20 PM PST 24
Peak memory	465632 kb
Host	smart-ac8b29f1-4d83-4c83-9bb2-141d84627cd9
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258414505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an d_output.4258414505 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/2.kmac_mubi.973643306
Short name	T298
Test name
Test status
Simulation time	5177080735 ps
CPU time	368.18 seconds
Started	Jan 10 12:50:12 PM PST 24
Finished	Jan 10 12:57:59 PM PST 24
Peak memory	256116 kb
Host	smart-d994f20d-c00a-4ad6-9ed6-aa01d5bf7902
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=973643306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.973643306 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_mubi/latest

Test location	/workspace/coverage/default/2.kmac_sideload.1076947677
Short name	T433
Test name
Test status
Simulation time	15812525905 ps
CPU time	387.59 seconds
Started	Jan 10 12:50:09 PM PST 24
Finished	Jan 10 12:58:15 PM PST 24
Peak memory	252476 kb
Host	smart-6bf1d690-e193-443d-85f9-0f25ee3f38fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1076947677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.1076947677 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_sideload/latest

Test location	/workspace/coverage/default/2.kmac_smoke.2214411789
Short name	T1109
Test name
Test status
Simulation time	9707109562 ps
CPU time	43.03 seconds
Started	Jan 10 12:50:06 PM PST 24
Finished	Jan 10 12:52:12 PM PST 24
Peak memory	227480 kb
Host	smart-ba71d7bc-b4bb-41e3-b5b8-ef6417adebbb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2214411789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.2214411789 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_smoke/latest

Test location	/workspace/coverage/default/2.kmac_stress_all.579534990
Short name	T558
Test name
Test status
Simulation time	49413901643 ps
CPU time	205.14 seconds
Started	Jan 10 12:50:20 PM PST 24
Finished	Jan 10 12:55:03 PM PST 24
Peak memory	252040 kb
Host	smart-ba5893d9-7ce0-4bfa-ae7b-8b352de95d46
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=579534990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.579534990 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_stress_all/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_kmac.3372681646
Short name	T774
Test name
Test status
Simulation time	505788785 ps
CPU time	5.39 seconds
Started	Jan 10 12:50:19 PM PST 24
Finished	Jan 10 12:51:44 PM PST 24
Peak memory	220684 kb
Host	smart-fc2caba1-342f-481e-b703-2ee4e4bd35c3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372681646 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.kmac_test_vectors_kmac.3372681646 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_kmac_xof.2778600645
Short name	T183
Test name
Test status
Simulation time	259573141 ps
CPU time	6.39 seconds
Started	Jan 10 12:50:12 PM PST 24
Finished	Jan 10 12:51:41 PM PST 24
Peak memory	219268 kb
Host	smart-8bc23e5c-5d70-4fab-b918-b2cc68a50ea8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778600645 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.2778600645 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_224.3229581879
Short name	T1088
Test name
Test status
Simulation time	82389107497 ps
CPU time	2196.53 seconds
Started	Jan 10 12:50:04 PM PST 24
Finished	Jan 10 01:28:29 PM PST 24
Peak memory	403436 kb
Host	smart-654f41d3-98e8-486c-8718-0eaff6bb1bc6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3229581879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.3229581879 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_256.3433557630
Short name	T644
Test name
Test status
Simulation time	370875226963 ps
CPU time	2226.34 seconds
Started	Jan 10 12:50:15 PM PST 24
Finished	Jan 10 01:28:59 PM PST 24
Peak memory	372596 kb
Host	smart-37851d02-a1ac-4195-944c-57e2519e59f4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3433557630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.3433557630 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_384.3369494319
Short name	T815
Test name
Test status
Simulation time	54565511867 ps
CPU time	1456.52 seconds
Started	Jan 10 12:50:48 PM PST 24
Finished	Jan 10 01:16:21 PM PST 24
Peak memory	340888 kb
Host	smart-6bc4ffbd-f8a4-43c7-b3d3-11253c0fc79d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3369494319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.3369494319 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_512.2860982347
Short name	T477
Test name
Test status
Simulation time	160563226485 ps
CPU time	1178.51 seconds
Started	Jan 10 12:50:31 PM PST 24
Finished	Jan 10 01:11:29 PM PST 24
Peak memory	296080 kb
Host	smart-0517c420-b65d-41c6-8a5c-c9801a9c475a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2860982347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.2860982347 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_shake_128.3565166912
Short name	T575
Test name
Test status
Simulation time	221626277763 ps
CPU time	4904.17 seconds
Started	Jan 10 12:50:42 PM PST 24
Finished	Jan 10 02:13:48 PM PST 24
Peak memory	646096 kb
Host	smart-6fdf2b30-cd5a-45e6-830d-cf250eed6562
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3565166912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.3565166912 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_shake_256.1101799411
Short name	T486
Test name
Test status
Simulation time	211013186544 ps
CPU time	4255.58 seconds
Started	Jan 10 12:50:10 PM PST 24
Finished	Jan 10 02:02:28 PM PST 24
Peak memory	576656 kb
Host	smart-e4accd5b-3c73-4967-9c11-76a28b41d7c7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1101799411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.1101799411 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/20.kmac_alert_test.1069189681
Short name	T954
Test name
Test status
Simulation time	31522600 ps
CPU time	0.8 seconds
Started	Jan 10 12:51:18 PM PST 24
Finished	Jan 10 12:52:41 PM PST 24
Peak memory	218964 kb
Host	smart-bb332a3a-b84a-4bf6-889c-7831ed40c8df
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069189681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.1069189681 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_alert_test/latest

Test location	/workspace/coverage/default/20.kmac_app.2407747
Short name	T1005
Test name
Test status
Simulation time	5895622775 ps
CPU time	86.63 seconds
Started	Jan 10 12:51:15 PM PST 24
Finished	Jan 10 12:54:09 PM PST 24
Peak memory	235136 kb
Host	smart-7d9260bb-757e-4cec-826e-88e2fb5b5c3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2407747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.2407747 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_app/latest

Test location	/workspace/coverage/default/20.kmac_burst_write.2808146704
Short name	T371
Test name
Test status
Simulation time	15015138345 ps
CPU time	474.71 seconds
Started	Jan 10 12:51:06 PM PST 24
Finished	Jan 10 01:00:31 PM PST 24
Peak memory	243812 kb
Host	smart-2ca2a472-fb98-4b74-88cb-868a80ce2c41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2808146704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.2808146704 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_burst_write/latest

Test location	/workspace/coverage/default/20.kmac_entropy_refresh.1488643785
Short name	T514
Test name
Test status
Simulation time	144608413696 ps
CPU time	315.67 seconds
Started	Jan 10 12:51:42 PM PST 24
Finished	Jan 10 12:58:19 PM PST 24
Peak memory	250924 kb
Host	smart-0d0fa82e-7118-4b1d-acae-4242dcec5996
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1488643785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.1488643785 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/20.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/20.kmac_error.3453690390
Short name	T1024
Test name
Test status
Simulation time	7051373946 ps
CPU time	87.05 seconds
Started	Jan 10 12:51:29 PM PST 24
Finished	Jan 10 12:54:11 PM PST 24
Peak memory	252144 kb
Host	smart-7be312d2-1334-43ff-b075-244fde86e1ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3453690390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.3453690390 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_error/latest

Test location	/workspace/coverage/default/20.kmac_key_error.3881383289
Short name	T563
Test name
Test status
Simulation time	3358471727 ps
CPU time	6.08 seconds
Started	Jan 10 12:51:25 PM PST 24
Finished	Jan 10 12:52:47 PM PST 24
Peak memory	219232 kb
Host	smart-25b3148a-2b56-4c7a-ac81-2c9efd25d55c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3881383289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.3881383289 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_key_error/latest

Test location	/workspace/coverage/default/20.kmac_lc_escalation.435727429
Short name	T370
Test name
Test status
Simulation time	499778332 ps
CPU time	15.19 seconds
Started	Jan 10 12:51:19 PM PST 24
Finished	Jan 10 12:52:56 PM PST 24
Peak memory	241492 kb
Host	smart-fee96c2f-bf76-4c8c-898b-96d05f02378c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=435727429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.435727429 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/20.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/20.kmac_long_msg_and_output.4292454483
Short name	T755
Test name
Test status
Simulation time	50793922357 ps
CPU time	1170.58 seconds
Started	Jan 10 12:51:32 PM PST 24
Finished	Jan 10 01:12:21 PM PST 24
Peak memory	335336 kb
Host	smart-234fc18c-f26f-42c0-8ccf-1653afea44fe
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292454483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a nd_output.4292454483 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/20.kmac_sideload.1963266967
Short name	T1003
Test name
Test status
Simulation time	27959840548 ps
CPU time	228.02 seconds
Started	Jan 10 12:51:32 PM PST 24
Finished	Jan 10 12:56:42 PM PST 24
Peak memory	244368 kb
Host	smart-4d5a6ef7-16e6-4f8c-8a33-04eb1f0cb07d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1963266967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.1963266967 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_sideload/latest

Test location	/workspace/coverage/default/20.kmac_smoke.1531156776
Short name	T874
Test name
Test status
Simulation time	3263112598 ps
CPU time	59.44 seconds
Started	Jan 10 12:51:13 PM PST 24
Finished	Jan 10 12:53:37 PM PST 24
Peak memory	227560 kb
Host	smart-6f038436-64da-4459-beca-623ab2064fc2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1531156776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.1531156776 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_smoke/latest

Test location	/workspace/coverage/default/20.kmac_stress_all_with_rand_reset.3877592195
Short name	T959
Test name
Test status
Simulation time	95846505847 ps
CPU time	1501.08 seconds
Started	Jan 10 12:52:04 PM PST 24
Finished	Jan 10 01:18:21 PM PST 24
Peak memory	322360 kb
Host	smart-cb319470-730f-4bcd-b613-12ee5884d753
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3877592195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all_with_rand_reset.3877592195 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_kmac.1706782130
Short name	T502
Test name
Test status
Simulation time	127471343 ps
CPU time	5.44 seconds
Started	Jan 10 12:51:19 PM PST 24
Finished	Jan 10 12:52:45 PM PST 24
Peak memory	219396 kb
Host	smart-43b5c21f-31bd-4753-a0de-bfd982435b3d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706782130 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 20.kmac_test_vectors_kmac.1706782130 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_kmac_xof.3294339364
Short name	T618
Test name
Test status
Simulation time	514549713 ps
CPU time	6.39 seconds
Started	Jan 10 12:51:28 PM PST 24
Finished	Jan 10 12:52:51 PM PST 24
Peak memory	220576 kb
Host	smart-7a71e6d6-335b-4db5-b8f3-27e408f999de
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294339364 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_kmac_xof.3294339364 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_224.3650264911
Short name	T951
Test name
Test status
Simulation time	42061467806 ps
CPU time	1949.83 seconds
Started	Jan 10 12:51:35 PM PST 24
Finished	Jan 10 01:25:19 PM PST 24
Peak memory	405856 kb
Host	smart-8dc9b955-7ffb-450d-bf24-666e5870ad0b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3650264911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.3650264911 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_256.1936174345
Short name	T794
Test name
Test status
Simulation time	174652145981 ps
CPU time	1758.95 seconds
Started	Jan 10 12:51:35 PM PST 24
Finished	Jan 10 01:22:11 PM PST 24
Peak memory	381100 kb
Host	smart-c696a948-9419-413f-a5f3-31180c8bfc9b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1936174345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.1936174345 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_384.3081030625
Short name	T593
Test name
Test status
Simulation time	71688540561 ps
CPU time	1813.71 seconds
Started	Jan 10 12:51:25 PM PST 24
Finished	Jan 10 01:22:55 PM PST 24
Peak memory	344024 kb
Host	smart-ca38ea05-7833-4f15-a77a-10f0a9a3a5f7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3081030625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.3081030625 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_512.4189338618
Short name	T972
Test name
Test status
Simulation time	34133635508 ps
CPU time	1182.1 seconds
Started	Jan 10 12:51:21 PM PST 24
Finished	Jan 10 01:12:28 PM PST 24
Peak memory	299852 kb
Host	smart-bb674608-b135-4038-ae14-bd7ef866eb15
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4189338618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.4189338618 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_shake_128.817834377
Short name	T385
Test name
Test status
Simulation time	60763294355 ps
CPU time	4766.8 seconds
Started	Jan 10 12:52:13 PM PST 24
Finished	Jan 10 02:12:52 PM PST 24
Peak memory	645816 kb
Host	smart-4a845550-4880-4dff-8e33-258f92b7f78f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=817834377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.817834377 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_shake_256.2435628688
Short name	T522
Test name
Test status
Simulation time	90742023420 ps
CPU time	4481.34 seconds
Started	Jan 10 12:51:27 PM PST 24
Finished	Jan 10 02:07:40 PM PST 24
Peak memory	580256 kb
Host	smart-1f40db51-20c2-4d2e-8924-d3481e11c861
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2435628688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.2435628688 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/21.kmac_alert_test.629799078
Short name	T880
Test name
Test status
Simulation time	18705244 ps
CPU time	0.86 seconds
Started	Jan 10 12:51:27 PM PST 24
Finished	Jan 10 12:52:47 PM PST 24
Peak memory	220188 kb
Host	smart-89b4e881-033f-4ac8-9eae-df48abe25711
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629799078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.629799078 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_alert_test/latest

Test location	/workspace/coverage/default/21.kmac_app.3208714263
Short name	T766
Test name
Test status
Simulation time	3624069031 ps
CPU time	82.07 seconds
Started	Jan 10 12:51:17 PM PST 24
Finished	Jan 10 12:53:53 PM PST 24
Peak memory	233544 kb
Host	smart-b49fade9-e6ac-4601-801f-b5146ee82531
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3208714263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.3208714263 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_app/latest

Test location	/workspace/coverage/default/21.kmac_entropy_refresh.530786620
Short name	T539
Test name
Test status
Simulation time	5292804801 ps
CPU time	247.37 seconds
Started	Jan 10 12:51:23 PM PST 24
Finished	Jan 10 12:56:49 PM PST 24
Peak memory	245756 kb
Host	smart-72793810-735a-40e8-a91b-5cd0142631e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=530786620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.530786620 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/21.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/21.kmac_key_error.2638560071
Short name	T333
Test name
Test status
Simulation time	4841902065 ps
CPU time	5.71 seconds
Started	Jan 10 12:51:37 PM PST 24
Finished	Jan 10 12:53:07 PM PST 24
Peak memory	219248 kb
Host	smart-e32352d9-67d7-4497-ac58-072aa2a30c97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2638560071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.2638560071 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_key_error/latest

Test location	/workspace/coverage/default/21.kmac_lc_escalation.3121425907
Short name	T259
Test name
Test status
Simulation time	35913936 ps
CPU time	1.7 seconds
Started	Jan 10 12:51:43 PM PST 24
Finished	Jan 10 12:53:08 PM PST 24
Peak memory	221996 kb
Host	smart-060d4328-4952-4dba-9d10-d4decf3c578b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3121425907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.3121425907 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/21.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/21.kmac_long_msg_and_output.294833106
Short name	T750
Test name
Test status
Simulation time	251065354776 ps
CPU time	896.45 seconds
Started	Jan 10 12:51:26 PM PST 24
Finished	Jan 10 01:07:42 PM PST 24
Peak memory	295388 kb
Host	smart-1850d3fc-6d9f-403c-92aa-72dbe4513550
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294833106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_an d_output.294833106 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/21.kmac_sideload.1827240772
Short name	T166
Test name
Test status
Simulation time	5738348812 ps
CPU time	295.6 seconds
Started	Jan 10 12:52:13 PM PST 24
Finished	Jan 10 12:58:20 PM PST 24
Peak memory	249332 kb
Host	smart-70c3ac95-f91e-4163-b8a4-d82ff6ca1734
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1827240772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.1827240772 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_sideload/latest

Test location	/workspace/coverage/default/21.kmac_smoke.4163165531
Short name	T528
Test name
Test status
Simulation time	1077956640 ps
CPU time	40.55 seconds
Started	Jan 10 12:51:40 PM PST 24
Finished	Jan 10 12:53:55 PM PST 24
Peak memory	227212 kb
Host	smart-2dd7b2f9-0a3d-40c6-8867-710f42730b2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4163165531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.4163165531 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_smoke/latest

Test location	/workspace/coverage/default/21.kmac_stress_all_with_rand_reset.1821671310
Short name	T71
Test name
Test status
Simulation time	35523745121 ps
CPU time	920.41 seconds
Started	Jan 10 12:51:26 PM PST 24
Finished	Jan 10 01:08:06 PM PST 24
Peak memory	296512 kb
Host	smart-2de7be41-f351-46eb-95e2-c7b06aa8ff37
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1821671310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all_with_rand_reset.1821671310 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_kmac.1983924825
Short name	T649
Test name
Test status
Simulation time	110315016 ps
CPU time	5.44 seconds
Started	Jan 10 12:51:20 PM PST 24
Finished	Jan 10 12:52:40 PM PST 24
Peak memory	220604 kb
Host	smart-3388d3ef-6fd5-41e8-a406-b66d107e3286
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983924825 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 21.kmac_test_vectors_kmac.1983924825 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_kmac_xof.940728745
Short name	T212
Test name
Test status
Simulation time	224708263 ps
CPU time	4.91 seconds
Started	Jan 10 12:51:28 PM PST 24
Finished	Jan 10 12:52:49 PM PST 24
Peak memory	219240 kb
Host	smart-224761fa-620e-4fa9-958f-211b32bfe2d3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940728745 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 21.kmac_test_vectors_kmac_xof.940728745 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_224.2094422301
Short name	T629
Test name
Test status
Simulation time	607265421080 ps
CPU time	2488.9 seconds
Started	Jan 10 12:51:23 PM PST 24
Finished	Jan 10 01:34:12 PM PST 24
Peak memory	407268 kb
Host	smart-48696b35-acbd-4718-9b3f-e22c337a3461
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2094422301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.2094422301 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_256.1626706273
Short name	T1020
Test name
Test status
Simulation time	20053726399 ps
CPU time	1751.42 seconds
Started	Jan 10 12:51:52 PM PST 24
Finished	Jan 10 01:22:20 PM PST 24
Peak memory	380276 kb
Host	smart-4b731f78-151b-48b5-a051-107ed2ae4d20
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1626706273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.1626706273 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_384.2889613968
Short name	T559
Test name
Test status
Simulation time	15721580620 ps
CPU time	1450.29 seconds
Started	Jan 10 12:51:57 PM PST 24
Finished	Jan 10 01:17:29 PM PST 24
Peak memory	344396 kb
Host	smart-1bc2f566-4720-4299-8f68-1d7bc12ee43a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2889613968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.2889613968 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_512.961141830
Short name	T1104
Test name
Test status
Simulation time	11504513804 ps
CPU time	1090.83 seconds
Started	Jan 10 12:51:31 PM PST 24
Finished	Jan 10 01:11:01 PM PST 24
Peak memory	303292 kb
Host	smart-21059818-5f44-46d3-8d4f-7a70d678d10b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=961141830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.961141830 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_shake_128.1721736682
Short name	T901
Test name
Test status
Simulation time	183772566276 ps
CPU time	5209.38 seconds
Started	Jan 10 12:51:34 PM PST 24
Finished	Jan 10 02:19:39 PM PST 24
Peak memory	652980 kb
Host	smart-543ce06c-0f10-4da5-bd3e-f002f24f52bd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1721736682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.1721736682 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_shake_256.1672336196
Short name	T782
Test name
Test status
Simulation time	445515550598 ps
CPU time	5012.33 seconds
Started	Jan 10 12:51:31 PM PST 24
Finished	Jan 10 02:16:20 PM PST 24
Peak memory	565620 kb
Host	smart-5fcb0813-24a9-4841-bf4e-0c591b1472a3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1672336196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.1672336196 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/22.kmac_alert_test.572277623
Short name	T1094
Test name
Test status
Simulation time	34398936 ps
CPU time	0.82 seconds
Started	Jan 10 12:51:25 PM PST 24
Finished	Jan 10 12:52:41 PM PST 24
Peak memory	220168 kb
Host	smart-ff7e689a-05c4-4ef9-8c80-04bb0e183d4b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572277623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.572277623 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_alert_test/latest

Test location	/workspace/coverage/default/22.kmac_app.4008940474
Short name	T202
Test name
Test status
Simulation time	11203011624 ps
CPU time	150.24 seconds
Started	Jan 10 12:51:35 PM PST 24
Finished	Jan 10 12:55:23 PM PST 24
Peak memory	239424 kb
Host	smart-eeaac590-ef56-4232-863c-a956539bbd5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4008940474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.4008940474 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_app/latest

Test location	/workspace/coverage/default/22.kmac_burst_write.856157884
Short name	T660
Test name
Test status
Simulation time	58984108835 ps
CPU time	1510.56 seconds
Started	Jan 10 12:51:23 PM PST 24
Finished	Jan 10 01:17:53 PM PST 24
Peak memory	243916 kb
Host	smart-6c30462c-d2d5-400b-8b2a-27839ba94dd0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=856157884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.856157884 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_burst_write/latest

Test location	/workspace/coverage/default/22.kmac_entropy_refresh.1132661498
Short name	T81
Test name
Test status
Simulation time	44484261240 ps
CPU time	374.36 seconds
Started	Jan 10 12:51:27 PM PST 24
Finished	Jan 10 12:59:12 PM PST 24
Peak memory	254260 kb
Host	smart-9a8ad95d-6a55-4c61-a157-7d40f75569b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1132661498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.1132661498 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/22.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/22.kmac_error.1881273740
Short name	T143
Test name
Test status
Simulation time	29424995571 ps
CPU time	90.89 seconds
Started	Jan 10 12:51:24 PM PST 24
Finished	Jan 10 12:54:30 PM PST 24
Peak memory	241336 kb
Host	smart-20eea777-8775-4b07-b445-1582bf39d16c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1881273740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.1881273740 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_error/latest

Test location	/workspace/coverage/default/22.kmac_key_error.2153705133
Short name	T31
Test name
Test status
Simulation time	69906115 ps
CPU time	1.19 seconds
Started	Jan 10 12:51:22 PM PST 24
Finished	Jan 10 12:52:43 PM PST 24
Peak memory	219096 kb
Host	smart-c7bab25b-e054-4d87-b9b6-d1229bcfd4f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2153705133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.2153705133 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_key_error/latest

Test location	/workspace/coverage/default/22.kmac_lc_escalation.273785913
Short name	T415
Test name
Test status
Simulation time	29967856 ps
CPU time	1.33 seconds
Started	Jan 10 12:51:26 PM PST 24
Finished	Jan 10 12:52:46 PM PST 24
Peak memory	220468 kb
Host	smart-65af66d2-89be-4fd1-a66c-4719090828a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=273785913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.273785913 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/22.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/22.kmac_long_msg_and_output.383097974
Short name	T702
Test name
Test status
Simulation time	37665634732 ps
CPU time	1184.35 seconds
Started	Jan 10 12:52:11 PM PST 24
Finished	Jan 10 01:13:16 PM PST 24
Peak memory	331780 kb
Host	smart-30bdc19f-2e41-452a-a010-7d0c6861750a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383097974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_an d_output.383097974 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/22.kmac_sideload.4083346396
Short name	T695
Test name
Test status
Simulation time	8107206539 ps
CPU time	187.88 seconds
Started	Jan 10 12:51:59 PM PST 24
Finished	Jan 10 12:56:28 PM PST 24
Peak memory	243408 kb
Host	smart-39cd4093-0a6b-4f14-8c68-a1c86f462d24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4083346396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.4083346396 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_sideload/latest

Test location	/workspace/coverage/default/22.kmac_smoke.4170444258
Short name	T307
Test name
Test status
Simulation time	4736540348 ps
CPU time	75.95 seconds
Started	Jan 10 12:51:27 PM PST 24
Finished	Jan 10 12:54:18 PM PST 24
Peak memory	224536 kb
Host	smart-33e57681-f5cb-4f4e-a7c3-3fb2bbb68325
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4170444258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.4170444258 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_smoke/latest

Test location	/workspace/coverage/default/22.kmac_stress_all.1627442870
Short name	T674
Test name
Test status
Simulation time	50729575316 ps
CPU time	772.58 seconds
Started	Jan 10 12:51:50 PM PST 24
Finished	Jan 10 01:05:59 PM PST 24
Peak memory	336920 kb
Host	smart-b1987e9f-f8b9-448b-9ee8-0d46fa4ed89a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1627442870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.1627442870 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_stress_all/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_kmac.3674499957
Short name	T994
Test name
Test status
Simulation time	130137541 ps
CPU time	5.43 seconds
Started	Jan 10 12:51:39 PM PST 24
Finished	Jan 10 12:53:00 PM PST 24
Peak memory	220768 kb
Host	smart-54f7e190-823a-408a-bbe1-c9163068c0b3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674499957 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 22.kmac_test_vectors_kmac.3674499957 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_kmac_xof.869219106
Short name	T1108
Test name
Test status
Simulation time	222897675 ps
CPU time	5.81 seconds
Started	Jan 10 12:51:36 PM PST 24
Finished	Jan 10 12:53:02 PM PST 24
Peak memory	219356 kb
Host	smart-e20ee22c-a76e-4c4f-9819-bac1ad3d8431
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869219106 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 22.kmac_test_vectors_kmac_xof.869219106 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_224.2075750851
Short name	T234
Test name
Test status
Simulation time	120443417799 ps
CPU time	2071.35 seconds
Started	Jan 10 12:51:29 PM PST 24
Finished	Jan 10 01:27:20 PM PST 24
Peak memory	408244 kb
Host	smart-5073a8ce-cf6a-4d8b-9d8b-437344e17c46
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2075750851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.2075750851 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_256.1973903724
Short name	T746
Test name
Test status
Simulation time	38884192140 ps
CPU time	1972.61 seconds
Started	Jan 10 12:51:23 PM PST 24
Finished	Jan 10 01:25:30 PM PST 24
Peak memory	382372 kb
Host	smart-be24eda1-5eb4-4ca8-ac7a-ea3d583d31cc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1973903724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.1973903724 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_384.633086079
Short name	T538
Test name
Test status
Simulation time	31832087366 ps
CPU time	1465.72 seconds
Started	Jan 10 12:51:37 PM PST 24
Finished	Jan 10 01:17:24 PM PST 24
Peak memory	338164 kb
Host	smart-5f339ea6-9d23-491a-97b0-b80eabaedfbf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=633086079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.633086079 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_512.367891400
Short name	T395
Test name
Test status
Simulation time	43682732739 ps
CPU time	1181.15 seconds
Started	Jan 10 12:51:57 PM PST 24
Finished	Jan 10 01:13:01 PM PST 24
Peak memory	305324 kb
Host	smart-426b906f-d8bb-4de9-bdfa-21f930edfb3f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=367891400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.367891400 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_shake_128.310880682
Short name	T242
Test name
Test status
Simulation time	189966717401 ps
CPU time	5592 seconds
Started	Jan 10 12:51:54 PM PST 24
Finished	Jan 10 02:26:20 PM PST 24
Peak memory	667104 kb
Host	smart-ded64e3f-3220-4d09-8583-a11fefb88bfb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=310880682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.310880682 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_shake_256.1458464902
Short name	T295
Test name
Test status
Simulation time	52951079057 ps
CPU time	4376.17 seconds
Started	Jan 10 12:51:51 PM PST 24
Finished	Jan 10 02:06:05 PM PST 24
Peak memory	569852 kb
Host	smart-416efbf1-680c-4790-8b07-19bc92c87baf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1458464902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.1458464902 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/23.kmac_alert_test.3210328374
Short name	T257
Test name
Test status
Simulation time	22696311 ps
CPU time	0.82 seconds
Started	Jan 10 12:51:35 PM PST 24
Finished	Jan 10 12:52:53 PM PST 24
Peak memory	219092 kb
Host	smart-df10c6f0-be2f-4bb1-acc7-c2cea0a9e0cb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210328374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.3210328374 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_alert_test/latest

Test location	/workspace/coverage/default/23.kmac_burst_write.2910847794
Short name	T871
Test name
Test status
Simulation time	6926320568 ps
CPU time	321.07 seconds
Started	Jan 10 12:51:28 PM PST 24
Finished	Jan 10 12:58:10 PM PST 24
Peak memory	241460 kb
Host	smart-df27be4a-702f-47d0-9776-ed537e6882fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2910847794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.2910847794 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_burst_write/latest

Test location	/workspace/coverage/default/23.kmac_entropy_refresh.1215512423
Short name	T17
Test name
Test status
Simulation time	9964476451 ps
CPU time	76.01 seconds
Started	Jan 10 12:51:54 PM PST 24
Finished	Jan 10 12:54:33 PM PST 24
Peak memory	241280 kb
Host	smart-cd317d47-8242-467c-a292-5a7ead5cfd79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1215512423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.1215512423 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/23.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/23.kmac_error.3401754865
Short name	T944
Test name
Test status
Simulation time	760595781 ps
CPU time	15.14 seconds
Started	Jan 10 12:51:57 PM PST 24
Finished	Jan 10 12:53:35 PM PST 24
Peak memory	241328 kb
Host	smart-23707dbd-965c-457e-8002-4e167800418e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3401754865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.3401754865 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_error/latest

Test location	/workspace/coverage/default/23.kmac_lc_escalation.3197823482
Short name	T397
Test name
Test status
Simulation time	56914981 ps
CPU time	1.43 seconds
Started	Jan 10 12:51:26 PM PST 24
Finished	Jan 10 12:52:42 PM PST 24
Peak memory	220460 kb
Host	smart-5e5bd0a7-0b94-47fb-9ab7-15bf5685199f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3197823482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.3197823482 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/23.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/23.kmac_long_msg_and_output.2094722212
Short name	T281
Test name
Test status
Simulation time	11832271115 ps
CPU time	104.24 seconds
Started	Jan 10 12:51:28 PM PST 24
Finished	Jan 10 12:54:32 PM PST 24
Peak memory	236416 kb
Host	smart-3c9a06bd-a929-4a53-9eda-411bf1a91ace
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094722212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a nd_output.2094722212 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/23.kmac_sideload.3737229163
Short name	T937
Test name
Test status
Simulation time	5348413228 ps
CPU time	173.02 seconds
Started	Jan 10 12:51:56 PM PST 24
Finished	Jan 10 12:56:02 PM PST 24
Peak memory	240064 kb
Host	smart-ddc2fca4-159b-404b-b24a-28a52070dfd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3737229163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.3737229163 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_sideload/latest

Test location	/workspace/coverage/default/23.kmac_smoke.1387769699
Short name	T749
Test name
Test status
Simulation time	2761553158 ps
CPU time	50.36 seconds
Started	Jan 10 12:51:49 PM PST 24
Finished	Jan 10 12:53:51 PM PST 24
Peak memory	227576 kb
Host	smart-1a21be21-bc2c-44fd-87bf-02886d306d7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1387769699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.1387769699 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_smoke/latest

Test location	/workspace/coverage/default/23.kmac_stress_all.3158429093
Short name	T362
Test name
Test status
Simulation time	63920519013 ps
CPU time	1092.3 seconds
Started	Jan 10 12:52:03 PM PST 24
Finished	Jan 10 01:11:48 PM PST 24
Peak memory	321064 kb
Host	smart-27911af0-b2a9-402d-878f-35d44b4c357b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3158429093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.3158429093 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_stress_all/latest

Test location	/workspace/coverage/default/23.kmac_stress_all_with_rand_reset.4018092273
Short name	T918
Test name
Test status
Simulation time	65310065008 ps
CPU time	1189.39 seconds
Started	Jan 10 12:51:24 PM PST 24
Finished	Jan 10 01:12:38 PM PST 24
Peak memory	293192 kb
Host	smart-df9d9e7d-1de8-4a14-be12-369f89b5c580
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4018092273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all_with_rand_reset.4018092273 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_kmac.2479891825
Short name	T1102
Test name
Test status
Simulation time	254305108 ps
CPU time	5.81 seconds
Started	Jan 10 12:52:00 PM PST 24
Finished	Jan 10 12:53:22 PM PST 24
Peak memory	220640 kb
Host	smart-63cc8241-5baf-4cec-a043-759c1c0f7659
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479891825 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 23.kmac_test_vectors_kmac.2479891825 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_kmac_xof.1701381272
Short name	T323
Test name
Test status
Simulation time	1310659596 ps
CPU time	6.12 seconds
Started	Jan 10 12:51:31 PM PST 24
Finished	Jan 10 12:53:00 PM PST 24
Peak memory	219140 kb
Host	smart-5bd8f3af-13e6-4fb1-99be-848674743e14
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701381272 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_kmac_xof.1701381272 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_224.655120529
Short name	T741
Test name
Test status
Simulation time	138152200399 ps
CPU time	2230.95 seconds
Started	Jan 10 12:51:28 PM PST 24
Finished	Jan 10 01:29:59 PM PST 24
Peak memory	404168 kb
Host	smart-3568f092-f051-48b1-951e-c26def31ed26
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=655120529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.655120529 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_256.401714288
Short name	T857
Test name
Test status
Simulation time	39934176101 ps
CPU time	1820.61 seconds
Started	Jan 10 12:52:00 PM PST 24
Finished	Jan 10 01:23:33 PM PST 24
Peak memory	400128 kb
Host	smart-16e99880-407a-4f14-8bce-b136efc71149
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=401714288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.401714288 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_384.1774791085
Short name	T683
Test name
Test status
Simulation time	75922276535 ps
CPU time	1747.35 seconds
Started	Jan 10 12:51:20 PM PST 24
Finished	Jan 10 01:21:48 PM PST 24
Peak memory	345416 kb
Host	smart-08f23027-f9c3-4fe8-b40e-d525c7ad5c86
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1774791085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.1774791085 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_512.1806734550
Short name	T843
Test name
Test status
Simulation time	21481500153 ps
CPU time	1120.2 seconds
Started	Jan 10 12:51:34 PM PST 24
Finished	Jan 10 01:11:33 PM PST 24
Peak memory	304252 kb
Host	smart-11e791b0-5f62-45df-b5f4-8f58ac9dc2b0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1806734550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.1806734550 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_shake_128.732831650
Short name	T784
Test name
Test status
Simulation time	63281139735 ps
CPU time	4860.11 seconds
Started	Jan 10 12:51:45 PM PST 24
Finished	Jan 10 02:14:00 PM PST 24
Peak memory	670204 kb
Host	smart-d6f06f5f-8581-4a97-b390-2630f0e090da
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=732831650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.732831650 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_shake_256.1178980406
Short name	T544
Test name
Test status
Simulation time	215397651008 ps
CPU time	4098.64 seconds
Started	Jan 10 12:51:20 PM PST 24
Finished	Jan 10 02:00:54 PM PST 24
Peak memory	557728 kb
Host	smart-ecfb1a3f-cfe4-4119-b393-9909c4b5a9bd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1178980406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.1178980406 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/24.kmac_alert_test.2272136613
Short name	T352
Test name
Test status
Simulation time	23142120 ps
CPU time	0.85 seconds
Started	Jan 10 12:51:52 PM PST 24
Finished	Jan 10 12:53:09 PM PST 24
Peak memory	219056 kb
Host	smart-1893dff8-e6a7-464a-ba41-1777f1bf0cfa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272136613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.2272136613 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_alert_test/latest

Test location	/workspace/coverage/default/24.kmac_app.1805198543
Short name	T701
Test name
Test status
Simulation time	32670441214 ps
CPU time	164.3 seconds
Started	Jan 10 12:51:33 PM PST 24
Finished	Jan 10 12:55:35 PM PST 24
Peak memory	243908 kb
Host	smart-50fe75b8-5c0d-44f9-b6d7-61df671af43f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1805198543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.1805198543 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_app/latest

Test location	/workspace/coverage/default/24.kmac_burst_write.146056655
Short name	T228
Test name
Test status
Simulation time	3538008370 ps
CPU time	326.66 seconds
Started	Jan 10 12:51:34 PM PST 24
Finished	Jan 10 12:58:26 PM PST 24
Peak memory	240960 kb
Host	smart-dca97d54-43f5-4219-ac60-b5229ed688f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=146056655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.146056655 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_burst_write/latest

Test location	/workspace/coverage/default/24.kmac_entropy_refresh.654536399
Short name	T790
Test name
Test status
Simulation time	10826719278 ps
CPU time	206.03 seconds
Started	Jan 10 12:51:34 PM PST 24
Finished	Jan 10 12:56:15 PM PST 24
Peak memory	245516 kb
Host	smart-00ad5a33-e767-4e50-afd2-b9b345457dc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=654536399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.654536399 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/24.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/24.kmac_error.1430859504
Short name	T518
Test name
Test status
Simulation time	18288621421 ps
CPU time	339.97 seconds
Started	Jan 10 12:52:02 PM PST 24
Finished	Jan 10 12:59:05 PM PST 24
Peak memory	260232 kb
Host	smart-ccf05a7f-c9cc-4008-9d7f-ff93ef7fe4f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1430859504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.1430859504 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_error/latest

Test location	/workspace/coverage/default/24.kmac_key_error.999333000
Short name	T771
Test name
Test status
Simulation time	678601068 ps
CPU time	4.38 seconds
Started	Jan 10 12:51:38 PM PST 24
Finished	Jan 10 12:52:55 PM PST 24
Peak memory	219140 kb
Host	smart-f8101989-9c9a-4098-9876-ff4d9e2cc953
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=999333000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.999333000 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_key_error/latest

Test location	/workspace/coverage/default/24.kmac_lc_escalation.4279545812
Short name	T15
Test name
Test status
Simulation time	105497678 ps
CPU time	1.41 seconds
Started	Jan 10 12:51:35 PM PST 24
Finished	Jan 10 12:52:54 PM PST 24
Peak memory	220344 kb
Host	smart-4f632f23-27aa-4cbc-bc5f-01bca78583d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4279545812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.4279545812 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/24.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/24.kmac_long_msg_and_output.2833444111
Short name	T1038
Test name
Test status
Simulation time	306611779184 ps
CPU time	2741.75 seconds
Started	Jan 10 12:51:19 PM PST 24
Finished	Jan 10 01:38:21 PM PST 24
Peak memory	448672 kb
Host	smart-8a2bced2-d905-41d7-9e8f-0b6739a516c8
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833444111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a nd_output.2833444111 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/24.kmac_sideload.2602028790
Short name	T248
Test name
Test status
Simulation time	42420962186 ps
CPU time	281.25 seconds
Started	Jan 10 12:51:35 PM PST 24
Finished	Jan 10 12:57:38 PM PST 24
Peak memory	247008 kb
Host	smart-e35b4eb1-2bfb-4f74-90ed-512587ca6ea6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2602028790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.2602028790 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_sideload/latest

Test location	/workspace/coverage/default/24.kmac_smoke.3261612939
Short name	T217
Test name
Test status
Simulation time	13058324385 ps
CPU time	112.07 seconds
Started	Jan 10 12:51:21 PM PST 24
Finished	Jan 10 12:54:32 PM PST 24
Peak memory	227628 kb
Host	smart-9255cc09-9845-4b9e-b226-26d720cb4195
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3261612939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.3261612939 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_smoke/latest

Test location	/workspace/coverage/default/24.kmac_stress_all.1209251102
Short name	T881
Test name
Test status
Simulation time	41059391347 ps
CPU time	1347.03 seconds
Started	Jan 10 12:51:38 PM PST 24
Finished	Jan 10 01:15:26 PM PST 24
Peak memory	388852 kb
Host	smart-6ee54058-92c3-4906-aac5-f454f7620986
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1209251102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.1209251102 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_stress_all/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_kmac.576192898
Short name	T789
Test name
Test status
Simulation time	805405387 ps
CPU time	6.13 seconds
Started	Jan 10 12:51:41 PM PST 24
Finished	Jan 10 12:52:59 PM PST 24
Peak memory	220840 kb
Host	smart-24d84893-5a6b-4418-8ca0-d322f792c9ed
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576192898 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 24.kmac_test_vectors_kmac.576192898 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_kmac_xof.4051340587
Short name	T261
Test name
Test status
Simulation time	260823216 ps
CPU time	5.56 seconds
Started	Jan 10 12:52:03 PM PST 24
Finished	Jan 10 12:53:28 PM PST 24
Peak memory	220948 kb
Host	smart-4a044340-fdbe-4982-8a6c-39853a1c35af
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051340587 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_kmac_xof.4051340587 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_224.2277236410
Short name	T1000
Test name
Test status
Simulation time	87449275522 ps
CPU time	1885.29 seconds
Started	Jan 10 12:51:34 PM PST 24
Finished	Jan 10 01:24:14 PM PST 24
Peak memory	398344 kb
Host	smart-67259b6f-a8a1-4961-83cb-dc43afe990e8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2277236410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.2277236410 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_256.3297408848
Short name	T245
Test name
Test status
Simulation time	41441536631 ps
CPU time	1779.07 seconds
Started	Jan 10 12:51:31 PM PST 24
Finished	Jan 10 01:22:29 PM PST 24
Peak memory	379264 kb
Host	smart-d58cce6b-44b5-4a8d-843d-42815b5f868a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3297408848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.3297408848 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_384.426475592
Short name	T865
Test name
Test status
Simulation time	118915186305 ps
CPU time	1685.39 seconds
Started	Jan 10 12:51:41 PM PST 24
Finished	Jan 10 01:21:11 PM PST 24
Peak memory	339048 kb
Host	smart-b7cb4c22-8c86-451d-be39-e9cb27a7cb72
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=426475592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.426475592 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_512.3884891303
Short name	T892
Test name
Test status
Simulation time	50934647050 ps
CPU time	1304.72 seconds
Started	Jan 10 12:51:37 PM PST 24
Finished	Jan 10 01:14:43 PM PST 24
Peak memory	303664 kb
Host	smart-324643e1-785a-4310-a5ab-692b4d955ea7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3884891303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.3884891303 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_shake_128.4108739521
Short name	T729
Test name
Test status
Simulation time	62876153641 ps
CPU time	5113.94 seconds
Started	Jan 10 12:51:38 PM PST 24
Finished	Jan 10 02:18:06 PM PST 24
Peak memory	656816 kb
Host	smart-b2a14c1e-1846-470a-961d-ac1e025187a6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4108739521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.4108739521 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_shake_256.2399504616
Short name	T1092
Test name
Test status
Simulation time	603047047537 ps
CPU time	5199.08 seconds
Started	Jan 10 12:51:38 PM PST 24
Finished	Jan 10 02:19:34 PM PST 24
Peak memory	575948 kb
Host	smart-7d09b686-e8dc-4151-ba5f-f8b8d6c2e09f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2399504616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.2399504616 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/25.kmac_alert_test.3605429761
Short name	T1050
Test name
Test status
Simulation time	25596751 ps
CPU time	0.83 seconds
Started	Jan 10 12:51:54 PM PST 24
Finished	Jan 10 12:53:07 PM PST 24
Peak memory	219092 kb
Host	smart-44e949f7-3a34-4d4d-bdbb-9bec95c0cd97
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605429761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.3605429761 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_alert_test/latest

Test location	/workspace/coverage/default/25.kmac_app.377990394
Short name	T578
Test name
Test status
Simulation time	4675339536 ps
CPU time	84.48 seconds
Started	Jan 10 12:51:29 PM PST 24
Finished	Jan 10 12:54:08 PM PST 24
Peak memory	234752 kb
Host	smart-db912f43-1153-478d-8a76-8eba420b61f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=377990394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.377990394 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_app/latest

Test location	/workspace/coverage/default/25.kmac_burst_write.1097069315
Short name	T962
Test name
Test status
Simulation time	84312229422 ps
CPU time	765.91 seconds
Started	Jan 10 12:52:00 PM PST 24
Finished	Jan 10 01:06:08 PM PST 24
Peak memory	237908 kb
Host	smart-82f28ee9-d2ab-4dd4-91fc-6951dcd27fff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1097069315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.1097069315 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_burst_write/latest

Test location	/workspace/coverage/default/25.kmac_entropy_refresh.78784309
Short name	T667
Test name
Test status
Simulation time	59762815802 ps
CPU time	351.27 seconds
Started	Jan 10 12:51:40 PM PST 24
Finished	Jan 10 12:58:45 PM PST 24
Peak memory	250856 kb
Host	smart-3aa3d90f-257d-4b7d-8e29-06d10a1629fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78784309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.78784309 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/25.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/25.kmac_error.1067104729
Short name	T777
Test name
Test status
Simulation time	21052314027 ps
CPU time	326.11 seconds
Started	Jan 10 12:51:48 PM PST 24
Finished	Jan 10 12:58:38 PM PST 24
Peak memory	260292 kb
Host	smart-8b5ddff2-f1ed-4b1a-9f72-dbdd63a7cdb5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1067104729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.1067104729 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_error/latest

Test location	/workspace/coverage/default/25.kmac_key_error.2628160975
Short name	T107
Test name
Test status
Simulation time	1163121453 ps
CPU time	6.65 seconds
Started	Jan 10 12:51:36 PM PST 24
Finished	Jan 10 12:53:18 PM PST 24
Peak memory	219176 kb
Host	smart-d0ae9126-7e2f-4316-afb4-e6da4423e730
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2628160975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.2628160975 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_key_error/latest

Test location	/workspace/coverage/default/25.kmac_lc_escalation.1726586746
Short name	T334
Test name
Test status
Simulation time	348753224 ps
CPU time	1.36 seconds
Started	Jan 10 12:52:07 PM PST 24
Finished	Jan 10 12:53:20 PM PST 24
Peak memory	220384 kb
Host	smart-414683f3-c54f-4d5a-90f5-3cd7fedd86a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1726586746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.1726586746 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/25.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/25.kmac_long_msg_and_output.761828237
Short name	T209
Test name
Test status
Simulation time	21094585733 ps
CPU time	2300.47 seconds
Started	Jan 10 12:51:40 PM PST 24
Finished	Jan 10 01:31:14 PM PST 24
Peak memory	420344 kb
Host	smart-cb3892e0-3b73-46c5-b84e-c2c3db4ac89e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761828237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_an d_output.761828237 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/25.kmac_sideload.555246811
Short name	T1031
Test name
Test status
Simulation time	47522714368 ps
CPU time	300.97 seconds
Started	Jan 10 12:51:29 PM PST 24
Finished	Jan 10 12:57:44 PM PST 24
Peak memory	247560 kb
Host	smart-834b361c-3731-48d0-b7dc-4fb68b00ac06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=555246811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.555246811 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_sideload/latest

Test location	/workspace/coverage/default/25.kmac_smoke.4184947517
Short name	T714
Test name
Test status
Simulation time	1520153512 ps
CPU time	29.97 seconds
Started	Jan 10 12:51:38 PM PST 24
Finished	Jan 10 12:53:29 PM PST 24
Peak memory	227428 kb
Host	smart-a00945f5-ad4f-4428-bf7a-fa74f176fdb5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4184947517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.4184947517 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_smoke/latest

Test location	/workspace/coverage/default/25.kmac_stress_all_with_rand_reset.1555895158
Short name	T786
Test name
Test status
Simulation time	99086612776 ps
CPU time	651.99 seconds
Started	Jan 10 12:51:35 PM PST 24
Finished	Jan 10 01:03:49 PM PST 24
Peak memory	295188 kb
Host	smart-93395657-dd3d-43ae-ba12-9748c41554e6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1555895158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all_with_rand_reset.1555895158 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_kmac.124225564
Short name	T665
Test name
Test status
Simulation time	147958336 ps
CPU time	6.09 seconds
Started	Jan 10 12:51:50 PM PST 24
Finished	Jan 10 12:53:19 PM PST 24
Peak memory	220776 kb
Host	smart-2711264d-2771-4ceb-94e7-94437acd3412
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124225564 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 25.kmac_test_vectors_kmac.124225564 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_kmac_xof.1402668684
Short name	T109
Test name
Test status
Simulation time	492698555 ps
CPU time	6.93 seconds
Started	Jan 10 12:51:34 PM PST 24
Finished	Jan 10 12:52:56 PM PST 24
Peak memory	220640 kb
Host	smart-baed1545-b565-415b-a036-a1faf993c756
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402668684 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_kmac_xof.1402668684 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_224.576213080
Short name	T199
Test name
Test status
Simulation time	200267336042 ps
CPU time	2370.95 seconds
Started	Jan 10 12:51:35 PM PST 24
Finished	Jan 10 01:32:24 PM PST 24
Peak memory	403644 kb
Host	smart-33be40ed-7b65-4435-accd-d46c1a072654
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=576213080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.576213080 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_256.778328599
Short name	T773
Test name
Test status
Simulation time	83546123846 ps
CPU time	1851.14 seconds
Started	Jan 10 12:51:39 PM PST 24
Finished	Jan 10 01:23:53 PM PST 24
Peak memory	378828 kb
Host	smart-ccbc1969-0167-4ddb-9cf8-6a807b9c359f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=778328599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.778328599 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_384.1310202310
Short name	T409
Test name
Test status
Simulation time	235741759814 ps
CPU time	1710.07 seconds
Started	Jan 10 12:51:48 PM PST 24
Finished	Jan 10 01:21:32 PM PST 24
Peak memory	342564 kb
Host	smart-6d7dcafa-aefd-4d44-ae85-0fbdddc30c4e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1310202310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.1310202310 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_512.3265148997
Short name	T233
Test name
Test status
Simulation time	100374760039 ps
CPU time	1383.7 seconds
Started	Jan 10 12:51:42 PM PST 24
Finished	Jan 10 01:16:16 PM PST 24
Peak memory	303036 kb
Host	smart-e24ef65c-5e91-4883-ae23-10ba7a4dcf78
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3265148997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.3265148997 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_shake_128.530896065
Short name	T827
Test name
Test status
Simulation time	908539805807 ps
CPU time	5893.55 seconds
Started	Jan 10 12:52:00 PM PST 24
Finished	Jan 10 02:31:27 PM PST 24
Peak memory	665940 kb
Host	smart-b0ead637-d77f-46b5-b42b-750631cc7fd5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=530896065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.530896065 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_shake_256.2642530363
Short name	T710
Test name
Test status
Simulation time	56960456726 ps
CPU time	4589.63 seconds
Started	Jan 10 12:52:06 PM PST 24
Finished	Jan 10 02:09:57 PM PST 24
Peak memory	576924 kb
Host	smart-1df686e3-41ed-4143-8e4e-6566fd338c2f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2642530363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.2642530363 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/26.kmac_alert_test.1586714555
Short name	T668
Test name
Test status
Simulation time	24853518 ps
CPU time	0.83 seconds
Started	Jan 10 12:51:32 PM PST 24
Finished	Jan 10 12:52:52 PM PST 24
Peak memory	219064 kb
Host	smart-740abf74-a3e7-4d67-b367-eb75204c1021
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586714555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.1586714555 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_alert_test/latest

Test location	/workspace/coverage/default/26.kmac_app.3060963823
Short name	T34
Test name
Test status
Simulation time	3565076691 ps
CPU time	185.8 seconds
Started	Jan 10 12:52:11 PM PST 24
Finished	Jan 10 12:56:31 PM PST 24
Peak memory	243324 kb
Host	smart-aa0b8e8a-8769-415f-80a6-35a4a8a9f0de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3060963823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.3060963823 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_app/latest

Test location	/workspace/coverage/default/26.kmac_burst_write.450519920
Short name	T957
Test name
Test status
Simulation time	50162506242 ps
CPU time	807 seconds
Started	Jan 10 12:52:02 PM PST 24
Finished	Jan 10 01:06:41 PM PST 24
Peak memory	243876 kb
Host	smart-6a7e49fd-31f0-4b2e-9f3b-b03dfe5b6f82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=450519920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.450519920 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_burst_write/latest

Test location	/workspace/coverage/default/26.kmac_entropy_refresh.1306589637
Short name	T970
Test name
Test status
Simulation time	15069109632 ps
CPU time	169.36 seconds
Started	Jan 10 12:52:25 PM PST 24
Finished	Jan 10 12:56:25 PM PST 24
Peak memory	239996 kb
Host	smart-4d806d7c-df0b-49e3-8a79-6e538d6083b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1306589637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.1306589637 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/26.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/26.kmac_error.491328007
Short name	T947
Test name
Test status
Simulation time	2561912862 ps
CPU time	29.61 seconds
Started	Jan 10 12:51:39 PM PST 24
Finished	Jan 10 12:53:27 PM PST 24
Peak memory	243928 kb
Host	smart-3ceb9bfc-55a6-4ad5-9e76-11549b8ea328
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=491328007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.491328007 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_error/latest

Test location	/workspace/coverage/default/26.kmac_key_error.2299557641
Short name	T383
Test name
Test status
Simulation time	3996089899 ps
CPU time	5.82 seconds
Started	Jan 10 12:51:48 PM PST 24
Finished	Jan 10 12:53:31 PM PST 24
Peak memory	219324 kb
Host	smart-8922c13b-d5a1-4542-88b9-8c4044385150
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2299557641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.2299557641 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_key_error/latest

Test location	/workspace/coverage/default/26.kmac_lc_escalation.1758682568
Short name	T1006
Test name
Test status
Simulation time	682998549 ps
CPU time	9.07 seconds
Started	Jan 10 12:51:38 PM PST 24
Finished	Jan 10 12:53:03 PM PST 24
Peak memory	238556 kb
Host	smart-cca0120e-e4b0-4c2a-b4fb-7ca14cdb77a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1758682568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.1758682568 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/26.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/26.kmac_long_msg_and_output.3931628318
Short name	T733
Test name
Test status
Simulation time	16660484324 ps
CPU time	428.58 seconds
Started	Jan 10 12:51:33 PM PST 24
Finished	Jan 10 12:59:59 PM PST 24
Peak memory	262676 kb
Host	smart-adbed756-3f57-4f3e-aab8-634c84db56dd
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931628318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a nd_output.3931628318 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/26.kmac_sideload.2323419332
Short name	T685
Test name
Test status
Simulation time	52995154351 ps
CPU time	324.11 seconds
Started	Jan 10 12:52:03 PM PST 24
Finished	Jan 10 12:58:42 PM PST 24
Peak memory	247116 kb
Host	smart-db60df7c-1fe4-4874-976d-487b5c2527ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2323419332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.2323419332 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_sideload/latest

Test location	/workspace/coverage/default/26.kmac_smoke.3021812367
Short name	T312
Test name
Test status
Simulation time	8817753495 ps
CPU time	78.24 seconds
Started	Jan 10 12:52:03 PM PST 24
Finished	Jan 10 12:54:36 PM PST 24
Peak memory	220176 kb
Host	smart-ae0e8c88-aaf4-4e59-a6c9-dfcd43a95136
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3021812367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.3021812367 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_smoke/latest

Test location	/workspace/coverage/default/26.kmac_stress_all.2166353261
Short name	T1044
Test name
Test status
Simulation time	18126210825 ps
CPU time	1014.52 seconds
Started	Jan 10 12:51:39 PM PST 24
Finished	Jan 10 01:09:49 PM PST 24
Peak memory	340348 kb
Host	smart-56200fd0-9f1e-4b09-824c-20005531809d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2166353261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.2166353261 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_stress_all/latest

Test location	/workspace/coverage/default/26.kmac_stress_all_with_rand_reset.966151566
Short name	T634
Test name
Test status
Simulation time	24386726963 ps
CPU time	487.73 seconds
Started	Jan 10 12:51:35 PM PST 24
Finished	Jan 10 01:00:57 PM PST 24
Peak memory	292352 kb
Host	smart-f2b116d5-dafd-4872-81da-d60297d6097c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=966151566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all_with_rand_reset.966151566 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_kmac.2859957207
Short name	T897
Test name
Test status
Simulation time	207345980 ps
CPU time	5.61 seconds
Started	Jan 10 12:51:43 PM PST 24
Finished	Jan 10 12:53:01 PM PST 24
Peak memory	220772 kb
Host	smart-24de6976-1e2c-4acc-8187-a7e62b930d49
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859957207 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 26.kmac_test_vectors_kmac.2859957207 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_kmac_xof.3964954303
Short name	T201
Test name
Test status
Simulation time	382951709 ps
CPU time	5.66 seconds
Started	Jan 10 12:51:43 PM PST 24
Finished	Jan 10 12:53:13 PM PST 24
Peak memory	220608 kb
Host	smart-20d4c37d-adc7-41f4-ae5b-998319615dc0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964954303 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_kmac_xof.3964954303 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_224.3189873196
Short name	T779
Test name
Test status
Simulation time	386804324319 ps
CPU time	2298.89 seconds
Started	Jan 10 12:51:35 PM PST 24
Finished	Jan 10 01:31:11 PM PST 24
Peak memory	398192 kb
Host	smart-d29d12df-769f-4615-8e40-3ef81e949f3a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3189873196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.3189873196 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_256.3407560387
Short name	T179
Test name
Test status
Simulation time	163359526952 ps
CPU time	2161.55 seconds
Started	Jan 10 12:52:02 PM PST 24
Finished	Jan 10 01:29:27 PM PST 24
Peak memory	382268 kb
Host	smart-ee9faed1-89ac-490e-95f0-9c98f7248aa7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3407560387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.3407560387 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_384.1919022589
Short name	T171
Test name
Test status
Simulation time	294296837225 ps
CPU time	1759.19 seconds
Started	Jan 10 12:51:37 PM PST 24
Finished	Jan 10 01:22:10 PM PST 24
Peak memory	343120 kb
Host	smart-47f26bbe-7c3e-447e-91fd-ecb0e5a80607
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1919022589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.1919022589 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_512.345281825
Short name	T221
Test name
Test status
Simulation time	472238086458 ps
CPU time	1382.86 seconds
Started	Jan 10 12:52:07 PM PST 24
Finished	Jan 10 01:16:22 PM PST 24
Peak memory	301672 kb
Host	smart-b644b7c4-6f51-454c-b4a7-c765db3106af
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=345281825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.345281825 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_shake_128.1306931969
Short name	T582
Test name
Test status
Simulation time	517101917556 ps
CPU time	5784.4 seconds
Started	Jan 10 01:21:50 PM PST 24
Finished	Jan 10 02:58:44 PM PST 24
Peak memory	651804 kb
Host	smart-f6239b74-dcc5-4506-9234-a2a568fe8a93
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1306931969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.1306931969 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_shake_256.838654779
Short name	T193
Test name
Test status
Simulation time	232132024243 ps
CPU time	4919.29 seconds
Started	Jan 10 12:51:35 PM PST 24
Finished	Jan 10 02:14:56 PM PST 24
Peak memory	569988 kb
Host	smart-629a3114-32a8-4940-a45a-fd53ff6ad4a8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=838654779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.838654779 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/27.kmac_alert_test.4117790828
Short name	T190
Test name
Test status
Simulation time	12812260 ps
CPU time	0.82 seconds
Started	Jan 10 12:51:40 PM PST 24
Finished	Jan 10 12:52:54 PM PST 24
Peak memory	219212 kb
Host	smart-4a0d0bbe-217f-4172-9f2e-9350539475d4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117790828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.4117790828 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_alert_test/latest

Test location	/workspace/coverage/default/27.kmac_app.1126909252
Short name	T1035
Test name
Test status
Simulation time	3405932186 ps
CPU time	223.63 seconds
Started	Jan 10 12:51:56 PM PST 24
Finished	Jan 10 12:57:03 PM PST 24
Peak memory	246376 kb
Host	smart-ccb74ad8-c4aa-415b-a959-c36c0418bfe3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1126909252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.1126909252 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_app/latest

Test location	/workspace/coverage/default/27.kmac_burst_write.1233837131
Short name	T1019
Test name
Test status
Simulation time	25323374663 ps
CPU time	603.53 seconds
Started	Jan 10 12:51:58 PM PST 24
Finished	Jan 10 01:03:20 PM PST 24
Peak memory	243760 kb
Host	smart-513fc063-1219-483c-8d55-5fda02077d89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1233837131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.1233837131 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_burst_write/latest

Test location	/workspace/coverage/default/27.kmac_entropy_refresh.2871995260
Short name	T572
Test name
Test status
Simulation time	219507950 ps
CPU time	2.72 seconds
Started	Jan 10 12:51:55 PM PST 24
Finished	Jan 10 12:53:12 PM PST 24
Peak memory	225476 kb
Host	smart-bbc322ef-bde9-4190-8719-b6b1c449fc65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2871995260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.2871995260 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/27.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/27.kmac_error.3194280138
Short name	T305
Test name
Test status
Simulation time	1151308284 ps
CPU time	83.65 seconds
Started	Jan 10 12:51:47 PM PST 24
Finished	Jan 10 12:54:27 PM PST 24
Peak memory	244156 kb
Host	smart-0af0b547-97f1-432f-a651-6973689f0263
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3194280138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.3194280138 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_error/latest

Test location	/workspace/coverage/default/27.kmac_key_error.217529795
Short name	T921
Test name
Test status
Simulation time	4840946211 ps
CPU time	5.24 seconds
Started	Jan 10 12:51:56 PM PST 24
Finished	Jan 10 12:53:18 PM PST 24
Peak memory	219376 kb
Host	smart-6ede7246-729d-4a44-be99-5dcf9437f70a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=217529795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.217529795 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_key_error/latest

Test location	/workspace/coverage/default/27.kmac_lc_escalation.934012377
Short name	T606
Test name
Test status
Simulation time	35021021 ps
CPU time	1.31 seconds
Started	Jan 10 12:51:59 PM PST 24
Finished	Jan 10 12:53:13 PM PST 24
Peak memory	220280 kb
Host	smart-2f887604-f7ff-429e-bf17-5550be580b4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=934012377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.934012377 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/27.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/27.kmac_long_msg_and_output.3520389324
Short name	T694
Test name
Test status
Simulation time	16847476742 ps
CPU time	1659.01 seconds
Started	Jan 10 12:51:32 PM PST 24
Finished	Jan 10 01:20:33 PM PST 24
Peak memory	378964 kb
Host	smart-0e6b16a8-92d5-4533-b03b-bb6d558612d2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520389324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a nd_output.3520389324 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/27.kmac_sideload.2042032181
Short name	T574
Test name
Test status
Simulation time	9641397526 ps
CPU time	321.1 seconds
Started	Jan 10 12:51:40 PM PST 24
Finished	Jan 10 12:58:24 PM PST 24
Peak memory	249800 kb
Host	smart-05845ce8-93d2-4c83-992a-65954266d94c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2042032181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.2042032181 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_sideload/latest

Test location	/workspace/coverage/default/27.kmac_smoke.3364104027
Short name	T699
Test name
Test status
Simulation time	27994259976 ps
CPU time	78.31 seconds
Started	Jan 10 12:52:06 PM PST 24
Finished	Jan 10 12:54:39 PM PST 24
Peak memory	224460 kb
Host	smart-85a95ce9-1cc2-4405-b2d9-2e603049aaf0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3364104027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.3364104027 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_smoke/latest

Test location	/workspace/coverage/default/27.kmac_stress_all.3974458542
Short name	T338
Test name
Test status
Simulation time	44426494108 ps
CPU time	1752.27 seconds
Started	Jan 10 12:51:37 PM PST 24
Finished	Jan 10 01:22:15 PM PST 24
Peak memory	419244 kb
Host	smart-53ea19df-280b-4e14-9776-e386643d49d3
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3974458542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.3974458542 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_stress_all/latest

Test location	/workspace/coverage/default/27.kmac_stress_all_with_rand_reset.45940003
Short name	T1072
Test name
Test status
Simulation time	45339023822 ps
CPU time	2366.22 seconds
Started	Jan 10 12:52:01 PM PST 24
Finished	Jan 10 01:32:51 PM PST 24
Peak memory	432616 kb
Host	smart-582d8255-223f-47d2-b5f1-c3bff05c12b1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=45940003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all_with_rand_reset.45940003 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_kmac_xof.3646237773
Short name	T639
Test name
Test status
Simulation time	285733868 ps
CPU time	6 seconds
Started	Jan 10 12:52:25 PM PST 24
Finished	Jan 10 12:53:41 PM PST 24
Peak memory	220892 kb
Host	smart-b359f864-2b4d-4ac6-94ae-bc61b1143624
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646237773 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_kmac_xof.3646237773 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_224.1392263288
Short name	T172
Test name
Test status
Simulation time	132382231450 ps
CPU time	2098.51 seconds
Started	Jan 10 12:51:56 PM PST 24
Finished	Jan 10 01:28:08 PM PST 24
Peak memory	395108 kb
Host	smart-9dda4248-60ac-41ca-8153-b4d8de505684
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1392263288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.1392263288 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_256.2922668275
Short name	T692
Test name
Test status
Simulation time	374918768664 ps
CPU time	2314.73 seconds
Started	Jan 10 12:52:07 PM PST 24
Finished	Jan 10 01:32:02 PM PST 24
Peak memory	396992 kb
Host	smart-c4e8154c-68fd-4c94-a159-4e592f8feff2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2922668275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.2922668275 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_384.3054710516
Short name	T417
Test name
Test status
Simulation time	202006662670 ps
CPU time	1721.02 seconds
Started	Jan 10 12:51:37 PM PST 24
Finished	Jan 10 01:21:43 PM PST 24
Peak memory	347544 kb
Host	smart-05b906b0-69ef-44c6-b7f3-278df3acb9d4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3054710516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.3054710516 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_512.506001908
Short name	T515
Test name
Test status
Simulation time	41920287023 ps
CPU time	1035.04 seconds
Started	Jan 10 12:51:37 PM PST 24
Finished	Jan 10 01:10:07 PM PST 24
Peak memory	301896 kb
Host	smart-bc38f3c6-dffa-43ac-a1a6-8aceac488f19
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=506001908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.506001908 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_shake_128.3167810701
Short name	T848
Test name
Test status
Simulation time	68640813568 ps
CPU time	5097.99 seconds
Started	Jan 10 12:52:20 PM PST 24
Finished	Jan 10 02:18:40 PM PST 24
Peak memory	657300 kb
Host	smart-1f890f7f-590d-4df2-96d7-f48882705392
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3167810701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.3167810701 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_shake_256.2914753994
Short name	T924
Test name
Test status
Simulation time	153936527369 ps
CPU time	4955.1 seconds
Started	Jan 10 12:52:06 PM PST 24
Finished	Jan 10 02:15:54 PM PST 24
Peak memory	570248 kb
Host	smart-94f73699-f64b-4a9e-9b50-1eafaf54d6d7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2914753994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.2914753994 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/28.kmac_alert_test.2551980513
Short name	T570
Test name
Test status
Simulation time	31310787 ps
CPU time	0.84 seconds
Started	Jan 10 12:51:53 PM PST 24
Finished	Jan 10 12:53:12 PM PST 24
Peak memory	220208 kb
Host	smart-ab88f320-9135-4526-8494-08b31d9960a1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551980513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.2551980513 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_alert_test/latest

Test location	/workspace/coverage/default/28.kmac_app.309491064
Short name	T302
Test name
Test status
Simulation time	149698294142 ps
CPU time	273.39 seconds
Started	Jan 10 12:51:38 PM PST 24
Finished	Jan 10 12:57:35 PM PST 24
Peak memory	245040 kb
Host	smart-93ade064-6d30-4130-99cb-6935eab0f42e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=309491064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.309491064 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_app/latest

Test location	/workspace/coverage/default/28.kmac_burst_write.2577548498
Short name	T353
Test name
Test status
Simulation time	22843811867 ps
CPU time	854.76 seconds
Started	Jan 10 12:51:37 PM PST 24
Finished	Jan 10 01:07:06 PM PST 24
Peak memory	243904 kb
Host	smart-79c38ac7-61d2-4e51-a3b9-ed4af2dcadfb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2577548498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.2577548498 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_burst_write/latest

Test location	/workspace/coverage/default/28.kmac_entropy_refresh.405101597
Short name	T343
Test name
Test status
Simulation time	9865261440 ps
CPU time	17.25 seconds
Started	Jan 10 12:51:45 PM PST 24
Finished	Jan 10 12:53:25 PM PST 24
Peak memory	227512 kb
Host	smart-84ae62b0-dfe5-4bbd-9e4f-9691efac338d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=405101597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.405101597 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/28.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/28.kmac_key_error.2645643313
Short name	T981
Test name
Test status
Simulation time	634850179 ps
CPU time	1.67 seconds
Started	Jan 10 12:51:40 PM PST 24
Finished	Jan 10 12:52:54 PM PST 24
Peak memory	219148 kb
Host	smart-0d28a676-18b1-4441-aff2-0e4897f9ed25
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2645643313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.2645643313 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_key_error/latest

Test location	/workspace/coverage/default/28.kmac_lc_escalation.712535521
Short name	T816
Test name
Test status
Simulation time	69778655 ps
CPU time	1.57 seconds
Started	Jan 10 12:51:38 PM PST 24
Finished	Jan 10 12:52:56 PM PST 24
Peak memory	220372 kb
Host	smart-10187394-5674-4a13-8c4c-ac86326d71b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=712535521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.712535521 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/28.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/28.kmac_long_msg_and_output.4011433676
Short name	T375
Test name
Test status
Simulation time	17173161396 ps
CPU time	1807.19 seconds
Started	Jan 10 12:51:55 PM PST 24
Finished	Jan 10 01:23:21 PM PST 24
Peak memory	390160 kb
Host	smart-17194333-3248-4645-b100-92ad90e5c229
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011433676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a nd_output.4011433676 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/28.kmac_sideload.2069370052
Short name	T594
Test name
Test status
Simulation time	7148955664 ps
CPU time	359.3 seconds
Started	Jan 10 12:51:46 PM PST 24
Finished	Jan 10 12:59:01 PM PST 24
Peak memory	252080 kb
Host	smart-7319c733-9ee5-4b74-b6c1-dca2cf88dd93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2069370052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.2069370052 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_sideload/latest

Test location	/workspace/coverage/default/28.kmac_smoke.1946329669
Short name	T1028
Test name
Test status
Simulation time	3645189332 ps
CPU time	36.84 seconds
Started	Jan 10 12:52:15 PM PST 24
Finished	Jan 10 12:54:04 PM PST 24
Peak memory	227380 kb
Host	smart-e7dc0cc6-9362-4fda-a5ee-81e7ec3eb8da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1946329669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.1946329669 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_smoke/latest

Test location	/workspace/coverage/default/28.kmac_stress_all.2236591685
Short name	T569
Test name
Test status
Simulation time	5404116057 ps
CPU time	38.54 seconds
Started	Jan 10 12:51:47 PM PST 24
Finished	Jan 10 12:53:42 PM PST 24
Peak memory	233612 kb
Host	smart-e2a8d3a9-ba4f-4b8e-a8c6-e5f54a5bd4a8
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2236591685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.2236591685 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_stress_all/latest

Test location	/workspace/coverage/default/28.kmac_stress_all_with_rand_reset.1017144593
Short name	T589
Test name
Test status
Simulation time	22671971234 ps
CPU time	447.63 seconds
Started	Jan 10 12:51:43 PM PST 24
Finished	Jan 10 01:00:38 PM PST 24
Peak memory	273768 kb
Host	smart-a58527d6-5191-427b-9f24-9bd0353ce732
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1017144593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all_with_rand_reset.1017144593 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_kmac.3997568457
Short name	T693
Test name
Test status
Simulation time	96731092 ps
CPU time	5.32 seconds
Started	Jan 10 12:51:40 PM PST 24
Finished	Jan 10 12:53:09 PM PST 24
Peak memory	219148 kb
Host	smart-10c73ea1-4e86-404f-afcf-811574b3053c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997568457 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 28.kmac_test_vectors_kmac.3997568457 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_kmac_xof.1365167260
Short name	T474
Test name
Test status
Simulation time	674873203 ps
CPU time	6.35 seconds
Started	Jan 10 12:52:15 PM PST 24
Finished	Jan 10 12:53:37 PM PST 24
Peak memory	219560 kb
Host	smart-5b8ced51-69dd-4e2d-a8c0-711dfabdfed9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365167260 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_kmac_xof.1365167260 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_224.2512521353
Short name	T430
Test name
Test status
Simulation time	347820641951 ps
CPU time	2192.42 seconds
Started	Jan 10 12:51:50 PM PST 24
Finished	Jan 10 01:29:48 PM PST 24
Peak memory	395556 kb
Host	smart-4ef20802-e741-47d5-b8d1-d5a72f19fa1f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2512521353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.2512521353 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_256.465996059
Short name	T803
Test name
Test status
Simulation time	79742129530 ps
CPU time	2086.72 seconds
Started	Jan 10 12:51:56 PM PST 24
Finished	Jan 10 01:28:07 PM PST 24
Peak memory	376776 kb
Host	smart-be00acfe-ba66-454e-88af-6b4c1fa1768d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=465996059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.465996059 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_384.2608352627
Short name	T1068
Test name
Test status
Simulation time	78970465260 ps
CPU time	1650.18 seconds
Started	Jan 10 12:51:43 PM PST 24
Finished	Jan 10 01:20:37 PM PST 24
Peak memory	333604 kb
Host	smart-9ba68ac8-4578-4536-9948-2f55b7ee0fc8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2608352627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.2608352627 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_512.1886723437
Short name	T263
Test name
Test status
Simulation time	130369108867 ps
CPU time	1327.85 seconds
Started	Jan 10 12:51:44 PM PST 24
Finished	Jan 10 01:15:16 PM PST 24
Peak memory	299356 kb
Host	smart-10e4d262-8a1a-4a17-a41f-4f12ecbadfde
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1886723437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.1886723437 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_shake_128.2979254247
Short name	T159
Test name
Test status
Simulation time	368958245618 ps
CPU time	5626.02 seconds
Started	Jan 10 12:52:27 PM PST 24
Finished	Jan 10 02:27:24 PM PST 24
Peak memory	655908 kb
Host	smart-28701d59-7509-4d7c-b391-1a6672f621ce
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2979254247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.2979254247 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_shake_256.63938001
Short name	T602
Test name
Test status
Simulation time	651597388101 ps
CPU time	5325.83 seconds
Started	Jan 10 12:51:47 PM PST 24
Finished	Jan 10 02:21:57 PM PST 24
Peak memory	570288 kb
Host	smart-0afb965b-bed3-4e64-94f0-23f21be23f03
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=63938001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.63938001 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/29.kmac_alert_test.113961643
Short name	T351
Test name
Test status
Simulation time	38497425 ps
CPU time	0.79 seconds
Started	Jan 10 12:51:57 PM PST 24
Finished	Jan 10 12:53:14 PM PST 24
Peak memory	220328 kb
Host	smart-ae890bb9-f559-44fd-97de-6604bdbc7650
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113961643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.113961643 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_alert_test/latest

Test location	/workspace/coverage/default/29.kmac_app.966141607
Short name	T533
Test name
Test status
Simulation time	4553235913 ps
CPU time	136.87 seconds
Started	Jan 10 12:51:48 PM PST 24
Finished	Jan 10 12:55:18 PM PST 24
Peak memory	243944 kb
Host	smart-5bbf34d8-d6a6-42bc-84ce-2b44ea184e92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=966141607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.966141607 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_app/latest

Test location	/workspace/coverage/default/29.kmac_burst_write.2280180906
Short name	T358
Test name
Test status
Simulation time	25643846747 ps
CPU time	1202.86 seconds
Started	Jan 10 12:51:38 PM PST 24
Finished	Jan 10 01:13:05 PM PST 24
Peak memory	241500 kb
Host	smart-8f042f95-ed03-489a-900d-f66bb3d249df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2280180906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.2280180906 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_burst_write/latest

Test location	/workspace/coverage/default/29.kmac_entropy_refresh.1150054718
Short name	T82
Test name
Test status
Simulation time	2871956198 ps
CPU time	63.82 seconds
Started	Jan 10 12:51:47 PM PST 24
Finished	Jan 10 12:54:14 PM PST 24
Peak memory	240448 kb
Host	smart-ecd1c5fd-68a9-4b5e-aed5-ff5c6e988005
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1150054718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.1150054718 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/29.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/29.kmac_error.707901465
Short name	T292
Test name
Test status
Simulation time	5400221260 ps
CPU time	131.07 seconds
Started	Jan 10 12:51:50 PM PST 24
Finished	Jan 10 12:55:15 PM PST 24
Peak memory	254480 kb
Host	smart-fe598093-d56b-4b70-b9d0-3d50f84fb443
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=707901465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.707901465 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_error/latest

Test location	/workspace/coverage/default/29.kmac_key_error.556700918
Short name	T446
Test name
Test status
Simulation time	95598108 ps
CPU time	1.25 seconds
Started	Jan 10 12:51:52 PM PST 24
Finished	Jan 10 12:53:13 PM PST 24
Peak memory	219104 kb
Host	smart-aa2d8aa8-96df-48c0-97b3-bb072bd40430
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=556700918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.556700918 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_key_error/latest

Test location	/workspace/coverage/default/29.kmac_lc_escalation.1576658999
Short name	T879
Test name
Test status
Simulation time	50212294 ps
CPU time	1.41 seconds
Started	Jan 10 12:51:38 PM PST 24
Finished	Jan 10 12:52:53 PM PST 24
Peak memory	219112 kb
Host	smart-3be8107f-805b-464a-9aef-9447304744b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1576658999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.1576658999 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/29.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/29.kmac_long_msg_and_output.3333605600
Short name	T1074
Test name
Test status
Simulation time	24092537310 ps
CPU time	2247.44 seconds
Started	Jan 10 12:51:51 PM PST 24
Finished	Jan 10 01:30:42 PM PST 24
Peak memory	441664 kb
Host	smart-b7dbe29a-43b4-46dd-94ae-e1a3e09193f7
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333605600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a nd_output.3333605600 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/29.kmac_sideload.3610775824
Short name	T1083
Test name
Test status
Simulation time	11234670956 ps
CPU time	204.24 seconds
Started	Jan 10 12:51:41 PM PST 24
Finished	Jan 10 12:56:17 PM PST 24
Peak memory	244684 kb
Host	smart-b00e51d3-fb94-4544-8d1c-856d9998780e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3610775824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.3610775824 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_sideload/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_kmac.1935300550
Short name	T423
Test name
Test status
Simulation time	261205757 ps
CPU time	5.8 seconds
Started	Jan 10 12:51:55 PM PST 24
Finished	Jan 10 12:53:22 PM PST 24
Peak memory	219140 kb
Host	smart-f2006405-df34-4925-84cb-cfb3355d1d8c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935300550 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 29.kmac_test_vectors_kmac.1935300550 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_kmac_xof.4109180687
Short name	T329
Test name
Test status
Simulation time	105782378 ps
CPU time	5.22 seconds
Started	Jan 10 12:52:09 PM PST 24
Finished	Jan 10 12:53:41 PM PST 24
Peak memory	219288 kb
Host	smart-f65de71f-0b42-48b5-9456-4750dab0b231
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109180687 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_kmac_xof.4109180687 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_224.1773013684
Short name	T758
Test name
Test status
Simulation time	84900396437 ps
CPU time	2010.15 seconds
Started	Jan 10 12:51:41 PM PST 24
Finished	Jan 10 01:26:35 PM PST 24
Peak memory	398600 kb
Host	smart-64034026-8d3e-48ec-8cd3-6b037ce8d561
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1773013684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.1773013684 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_256.1744738866
Short name	T751
Test name
Test status
Simulation time	386648121093 ps
CPU time	2286.17 seconds
Started	Jan 10 12:52:20 PM PST 24
Finished	Jan 10 01:31:43 PM PST 24
Peak memory	393768 kb
Host	smart-615bf031-1a53-4df5-be4e-c088c3ebe4c1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1744738866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.1744738866 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_384.2836302643
Short name	T581
Test name
Test status
Simulation time	60146426784 ps
CPU time	1491.73 seconds
Started	Jan 10 12:51:55 PM PST 24
Finished	Jan 10 01:18:08 PM PST 24
Peak memory	343100 kb
Host	smart-7b38e447-dde8-4300-bcb9-b9084168445c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2836302643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.2836302643 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_512.1185507808
Short name	T932
Test name
Test status
Simulation time	877924638922 ps
CPU time	1504.63 seconds
Started	Jan 10 12:51:45 PM PST 24
Finished	Jan 10 01:18:04 PM PST 24
Peak memory	307048 kb
Host	smart-c9196816-807c-4bcc-b0c7-0fa8c88e286c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1185507808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.1185507808 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_shake_128.2528984366
Short name	T1069
Test name
Test status
Simulation time	732303079888 ps
CPU time	5623.28 seconds
Started	Jan 10 12:51:37 PM PST 24
Finished	Jan 10 02:26:35 PM PST 24
Peak memory	650596 kb
Host	smart-305b3f23-35bf-446d-b83c-27be5d2b6d7c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2528984366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.2528984366 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_shake_256.2453073249
Short name	T386
Test name
Test status
Simulation time	655259766439 ps
CPU time	4543.03 seconds
Started	Jan 10 12:51:56 PM PST 24
Finished	Jan 10 02:08:56 PM PST 24
Peak memory	568796 kb
Host	smart-8a5f38d9-0fba-47de-86fa-92424965c5b1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2453073249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.2453073249 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/3.kmac_alert_test.3639420850
Short name	T241
Test name
Test status
Simulation time	56841156 ps
CPU time	0.84 seconds
Started	Jan 10 12:51:36 PM PST 24
Finished	Jan 10 12:52:54 PM PST 24
Peak memory	218656 kb
Host	smart-c662b923-07b7-4bb4-a9e9-dd1fc2bc219f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639420850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.3639420850 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_alert_test/latest

Test location	/workspace/coverage/default/3.kmac_app.2757854694
Short name	T945
Test name
Test status
Simulation time	2001320669 ps
CPU time	101.94 seconds
Started	Jan 10 12:50:30 PM PST 24
Finished	Jan 10 12:53:44 PM PST 24
Peak memory	236008 kb
Host	smart-01cd19ea-7755-4c51-9c04-c23502b4a2b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2757854694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.2757854694 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_app/latest

Test location	/workspace/coverage/default/3.kmac_app_with_partial_data.2575618251
Short name	T407
Test name
Test status
Simulation time	53448761500 ps
CPU time	315.96 seconds
Started	Jan 10 12:51:44 PM PST 24
Finished	Jan 10 12:58:12 PM PST 24
Peak memory	250560 kb
Host	smart-ac61e0b8-413b-4801-a84b-897a02337d85
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2575618251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.2575618251 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/3.kmac_burst_write.2114082472
Short name	T470
Test name
Test status
Simulation time	30211824007 ps
CPU time	793.19 seconds
Started	Jan 10 12:50:16 PM PST 24
Finished	Jan 10 01:04:49 PM PST 24
Peak memory	235808 kb
Host	smart-bdb970a2-cfd6-4efb-b72a-b44e013e5ae2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2114082472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.2114082472 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_burst_write/latest

Test location	/workspace/coverage/default/3.kmac_edn_timeout_error.3839033064
Short name	T492
Test name
Test status
Simulation time	382592490 ps
CPU time	14.93 seconds
Started	Jan 10 12:50:15 PM PST 24
Finished	Jan 10 12:52:03 PM PST 24
Peak memory	232424 kb
Host	smart-d06ea8bb-0583-470d-8539-47c70fc916ef
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3839033064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.3839033064 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/3.kmac_entropy_mode_error.1740840140
Short name	T615
Test name
Test status
Simulation time	44069234 ps
CPU time	1.1 seconds
Started	Jan 10 12:50:15 PM PST 24
Finished	Jan 10 12:51:46 PM PST 24
Peak memory	219304 kb
Host	smart-5d0e6aa5-ed7d-4616-86a4-abb2a03db08a
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1740840140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.1740840140 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/3.kmac_entropy_ready_error.3202275389
Short name	T1062
Test name
Test status
Simulation time	2445028469 ps
CPU time	19.52 seconds
Started	Jan 10 12:50:15 PM PST 24
Finished	Jan 10 12:52:04 PM PST 24
Peak memory	219596 kb
Host	smart-f3814b84-3ea1-496a-ab2b-5338941c27fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3202275389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.3202275389 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/3.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/3.kmac_entropy_refresh.4059500027
Short name	T13
Test name
Test status
Simulation time	6109774755 ps
CPU time	151.01 seconds
Started	Jan 10 12:50:11 PM PST 24
Finished	Jan 10 12:54:18 PM PST 24
Peak memory	243868 kb
Host	smart-59364795-3c6c-48dd-aa44-af25ebbd4ccc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4059500027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.4059500027 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/3.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/3.kmac_error.1456566936
Short name	T547
Test name
Test status
Simulation time	10002324755 ps
CPU time	115.93 seconds
Started	Jan 10 12:51:55 PM PST 24
Finished	Jan 10 12:55:10 PM PST 24
Peak memory	255540 kb
Host	smart-2d43454a-7cd7-4eba-a37d-bb68e9c7b17c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1456566936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.1456566936 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_error/latest

Test location	/workspace/coverage/default/3.kmac_key_error.1358965753
Short name	T910
Test name
Test status
Simulation time	1688551529 ps
CPU time	3.2 seconds
Started	Jan 10 12:50:12 PM PST 24
Finished	Jan 10 12:51:59 PM PST 24
Peak memory	219148 kb
Host	smart-408444f1-529e-4499-9e3f-b0bd7a405e72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1358965753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.1358965753 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_key_error/latest

Test location	/workspace/coverage/default/3.kmac_lc_escalation.62573271
Short name	T813
Test name
Test status
Simulation time	11593284612 ps
CPU time	38.75 seconds
Started	Jan 10 12:51:38 PM PST 24
Finished	Jan 10 12:53:30 PM PST 24
Peak memory	238004 kb
Host	smart-f1b85273-ef21-4574-98c7-b487d1940085
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62573271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.62573271 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/3.kmac_long_msg_and_output.4155919088
Short name	T464
Test name
Test status
Simulation time	7934132656 ps
CPU time	503.49 seconds
Started	Jan 10 12:51:36 PM PST 24
Finished	Jan 10 01:01:16 PM PST 24
Peak memory	271316 kb
Host	smart-aa2fa29d-70f4-4483-ba2a-2add3be96dc9
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155919088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an d_output.4155919088 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/3.kmac_mubi.1312976034
Short name	T1016
Test name
Test status
Simulation time	8685860080 ps
CPU time	193.53 seconds
Started	Jan 10 12:50:56 PM PST 24
Finished	Jan 10 12:55:25 PM PST 24
Peak memory	244136 kb
Host	smart-dbe67120-c2c9-4280-9ead-e69c8e573153
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1312976034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.1312976034 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_mubi/latest

Test location	/workspace/coverage/default/3.kmac_sec_cm.1335986600
Short name	T7
Test name
Test status
Simulation time	6442737545 ps
CPU time	91.39 seconds
Started	Jan 10 12:50:11 PM PST 24
Finished	Jan 10 12:53:04 PM PST 24
Peak memory	292056 kb
Host	smart-6c2fdd74-2c29-4c53-ba41-c11e72e04c15
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335986600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.1335986600 +enable_maski ng=1 +sw_key_masked=0
Directory	/workspace/3.kmac_sec_cm/latest

Test location	/workspace/coverage/default/3.kmac_sideload.353840663
Short name	T657
Test name
Test status
Simulation time	68235632538 ps
CPU time	360.27 seconds
Started	Jan 10 12:50:18 PM PST 24
Finished	Jan 10 12:58:08 PM PST 24
Peak memory	252376 kb
Host	smart-9555a593-9061-43af-9965-e569cf0ed8c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=353840663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.353840663 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_sideload/latest

Test location	/workspace/coverage/default/3.kmac_smoke.218206526
Short name	T441
Test name
Test status
Simulation time	616845018 ps
CPU time	13.89 seconds
Started	Jan 10 12:50:44 PM PST 24
Finished	Jan 10 12:52:14 PM PST 24
Peak memory	227468 kb
Host	smart-fe888de1-17ec-4e17-a712-a0757cd2d605
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=218206526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.218206526 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_smoke/latest

Test location	/workspace/coverage/default/3.kmac_stress_all.3232446607
Short name	T33
Test name
Test status
Simulation time	70663705251 ps
CPU time	222.94 seconds
Started	Jan 10 12:51:36 PM PST 24
Finished	Jan 10 12:56:35 PM PST 24
Peak memory	272820 kb
Host	smart-bed4e45a-2c01-4bac-9c16-428e903a5a92
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3232446607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.3232446607 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_stress_all/latest

Test location	/workspace/coverage/default/3.kmac_stress_all_with_rand_reset.3819972683
Short name	T347
Test name
Test status
Simulation time	18419410941 ps
CPU time	1422.64 seconds
Started	Jan 10 12:50:10 PM PST 24
Finished	Jan 10 01:15:48 PM PST 24
Peak memory	369324 kb
Host	smart-d6f9b528-6de5-4e11-96ed-6e4479f8b8f5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3819972683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_with_rand_reset.3819972683 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_kmac.4265854500
Short name	T21
Test name
Test status
Simulation time	108344501 ps
CPU time	5.34 seconds
Started	Jan 10 12:50:28 PM PST 24
Finished	Jan 10 12:52:00 PM PST 24
Peak memory	219296 kb
Host	smart-c137762c-8389-41c1-8211-22f5a42acf14
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265854500 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 3.kmac_test_vectors_kmac.4265854500 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_kmac_xof.653653452
Short name	T1111
Test name
Test status
Simulation time	168687150 ps
CPU time	5.3 seconds
Started	Jan 10 12:50:12 PM PST 24
Finished	Jan 10 12:51:40 PM PST 24
Peak memory	219320 kb
Host	smart-6bf8cb3e-d49f-41fc-9ad6-bc2ba905aefb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653653452 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 3.kmac_test_vectors_kmac_xof.653653452 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_224.1304700769
Short name	T1067
Test name
Test status
Simulation time	21107799735 ps
CPU time	1838.83 seconds
Started	Jan 10 12:50:28 PM PST 24
Finished	Jan 10 01:22:36 PM PST 24
Peak memory	397612 kb
Host	smart-a090e6ac-804c-4fcc-9861-de568d8456cf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1304700769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.1304700769 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_256.3821785358
Short name	T869
Test name
Test status
Simulation time	88092435892 ps
CPU time	2186.63 seconds
Started	Jan 10 12:50:27 PM PST 24
Finished	Jan 10 01:28:21 PM PST 24
Peak memory	400860 kb
Host	smart-21a73d62-5783-462f-a6cd-386c43c0e1f6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3821785358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.3821785358 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_384.2167012295
Short name	T1091
Test name
Test status
Simulation time	95064619823 ps
CPU time	1659.42 seconds
Started	Jan 10 12:50:45 PM PST 24
Finished	Jan 10 01:19:36 PM PST 24
Peak memory	342180 kb
Host	smart-2ebfa64a-9317-466c-b631-366d2ddd94d1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2167012295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.2167012295 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_512.211491077
Short name	T1063
Test name
Test status
Simulation time	36984201078 ps
CPU time	1149.98 seconds
Started	Jan 10 12:50:12 PM PST 24
Finished	Jan 10 01:10:45 PM PST 24
Peak memory	306620 kb
Host	smart-d0d9fca6-2d02-47ec-b2c3-21021a1d04a0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=211491077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.211491077 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_shake_128.1291544620
Short name	T274
Test name
Test status
Simulation time	60179527177 ps
CPU time	5056.65 seconds
Started	Jan 10 12:50:44 PM PST 24
Finished	Jan 10 02:16:28 PM PST 24
Peak memory	663140 kb
Host	smart-ed0022b5-b348-48d3-bf2a-f573a7368ba6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1291544620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.1291544620 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_shake_256.1001159977
Short name	T614
Test name
Test status
Simulation time	518059072526 ps
CPU time	5469.24 seconds
Started	Jan 10 12:50:28 PM PST 24
Finished	Jan 10 02:23:02 PM PST 24
Peak memory	588752 kb
Host	smart-ff1214ad-43c6-4820-8d76-0d3bfd89ff5d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1001159977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.1001159977 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/30.kmac_alert_test.4210928594
Short name	T220
Test name
Test status
Simulation time	14596926 ps
CPU time	0.81 seconds
Started	Jan 10 12:52:07 PM PST 24
Finished	Jan 10 12:53:20 PM PST 24
Peak memory	220320 kb
Host	smart-6c88317e-7b82-418d-832f-cee1b49e7d69
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210928594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.4210928594 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_alert_test/latest

Test location	/workspace/coverage/default/30.kmac_app.1739390109
Short name	T35
Test name
Test status
Simulation time	5937708379 ps
CPU time	34.59 seconds
Started	Jan 10 12:52:01 PM PST 24
Finished	Jan 10 12:54:02 PM PST 24
Peak memory	227916 kb
Host	smart-0a618830-dabc-4962-8cf8-41626e2fb876
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1739390109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.1739390109 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_app/latest

Test location	/workspace/coverage/default/30.kmac_burst_write.2380933155
Short name	T178
Test name
Test status
Simulation time	178821679709 ps
CPU time	1130.56 seconds
Started	Jan 10 12:51:42 PM PST 24
Finished	Jan 10 01:12:03 PM PST 24
Peak memory	243852 kb
Host	smart-a0c6b865-89fc-4c35-b891-9dba61ef4bcf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2380933155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.2380933155 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_burst_write/latest

Test location	/workspace/coverage/default/30.kmac_entropy_refresh.343302105
Short name	T144
Test name
Test status
Simulation time	163663159052 ps
CPU time	434.05 seconds
Started	Jan 10 12:51:49 PM PST 24
Finished	Jan 10 01:00:20 PM PST 24
Peak memory	254460 kb
Host	smart-56364864-1439-4b82-9797-2d5ec291e8ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=343302105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.343302105 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/30.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/30.kmac_key_error.1633872191
Short name	T537
Test name
Test status
Simulation time	1207749890 ps
CPU time	5.16 seconds
Started	Jan 10 12:52:09 PM PST 24
Finished	Jan 10 12:53:41 PM PST 24
Peak memory	219260 kb
Host	smart-b888f7f8-0351-4f33-9969-c03c23534674
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1633872191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.1633872191 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_key_error/latest

Test location	/workspace/coverage/default/30.kmac_lc_escalation.2555762738
Short name	T349
Test name
Test status
Simulation time	34341449 ps
CPU time	1.35 seconds
Started	Jan 10 12:52:19 PM PST 24
Finished	Jan 10 12:53:31 PM PST 24
Peak memory	220316 kb
Host	smart-93d4cc54-7640-49ce-98a0-097a6eb5e122
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2555762738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.2555762738 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/30.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/30.kmac_long_msg_and_output.3126180816
Short name	T656
Test name
Test status
Simulation time	94320406867 ps
CPU time	1561.32 seconds
Started	Jan 10 12:51:57 PM PST 24
Finished	Jan 10 01:19:23 PM PST 24
Peak memory	346580 kb
Host	smart-4f5d0ba2-f6bd-4562-8c19-7e4fc29f65a3
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126180816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a nd_output.3126180816 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/30.kmac_sideload.4102744468
Short name	T331
Test name
Test status
Simulation time	8344184731 ps
CPU time	178.27 seconds
Started	Jan 10 12:51:41 PM PST 24
Finished	Jan 10 12:56:03 PM PST 24
Peak memory	243896 kb
Host	smart-e51fb610-4ec4-4637-aa55-6d9b788ff7fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4102744468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.4102744468 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_sideload/latest

Test location	/workspace/coverage/default/30.kmac_smoke.240009376
Short name	T400
Test name
Test status
Simulation time	769272564 ps
CPU time	16.95 seconds
Started	Jan 10 12:51:38 PM PST 24
Finished	Jan 10 12:53:16 PM PST 24
Peak memory	227412 kb
Host	smart-f0bd3a01-f379-42e5-90ae-bc30710cc730
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=240009376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.240009376 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_smoke/latest

Test location	/workspace/coverage/default/30.kmac_stress_all.1631157229
Short name	T48
Test name
Test status
Simulation time	41382872510 ps
CPU time	1051.31 seconds
Started	Jan 10 12:51:58 PM PST 24
Finished	Jan 10 01:11:02 PM PST 24
Peak memory	342580 kb
Host	smart-26d47e84-247d-44c4-89e8-01ce0af10114
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1631157229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.1631157229 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_stress_all/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_kmac.3154504122
Short name	T1032
Test name
Test status
Simulation time	488260667 ps
CPU time	5.13 seconds
Started	Jan 10 12:52:06 PM PST 24
Finished	Jan 10 12:53:30 PM PST 24
Peak memory	220648 kb
Host	smart-7e676cc8-a2fa-4e96-97d7-b26c6d9091e3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154504122 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 30.kmac_test_vectors_kmac.3154504122 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_kmac_xof.1129356160
Short name	T1014
Test name
Test status
Simulation time	371217149 ps
CPU time	6 seconds
Started	Jan 10 12:52:09 PM PST 24
Finished	Jan 10 12:53:42 PM PST 24
Peak memory	219352 kb
Host	smart-48247755-1d95-48f3-b256-69799998191a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129356160 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_kmac_xof.1129356160 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_224.983704144
Short name	T458
Test name
Test status
Simulation time	140181423051 ps
CPU time	2154.5 seconds
Started	Jan 10 12:51:44 PM PST 24
Finished	Jan 10 01:28:54 PM PST 24
Peak memory	392284 kb
Host	smart-f8139715-3902-4be0-98d4-19a0a445aec0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=983704144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.983704144 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_256.2276566047
Short name	T675
Test name
Test status
Simulation time	319867619771 ps
CPU time	2087.84 seconds
Started	Jan 10 12:52:11 PM PST 24
Finished	Jan 10 01:28:17 PM PST 24
Peak memory	390420 kb
Host	smart-abacfecc-ba3b-47c3-900b-7b1cbd292ac3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2276566047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.2276566047 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_384.2180302056
Short name	T110
Test name
Test status
Simulation time	323439149853 ps
CPU time	1826.45 seconds
Started	Jan 10 12:51:56 PM PST 24
Finished	Jan 10 01:23:36 PM PST 24
Peak memory	342820 kb
Host	smart-7c0e024e-6669-4a9d-847a-a3a8f90dd3c4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2180302056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.2180302056 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_512.1712403602
Short name	T628
Test name
Test status
Simulation time	33260322508 ps
CPU time	1189.58 seconds
Started	Jan 10 12:51:57 PM PST 24
Finished	Jan 10 01:13:03 PM PST 24
Peak memory	301644 kb
Host	smart-452911ec-86cb-478f-aa95-a84f094ac077
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1712403602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.1712403602 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_shake_128.2698551673
Short name	T222
Test name
Test status
Simulation time	356374506750 ps
CPU time	5515.79 seconds
Started	Jan 10 12:51:55 PM PST 24
Finished	Jan 10 02:25:21 PM PST 24
Peak memory	649024 kb
Host	smart-39a56710-83f9-487a-801b-d7f151203ef3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2698551673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.2698551673 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_shake_256.1591529644
Short name	T498
Test name
Test status
Simulation time	61729091963 ps
CPU time	4584.38 seconds
Started	Jan 10 12:51:41 PM PST 24
Finished	Jan 10 02:09:22 PM PST 24
Peak memory	588096 kb
Host	smart-53536148-e8b6-4acf-8cb9-eb57fae0e8e0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1591529644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.1591529644 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/31.kmac_alert_test.1401468912
Short name	T1015
Test name
Test status
Simulation time	31737918 ps
CPU time	0.86 seconds
Started	Jan 10 12:52:15 PM PST 24
Finished	Jan 10 12:53:31 PM PST 24
Peak memory	218904 kb
Host	smart-172f39ec-c6b1-437a-ac5f-71ef2c80ffc5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401468912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.1401468912 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_alert_test/latest

Test location	/workspace/coverage/default/31.kmac_app.2582266974
Short name	T961
Test name
Test status
Simulation time	5488170797 ps
CPU time	248.2 seconds
Started	Jan 10 12:51:58 PM PST 24
Finished	Jan 10 12:57:24 PM PST 24
Peak memory	249976 kb
Host	smart-12243a2a-7ea1-4c9b-a6d9-bd6dcd774316
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2582266974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.2582266974 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_app/latest

Test location	/workspace/coverage/default/31.kmac_burst_write.2979833250
Short name	T837
Test name
Test status
Simulation time	12918959616 ps
CPU time	430.76 seconds
Started	Jan 10 12:52:12 PM PST 24
Finished	Jan 10 01:00:38 PM PST 24
Peak memory	233704 kb
Host	smart-11a3020b-f4e1-47e5-b2af-712a18aaa063
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2979833250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.2979833250 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_burst_write/latest

Test location	/workspace/coverage/default/31.kmac_entropy_refresh.252737535
Short name	T381
Test name
Test status
Simulation time	38629356645 ps
CPU time	212.45 seconds
Started	Jan 10 12:52:01 PM PST 24
Finished	Jan 10 12:56:55 PM PST 24
Peak memory	243928 kb
Host	smart-893f4977-e8ea-4c59-bbb1-936313d8a9d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=252737535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.252737535 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/31.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/31.kmac_error.2408916280
Short name	T734
Test name
Test status
Simulation time	305118174 ps
CPU time	23.03 seconds
Started	Jan 10 12:51:59 PM PST 24
Finished	Jan 10 12:53:45 PM PST 24
Peak memory	242332 kb
Host	smart-8e2eb968-b7f2-4ab9-861d-a48b2d77fda7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2408916280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.2408916280 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_error/latest

Test location	/workspace/coverage/default/31.kmac_key_error.977895952
Short name	T293
Test name
Test status
Simulation time	383927163 ps
CPU time	3.01 seconds
Started	Jan 10 12:52:03 PM PST 24
Finished	Jan 10 12:53:21 PM PST 24
Peak memory	219220 kb
Host	smart-7a30c5f8-beaf-48b3-b298-8cfb1f85409e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=977895952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.977895952 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_key_error/latest

Test location	/workspace/coverage/default/31.kmac_lc_escalation.1370279616
Short name	T596
Test name
Test status
Simulation time	64352680 ps
CPU time	1.39 seconds
Started	Jan 10 12:52:07 PM PST 24
Finished	Jan 10 12:53:20 PM PST 24
Peak memory	220284 kb
Host	smart-e725366a-d30f-4f8b-b5c2-f300c4216e09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1370279616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.1370279616 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/31.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/31.kmac_long_msg_and_output.1434745870
Short name	T841
Test name
Test status
Simulation time	60723459499 ps
CPU time	1053.63 seconds
Started	Jan 10 12:52:01 PM PST 24
Finished	Jan 10 01:10:59 PM PST 24
Peak memory	314032 kb
Host	smart-e29c5b2f-dc6b-455a-8627-99662c932d9c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434745870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a nd_output.1434745870 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/31.kmac_sideload.805976938
Short name	T612
Test name
Test status
Simulation time	1305346856 ps
CPU time	91.29 seconds
Started	Jan 10 12:52:03 PM PST 24
Finished	Jan 10 12:54:57 PM PST 24
Peak memory	232768 kb
Host	smart-c51972cd-c04b-4532-8fe7-73eddab581ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=805976938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.805976938 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_sideload/latest

Test location	/workspace/coverage/default/31.kmac_smoke.1034258631
Short name	T658
Test name
Test status
Simulation time	4307768313 ps
CPU time	43.55 seconds
Started	Jan 10 12:52:01 PM PST 24
Finished	Jan 10 12:54:17 PM PST 24
Peak memory	225292 kb
Host	smart-044d5c36-11e6-4d24-a209-173c907fe150
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1034258631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.1034258631 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_smoke/latest

Test location	/workspace/coverage/default/31.kmac_stress_all.4185381483
Short name	T12
Test name
Test status
Simulation time	13001147791 ps
CPU time	252.36 seconds
Started	Jan 10 12:51:51 PM PST 24
Finished	Jan 10 12:57:17 PM PST 24
Peak memory	269552 kb
Host	smart-04d26539-5a0b-4d1e-a86e-728859263db4
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4185381483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.4185381483 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_stress_all/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_kmac.2077392633
Short name	T523
Test name
Test status
Simulation time	278638676 ps
CPU time	6.08 seconds
Started	Jan 10 12:52:06 PM PST 24
Finished	Jan 10 12:53:29 PM PST 24
Peak memory	220836 kb
Host	smart-8c0a136c-0909-4f50-9f2a-f557d3c5c0d0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077392633 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 31.kmac_test_vectors_kmac.2077392633 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_kmac_xof.169623954
Short name	T760
Test name
Test status
Simulation time	269454372 ps
CPU time	6.63 seconds
Started	Jan 10 12:52:33 PM PST 24
Finished	Jan 10 12:53:59 PM PST 24
Peak memory	220712 kb
Host	smart-317591d5-1f9f-4a8d-8aa6-123d90785f03
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169623954 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 31.kmac_test_vectors_kmac_xof.169623954 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_224.1040918309
Short name	T808
Test name
Test status
Simulation time	118028220404 ps
CPU time	1890.48 seconds
Started	Jan 10 12:52:01 PM PST 24
Finished	Jan 10 01:24:56 PM PST 24
Peak memory	391424 kb
Host	smart-37adc81d-fbed-444f-9c75-6efc76bf79f9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1040918309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.1040918309 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_256.2592260099
Short name	T1049
Test name
Test status
Simulation time	358923735394 ps
CPU time	2155.88 seconds
Started	Jan 10 12:52:04 PM PST 24
Finished	Jan 10 01:29:23 PM PST 24
Peak memory	375012 kb
Host	smart-656fcfe0-1ee2-4bef-9d30-da9c19f30613
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2592260099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.2592260099 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_384.2740783283
Short name	T809
Test name
Test status
Simulation time	69446127634 ps
CPU time	1685.7 seconds
Started	Jan 10 12:51:56 PM PST 24
Finished	Jan 10 01:21:26 PM PST 24
Peak memory	338428 kb
Host	smart-af1c63ed-b381-4917-8ffb-01171c8f7f6c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2740783283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.2740783283 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_512.1387653250
Short name	T256
Test name
Test status
Simulation time	34731376278 ps
CPU time	1261.51 seconds
Started	Jan 10 12:52:09 PM PST 24
Finished	Jan 10 01:14:23 PM PST 24
Peak memory	305944 kb
Host	smart-f7e2a213-9d35-4fdf-a5d3-099b2ebb890f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1387653250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.1387653250 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_shake_128.1506949122
Short name	T188
Test name
Test status
Simulation time	1162507772725 ps
CPU time	5584.74 seconds
Started	Jan 10 12:51:57 PM PST 24
Finished	Jan 10 02:26:15 PM PST 24
Peak memory	645636 kb
Host	smart-f7454714-f21d-4c4e-8dce-92fe0b40f68e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1506949122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.1506949122 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_shake_256.3049202809
Short name	T1089
Test name
Test status
Simulation time	153916469275 ps
CPU time	4913.97 seconds
Started	Jan 10 12:52:24 PM PST 24
Finished	Jan 10 02:15:30 PM PST 24
Peak memory	551124 kb
Host	smart-1c833df0-1b1c-45f1-8ea4-64ec2e0b0754
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3049202809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.3049202809 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/32.kmac_alert_test.822216827
Short name	T663
Test name
Test status
Simulation time	36233309 ps
CPU time	0.8 seconds
Started	Jan 10 12:51:57 PM PST 24
Finished	Jan 10 12:53:23 PM PST 24
Peak memory	220208 kb
Host	smart-c30b3210-873e-4f28-b58f-0c838d5f3996
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822216827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.822216827 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_alert_test/latest

Test location	/workspace/coverage/default/32.kmac_app.3837024493
Short name	T610
Test name
Test status
Simulation time	76191449775 ps
CPU time	240.96 seconds
Started	Jan 10 12:52:11 PM PST 24
Finished	Jan 10 12:57:33 PM PST 24
Peak memory	246476 kb
Host	smart-f997c823-a7e6-4a41-ae6a-206363b9ddea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3837024493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.3837024493 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_app/latest

Test location	/workspace/coverage/default/32.kmac_burst_write.1456465721
Short name	T864
Test name
Test status
Simulation time	7280478412 ps
CPU time	390.99 seconds
Started	Jan 10 12:51:54 PM PST 24
Finished	Jan 10 12:59:38 PM PST 24
Peak memory	234268 kb
Host	smart-7eb9a3a3-5e03-46b4-846a-b1fe124d2b8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1456465721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.1456465721 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_burst_write/latest

Test location	/workspace/coverage/default/32.kmac_entropy_refresh.1982866479
Short name	T49
Test name
Test status
Simulation time	55110635 ps
CPU time	2.93 seconds
Started	Jan 10 12:52:19 PM PST 24
Finished	Jan 10 12:53:32 PM PST 24
Peak memory	224716 kb
Host	smart-e98e0fe6-a444-4d12-a5d3-668e292a08d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1982866479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.1982866479 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/32.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/32.kmac_error.3964526020
Short name	T875
Test name
Test status
Simulation time	8809362166 ps
CPU time	97.57 seconds
Started	Jan 10 12:52:04 PM PST 24
Finished	Jan 10 12:54:54 PM PST 24
Peak memory	243676 kb
Host	smart-01d0dd88-ead3-4250-9aa7-d9df645ee4fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3964526020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.3964526020 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_error/latest

Test location	/workspace/coverage/default/32.kmac_lc_escalation.1518679983
Short name	T738
Test name
Test status
Simulation time	39945856 ps
CPU time	1.42 seconds
Started	Jan 10 12:52:03 PM PST 24
Finished	Jan 10 12:53:20 PM PST 24
Peak memory	220244 kb
Host	smart-e8259c01-bb7b-437a-93cf-94d9a9657ae1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1518679983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.1518679983 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/32.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/32.kmac_long_msg_and_output.839763163
Short name	T607
Test name
Test status
Simulation time	79175072616 ps
CPU time	2839.33 seconds
Started	Jan 10 12:52:00 PM PST 24
Finished	Jan 10 01:40:32 PM PST 24
Peak memory	451136 kb
Host	smart-68ec8f5f-c9bb-4e3f-92c4-9152502c20ab
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839763163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_an d_output.839763163 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/32.kmac_sideload.2373338819
Short name	T432
Test name
Test status
Simulation time	41811292333 ps
CPU time	274.24 seconds
Started	Jan 10 12:52:32 PM PST 24
Finished	Jan 10 12:58:15 PM PST 24
Peak memory	244944 kb
Host	smart-9e3d0f67-f7b3-46bc-8ae8-fb944368dc58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2373338819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.2373338819 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_sideload/latest

Test location	/workspace/coverage/default/32.kmac_smoke.2243551750
Short name	T6
Test name
Test status
Simulation time	1274501709 ps
CPU time	32.77 seconds
Started	Jan 10 12:51:56 PM PST 24
Finished	Jan 10 12:53:45 PM PST 24
Peak memory	227432 kb
Host	smart-8aba2c9c-0fca-4970-bee8-f7d5c5e23d2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2243551750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.2243551750 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_smoke/latest

Test location	/workspace/coverage/default/32.kmac_stress_all.1152477581
Short name	T963
Test name
Test status
Simulation time	601737170818 ps
CPU time	1350.63 seconds
Started	Jan 10 12:51:59 PM PST 24
Finished	Jan 10 01:15:46 PM PST 24
Peak memory	325868 kb
Host	smart-78b3ea92-d082-4bfe-a271-e6b784618c28
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1152477581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.1152477581 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_stress_all/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_kmac.924691663
Short name	T170
Test name
Test status
Simulation time	110806643 ps
CPU time	5.46 seconds
Started	Jan 10 12:51:54 PM PST 24
Finished	Jan 10 12:53:12 PM PST 24
Peak memory	219296 kb
Host	smart-ac686d49-4c6a-4015-b590-6ab0be7baba8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924691663 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 32.kmac_test_vectors_kmac.924691663 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_kmac_xof.3957915612
Short name	T1052
Test name
Test status
Simulation time	229876650 ps
CPU time	5.72 seconds
Started	Jan 10 12:52:06 PM PST 24
Finished	Jan 10 12:53:24 PM PST 24
Peak memory	220896 kb
Host	smart-ed725a81-52ab-452a-bf06-e3cf9dfbca4d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957915612 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_kmac_xof.3957915612 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_224.2239168155
Short name	T1073
Test name
Test status
Simulation time	97599019421 ps
CPU time	2206.08 seconds
Started	Jan 10 12:51:55 PM PST 24
Finished	Jan 10 01:29:55 PM PST 24
Peak memory	392816 kb
Host	smart-75f29334-13c9-4ebe-9fe5-2cb3f5c18153
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2239168155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.2239168155 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_256.3129885121
Short name	T740
Test name
Test status
Simulation time	131403539028 ps
CPU time	2102.63 seconds
Started	Jan 10 12:52:03 PM PST 24
Finished	Jan 10 01:28:28 PM PST 24
Peak memory	371764 kb
Host	smart-6484052c-3548-489f-8994-1a990aa42405
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3129885121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.3129885121 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_384.2056960429
Short name	T219
Test name
Test status
Simulation time	987715757355 ps
CPU time	2074.34 seconds
Started	Jan 10 12:51:59 PM PST 24
Finished	Jan 10 01:27:55 PM PST 24
Peak memory	337852 kb
Host	smart-d5b1d203-e8cf-41f7-89f7-b99f43d29e8d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2056960429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.2056960429 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_512.2306144100
Short name	T311
Test name
Test status
Simulation time	51353198791 ps
CPU time	1061.23 seconds
Started	Jan 10 12:51:47 PM PST 24
Finished	Jan 10 01:10:52 PM PST 24
Peak memory	304652 kb
Host	smart-eabd7038-282b-40f4-ae6d-9a55e6e92392
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2306144100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.2306144100 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_shake_128.2735228060
Short name	T1114
Test name
Test status
Simulation time	727172748182 ps
CPU time	5822.86 seconds
Started	Jan 10 12:52:03 PM PST 24
Finished	Jan 10 02:30:22 PM PST 24
Peak memory	645404 kb
Host	smart-b305b81e-fc75-4998-98e2-c137d542ef09
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2735228060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.2735228060 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_shake_256.2250976802
Short name	T804
Test name
Test status
Simulation time	57194551287 ps
CPU time	4401.75 seconds
Started	Jan 10 12:52:00 PM PST 24
Finished	Jan 10 02:06:38 PM PST 24
Peak memory	564796 kb
Host	smart-6adf2f05-c050-4f27-9ef5-e086f616bc08
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2250976802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.2250976802 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/33.kmac_alert_test.105288386
Short name	T545
Test name
Test status
Simulation time	34823506 ps
CPU time	0.85 seconds
Started	Jan 10 12:51:59 PM PST 24
Finished	Jan 10 12:53:21 PM PST 24
Peak memory	220312 kb
Host	smart-d789d8e0-ca49-4f65-b053-c198714b7d25
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105288386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.105288386 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_alert_test/latest

Test location	/workspace/coverage/default/33.kmac_app.3886177973
Short name	T145
Test name
Test status
Simulation time	62764241301 ps
CPU time	362.71 seconds
Started	Jan 10 12:52:16 PM PST 24
Finished	Jan 10 12:59:51 PM PST 24
Peak memory	250792 kb
Host	smart-7790cefa-7aac-4077-92f3-cf5681e895f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3886177973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.3886177973 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_app/latest

Test location	/workspace/coverage/default/33.kmac_burst_write.2976815493
Short name	T952
Test name
Test status
Simulation time	112836353211 ps
CPU time	1098.85 seconds
Started	Jan 10 12:52:09 PM PST 24
Finished	Jan 10 01:11:50 PM PST 24
Peak memory	243916 kb
Host	smart-86c7495e-fc37-4ec4-8a2f-cfb484072436
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2976815493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.2976815493 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_burst_write/latest

Test location	/workspace/coverage/default/33.kmac_entropy_refresh.2856045137
Short name	T788
Test name
Test status
Simulation time	35056922745 ps
CPU time	374.86 seconds
Started	Jan 10 12:52:09 PM PST 24
Finished	Jan 10 12:59:51 PM PST 24
Peak memory	252364 kb
Host	smart-4a829750-f52c-4862-afd1-ef681860b8ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2856045137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.2856045137 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/33.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/33.kmac_error.1463617872
Short name	T74
Test name
Test status
Simulation time	13827126755 ps
CPU time	334.54 seconds
Started	Jan 10 12:52:13 PM PST 24
Finished	Jan 10 12:59:02 PM PST 24
Peak memory	259508 kb
Host	smart-8c15f277-a06e-42cb-b2e6-53a3b876cba0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1463617872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.1463617872 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_error/latest

Test location	/workspace/coverage/default/33.kmac_key_error.1806181442
Short name	T643
Test name
Test status
Simulation time	8173944704 ps
CPU time	7.81 seconds
Started	Jan 10 12:51:57 PM PST 24
Finished	Jan 10 12:53:21 PM PST 24
Peak memory	219456 kb
Host	smart-814a77c2-22c2-408f-8919-e6e51ab204dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1806181442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.1806181442 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_key_error/latest

Test location	/workspace/coverage/default/33.kmac_lc_escalation.1540213130
Short name	T637
Test name
Test status
Simulation time	60276030 ps
CPU time	1.27 seconds
Started	Jan 10 12:52:11 PM PST 24
Finished	Jan 10 12:53:33 PM PST 24
Peak memory	219104 kb
Host	smart-6155c329-e82e-4fe6-8c9a-71b97f2c4752
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1540213130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.1540213130 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/33.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/33.kmac_long_msg_and_output.668564836
Short name	T527
Test name
Test status
Simulation time	392430172198 ps
CPU time	2162.71 seconds
Started	Jan 10 12:52:02 PM PST 24
Finished	Jan 10 01:29:21 PM PST 24
Peak memory	374576 kb
Host	smart-77f86d8f-8d9b-42e2-90fd-e63428f767db
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668564836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_an d_output.668564836 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/33.kmac_sideload.3320690421
Short name	T672
Test name
Test status
Simulation time	14052065468 ps
CPU time	160.57 seconds
Started	Jan 10 12:52:29 PM PST 24
Finished	Jan 10 12:56:27 PM PST 24
Peak memory	244028 kb
Host	smart-9fa21637-a6d7-4de2-a52d-7854f26e7cbb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3320690421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.3320690421 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_sideload/latest

Test location	/workspace/coverage/default/33.kmac_smoke.3065411
Short name	T845
Test name
Test status
Simulation time	365270482 ps
CPU time	7.16 seconds
Started	Jan 10 12:52:00 PM PST 24
Finished	Jan 10 12:53:29 PM PST 24
Peak memory	224860 kb
Host	smart-7c7df795-5062-4ae5-add1-3cb077031093
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3065411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.3065411 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_smoke/latest

Test location	/workspace/coverage/default/33.kmac_stress_all.2917210365
Short name	T557
Test name
Test status
Simulation time	7332765502 ps
CPU time	473.95 seconds
Started	Jan 10 12:52:01 PM PST 24
Finished	Jan 10 01:01:27 PM PST 24
Peak memory	306280 kb
Host	smart-cf98b8b9-c263-4f89-b5d3-1ba4d7b9b8b7
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2917210365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.2917210365 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_stress_all/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_kmac.252253793
Short name	T404
Test name
Test status
Simulation time	281216106 ps
CPU time	6.32 seconds
Started	Jan 10 12:52:08 PM PST 24
Finished	Jan 10 12:53:32 PM PST 24
Peak memory	220800 kb
Host	smart-118f6e2a-fb10-4fc2-981d-0e79dd08414b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252253793 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 33.kmac_test_vectors_kmac.252253793 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_kmac_xof.2196690317
Short name	T748
Test name
Test status
Simulation time	164571598 ps
CPU time	5.63 seconds
Started	Jan 10 12:52:03 PM PST 24
Finished	Jan 10 12:53:31 PM PST 24
Peak memory	219300 kb
Host	smart-fbece639-4bc8-4e92-b44c-494d793d4e90
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196690317 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_kmac_xof.2196690317 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_224.794765001
Short name	T653
Test name
Test status
Simulation time	134120610381 ps
CPU time	2169.18 seconds
Started	Jan 10 12:52:29 PM PST 24
Finished	Jan 10 01:29:48 PM PST 24
Peak memory	400252 kb
Host	smart-5b2ddbdb-c75d-4be9-848a-c8f8e97c2793
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=794765001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.794765001 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_256.2132520533
Short name	T824
Test name
Test status
Simulation time	183818828644 ps
CPU time	2307.63 seconds
Started	Jan 10 12:51:50 PM PST 24
Finished	Jan 10 01:31:41 PM PST 24
Peak memory	381228 kb
Host	smart-790c22f8-7b88-41c4-b77c-20ef40159150
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2132520533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.2132520533 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_384.567874702
Short name	T431
Test name
Test status
Simulation time	50821036897 ps
CPU time	1512.3 seconds
Started	Jan 10 12:51:59 PM PST 24
Finished	Jan 10 01:18:32 PM PST 24
Peak memory	330172 kb
Host	smart-7399b24f-5387-48ee-9d0a-cf2de7f99807
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=567874702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.567874702 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_512.1542720227
Short name	T290
Test name
Test status
Simulation time	309813647062 ps
CPU time	1253.28 seconds
Started	Jan 10 12:52:14 PM PST 24
Finished	Jan 10 01:14:20 PM PST 24
Peak memory	307840 kb
Host	smart-1affa0d1-7ce8-4282-83d1-9d86277fd54b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1542720227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.1542720227 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_shake_128.1565528670
Short name	T412
Test name
Test status
Simulation time	61611358276 ps
CPU time	4725.3 seconds
Started	Jan 10 12:52:05 PM PST 24
Finished	Jan 10 02:12:09 PM PST 24
Peak memory	661200 kb
Host	smart-f289bdf5-9bca-41de-9a2f-5a9bfd3a626b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1565528670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.1565528670 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_shake_256.26951410
Short name	T206
Test name
Test status
Simulation time	689586387753 ps
CPU time	4769.24 seconds
Started	Jan 10 12:52:01 PM PST 24
Finished	Jan 10 02:12:52 PM PST 24
Peak memory	588552 kb
Host	smart-28b815e8-75b5-48a9-8e66-c002fc6f0241
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=26951410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.26951410 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/34.kmac_alert_test.4238969270
Short name	T676
Test name
Test status
Simulation time	44125242 ps
CPU time	0.81 seconds
Started	Jan 10 12:52:11 PM PST 24
Finished	Jan 10 12:53:25 PM PST 24
Peak memory	219016 kb
Host	smart-b0331919-ee84-4d62-88b4-1e7e99242bfc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238969270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.4238969270 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_alert_test/latest

Test location	/workspace/coverage/default/34.kmac_app.3014469704
Short name	T858
Test name
Test status
Simulation time	9159264867 ps
CPU time	340.64 seconds
Started	Jan 10 12:52:13 PM PST 24
Finished	Jan 10 12:59:08 PM PST 24
Peak memory	252144 kb
Host	smart-8eb1b947-06c3-4495-ae61-6740b1d708d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3014469704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.3014469704 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_app/latest

Test location	/workspace/coverage/default/34.kmac_burst_write.1503340981
Short name	T623
Test name
Test status
Simulation time	51353202026 ps
CPU time	1314.25 seconds
Started	Jan 10 12:52:00 PM PST 24
Finished	Jan 10 01:15:17 PM PST 24
Peak memory	243984 kb
Host	smart-d7af8305-af8c-434c-959b-161b23540fc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1503340981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.1503340981 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_burst_write/latest

Test location	/workspace/coverage/default/34.kmac_entropy_refresh.1606484720
Short name	T882
Test name
Test status
Simulation time	5979757651 ps
CPU time	249.35 seconds
Started	Jan 10 12:52:16 PM PST 24
Finished	Jan 10 12:57:40 PM PST 24
Peak memory	246860 kb
Host	smart-0da8660a-a2a3-4b63-b3ff-240c89dde6a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1606484720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.1606484720 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/34.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/34.kmac_error.761462583
Short name	T669
Test name
Test status
Simulation time	9306699231 ps
CPU time	230.96 seconds
Started	Jan 10 12:52:11 PM PST 24
Finished	Jan 10 12:57:17 PM PST 24
Peak memory	254904 kb
Host	smart-043e3253-43d2-439f-8949-2d0e49c80127
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=761462583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.761462583 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_error/latest

Test location	/workspace/coverage/default/34.kmac_key_error.3368875147
Short name	T468
Test name
Test status
Simulation time	625645063 ps
CPU time	4.07 seconds
Started	Jan 10 12:52:14 PM PST 24
Finished	Jan 10 12:53:30 PM PST 24
Peak memory	219100 kb
Host	smart-d347dfaf-8a8a-4097-9c53-aac80ca0dc1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3368875147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.3368875147 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_key_error/latest

Test location	/workspace/coverage/default/34.kmac_lc_escalation.3921751829
Short name	T920
Test name
Test status
Simulation time	42098408 ps
CPU time	1.43 seconds
Started	Jan 10 12:52:01 PM PST 24
Finished	Jan 10 12:53:26 PM PST 24
Peak memory	220384 kb
Host	smart-dd0a8e9a-ae39-49c0-bd18-407d77ac399c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3921751829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.3921751829 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/34.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/34.kmac_long_msg_and_output.2872113321
Short name	T168
Test name
Test status
Simulation time	70578307168 ps
CPU time	353.74 seconds
Started	Jan 10 12:51:57 PM PST 24
Finished	Jan 10 12:59:13 PM PST 24
Peak memory	253328 kb
Host	smart-e213dd7f-1ece-4e0c-bb4b-d4d886235aa8
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872113321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a nd_output.2872113321 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/34.kmac_sideload.241817098
Short name	T650
Test name
Test status
Simulation time	114334582428 ps
CPU time	485.11 seconds
Started	Jan 10 12:52:15 PM PST 24
Finished	Jan 10 01:01:32 PM PST 24
Peak memory	258968 kb
Host	smart-ccb02987-cd22-4244-a4ce-62d6aec061ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=241817098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.241817098 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_sideload/latest

Test location	/workspace/coverage/default/34.kmac_smoke.4155524553
Short name	T867
Test name
Test status
Simulation time	7174136183 ps
CPU time	44.38 seconds
Started	Jan 10 12:52:09 PM PST 24
Finished	Jan 10 12:54:10 PM PST 24
Peak memory	227476 kb
Host	smart-6eec0557-af41-48cd-a7c3-d2e890ff4023
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4155524553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.4155524553 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_smoke/latest

Test location	/workspace/coverage/default/34.kmac_stress_all_with_rand_reset.3435974363
Short name	T763
Test name
Test status
Simulation time	173291933880 ps
CPU time	1151.05 seconds
Started	Jan 10 12:52:08 PM PST 24
Finished	Jan 10 01:12:37 PM PST 24
Peak memory	268892 kb
Host	smart-feda3b8d-5974-4729-89a5-e6da6e154197
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3435974363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all_with_rand_reset.3435974363 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_kmac.1667532709
Short name	T1002
Test name
Test status
Simulation time	1346814443 ps
CPU time	6.34 seconds
Started	Jan 10 12:52:06 PM PST 24
Finished	Jan 10 12:53:25 PM PST 24
Peak memory	220776 kb
Host	smart-b35df1e8-2999-48e5-b378-27636efed8d2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667532709 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 34.kmac_test_vectors_kmac.1667532709 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_kmac_xof.2633967146
Short name	T445
Test name
Test status
Simulation time	376065439 ps
CPU time	5.38 seconds
Started	Jan 10 12:52:09 PM PST 24
Finished	Jan 10 12:53:41 PM PST 24
Peak memory	220632 kb
Host	smart-b751357f-a989-4d21-940d-9813d6c6669e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633967146 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_kmac_xof.2633967146 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_224.2195909605
Short name	T413
Test name
Test status
Simulation time	613370012235 ps
CPU time	2462.91 seconds
Started	Jan 10 12:51:56 PM PST 24
Finished	Jan 10 01:34:22 PM PST 24
Peak memory	403184 kb
Host	smart-647a67cc-52e6-4545-8c35-129402b84294
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2195909605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.2195909605 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_256.1579363358
Short name	T434
Test name
Test status
Simulation time	37465267443 ps
CPU time	1861.11 seconds
Started	Jan 10 12:52:14 PM PST 24
Finished	Jan 10 01:24:31 PM PST 24
Peak memory	396640 kb
Host	smart-4b86531d-7be6-46c2-98c9-c285eaf416bc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1579363358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.1579363358 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_384.1514336899
Short name	T461
Test name
Test status
Simulation time	116748890329 ps
CPU time	1594.43 seconds
Started	Jan 10 12:52:13 PM PST 24
Finished	Jan 10 01:20:00 PM PST 24
Peak memory	350880 kb
Host	smart-d8b09bc7-c167-42ba-b8ec-9b6b9b428e42
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1514336899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.1514336899 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_512.2264849738
Short name	T229
Test name
Test status
Simulation time	21681065663 ps
CPU time	1100.47 seconds
Started	Jan 10 12:52:16 PM PST 24
Finished	Jan 10 01:11:51 PM PST 24
Peak memory	300020 kb
Host	smart-ade196ae-1d10-4ce8-ba5e-fc92defd86a8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2264849738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.2264849738 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_shake_128.63710428
Short name	T442
Test name
Test status
Simulation time	242554403793 ps
CPU time	5485.18 seconds
Started	Jan 10 12:52:05 PM PST 24
Finished	Jan 10 02:24:44 PM PST 24
Peak memory	667324 kb
Host	smart-3ae70bb6-ad1f-41de-9dac-fcb3d6e2c18f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=63710428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.63710428 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_shake_256.883149022
Short name	T846
Test name
Test status
Simulation time	624004941105 ps
CPU time	5043.35 seconds
Started	Jan 10 12:52:03 PM PST 24
Finished	Jan 10 02:17:40 PM PST 24
Peak memory	572604 kb
Host	smart-3d6bf3be-6158-411a-ba41-693766304290
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=883149022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.883149022 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/35.kmac_alert_test.523761869
Short name	T742
Test name
Test status
Simulation time	46691916 ps
CPU time	0.83 seconds
Started	Jan 10 12:52:12 PM PST 24
Finished	Jan 10 12:53:28 PM PST 24
Peak memory	218952 kb
Host	smart-362327b7-22b5-4374-8781-d89e8bbd166e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523761869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.523761869 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_alert_test/latest

Test location	/workspace/coverage/default/35.kmac_app.1607205473
Short name	T866
Test name
Test status
Simulation time	5572473521 ps
CPU time	122.41 seconds
Started	Jan 10 12:52:03 PM PST 24
Finished	Jan 10 12:55:23 PM PST 24
Peak memory	237664 kb
Host	smart-abb9cfdc-7982-42b0-bd0a-1d10efcc2d47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1607205473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.1607205473 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_app/latest

Test location	/workspace/coverage/default/35.kmac_burst_write.3891340040
Short name	T438
Test name
Test status
Simulation time	28220955312 ps
CPU time	655.63 seconds
Started	Jan 10 12:52:13 PM PST 24
Finished	Jan 10 01:04:40 PM PST 24
Peak memory	237660 kb
Host	smart-2789ebd9-2a63-41b6-bfc3-f4519562adda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3891340040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.3891340040 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_burst_write/latest

Test location	/workspace/coverage/default/35.kmac_entropy_refresh.2540998086
Short name	T359
Test name
Test status
Simulation time	31400410517 ps
CPU time	316.55 seconds
Started	Jan 10 12:52:13 PM PST 24
Finished	Jan 10 12:58:45 PM PST 24
Peak memory	253412 kb
Host	smart-77e4b7f0-b777-49ca-a64c-072a57010776
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2540998086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.2540998086 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/35.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/35.kmac_error.1853445978
Short name	T394
Test name
Test status
Simulation time	816857040 ps
CPU time	62.66 seconds
Started	Jan 10 12:52:26 PM PST 24
Finished	Jan 10 12:54:49 PM PST 24
Peak memory	240572 kb
Host	smart-0b680bf9-beb5-4a5b-ba44-2d2aeb781956
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1853445978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.1853445978 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_error/latest

Test location	/workspace/coverage/default/35.kmac_key_error.1175277164
Short name	T1045
Test name
Test status
Simulation time	805708918 ps
CPU time	4.58 seconds
Started	Jan 10 12:52:04 PM PST 24
Finished	Jan 10 12:53:28 PM PST 24
Peak memory	219176 kb
Host	smart-8728fafa-c83a-4a83-a894-73bc0651ce77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1175277164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.1175277164 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_key_error/latest

Test location	/workspace/coverage/default/35.kmac_lc_escalation.2911888892
Short name	T838
Test name
Test status
Simulation time	125302678 ps
CPU time	1.28 seconds
Started	Jan 10 12:52:14 PM PST 24
Finished	Jan 10 12:53:36 PM PST 24
Peak memory	220192 kb
Host	smart-29b6b08c-37de-4346-ba0f-51afcf72f3d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2911888892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.2911888892 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/35.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/35.kmac_long_msg_and_output.385604396
Short name	T1107
Test name
Test status
Simulation time	342002763425 ps
CPU time	2427 seconds
Started	Jan 10 12:52:03 PM PST 24
Finished	Jan 10 01:33:45 PM PST 24
Peak memory	423192 kb
Host	smart-e38d4c19-b784-4df5-b21b-2fb5ecd63817
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385604396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_an d_output.385604396 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/35.kmac_sideload.1264435018
Short name	T210
Test name
Test status
Simulation time	13049596748 ps
CPU time	336.99 seconds
Started	Jan 10 12:52:16 PM PST 24
Finished	Jan 10 12:59:12 PM PST 24
Peak memory	248080 kb
Host	smart-a79c65aa-d56b-42b8-a3a8-79d71d3c84c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1264435018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.1264435018 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_sideload/latest

Test location	/workspace/coverage/default/35.kmac_smoke.1968764987
Short name	T849
Test name
Test status
Simulation time	1076516047 ps
CPU time	11.05 seconds
Started	Jan 10 12:52:10 PM PST 24
Finished	Jan 10 12:53:33 PM PST 24
Peak memory	227416 kb
Host	smart-de3d86d0-4a09-4afe-85b6-f012e73bd950
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1968764987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.1968764987 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_smoke/latest

Test location	/workspace/coverage/default/35.kmac_stress_all.4241867461
Short name	T1040
Test name
Test status
Simulation time	10000007863 ps
CPU time	276.8 seconds
Started	Jan 10 12:52:11 PM PST 24
Finished	Jan 10 12:58:05 PM PST 24
Peak memory	284988 kb
Host	smart-0a5f8800-619f-4d72-95fa-f09b8bfa70ae
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4241867461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.4241867461 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_stress_all/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_kmac.1154085928
Short name	T576
Test name
Test status
Simulation time	213713743 ps
CPU time	5.97 seconds
Started	Jan 10 12:52:09 PM PST 24
Finished	Jan 10 12:53:31 PM PST 24
Peak memory	220504 kb
Host	smart-4caacbe9-1336-4fd8-84f4-5a883e07bfd6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154085928 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 35.kmac_test_vectors_kmac.1154085928 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_kmac_xof.849005152
Short name	T851
Test name
Test status
Simulation time	311797592 ps
CPU time	6.2 seconds
Started	Jan 10 12:52:13 PM PST 24
Finished	Jan 10 12:53:31 PM PST 24
Peak memory	220684 kb
Host	smart-98a9e06b-4ef0-4f84-bb98-be4024a2e1e4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849005152 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 35.kmac_test_vectors_kmac_xof.849005152 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_224.3081835584
Short name	T317
Test name
Test status
Simulation time	76335280782 ps
CPU time	2178.61 seconds
Started	Jan 10 12:52:17 PM PST 24
Finished	Jan 10 01:29:47 PM PST 24
Peak memory	403580 kb
Host	smart-3b121742-7bf1-48ca-babe-6e0d38f9a946
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3081835584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.3081835584 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_256.2190342123
Short name	T215
Test name
Test status
Simulation time	22987722396 ps
CPU time	1845.9 seconds
Started	Jan 10 12:52:09 PM PST 24
Finished	Jan 10 01:24:22 PM PST 24
Peak memory	382464 kb
Host	smart-f433e289-47f4-427a-81a3-1485f46a15d7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2190342123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.2190342123 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_384.1870988839
Short name	T176
Test name
Test status
Simulation time	42736939913 ps
CPU time	1397.13 seconds
Started	Jan 10 12:52:12 PM PST 24
Finished	Jan 10 01:16:41 PM PST 24
Peak memory	343664 kb
Host	smart-dc8b2652-81dd-4ea7-b476-0f023895bd7e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1870988839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.1870988839 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_512.1669900073
Short name	T484
Test name
Test status
Simulation time	998280320680 ps
CPU time	1304.66 seconds
Started	Jan 10 12:52:01 PM PST 24
Finished	Jan 10 01:15:08 PM PST 24
Peak memory	305324 kb
Host	smart-55cda760-32d1-484c-917a-806660f77e85
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1669900073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.1669900073 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_shake_128.1075746950
Short name	T243
Test name
Test status
Simulation time	740174237787 ps
CPU time	5717.42 seconds
Started	Jan 10 12:52:09 PM PST 24
Finished	Jan 10 02:28:40 PM PST 24
Peak memory	660552 kb
Host	smart-162d954c-4c8f-452c-922f-455baae741a9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1075746950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.1075746950 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_shake_256.3648300684
Short name	T973
Test name
Test status
Simulation time	56219973321 ps
CPU time	4403.31 seconds
Started	Jan 10 12:52:07 PM PST 24
Finished	Jan 10 02:06:51 PM PST 24
Peak memory	573968 kb
Host	smart-f9485c72-eeab-4469-9620-690b976e9690
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3648300684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.3648300684 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/36.kmac_alert_test.647432207
Short name	T223
Test name
Test status
Simulation time	16908870 ps
CPU time	0.78 seconds
Started	Jan 10 12:52:14 PM PST 24
Finished	Jan 10 12:53:27 PM PST 24
Peak memory	219168 kb
Host	smart-d937c11d-70aa-490c-a41f-1a1763b0d0a7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647432207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.647432207 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_alert_test/latest

Test location	/workspace/coverage/default/36.kmac_app.3069218177
Short name	T495
Test name
Test status
Simulation time	10529169449 ps
CPU time	276.52 seconds
Started	Jan 10 12:52:16 PM PST 24
Finished	Jan 10 12:58:06 PM PST 24
Peak memory	248792 kb
Host	smart-74902ec7-0c83-4262-b8f3-b2c0de8abe28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3069218177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.3069218177 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_app/latest

Test location	/workspace/coverage/default/36.kmac_burst_write.3469089395
Short name	T186
Test name
Test status
Simulation time	4933947710 ps
CPU time	496.35 seconds
Started	Jan 10 12:52:14 PM PST 24
Finished	Jan 10 01:01:51 PM PST 24
Peak memory	242188 kb
Host	smart-21d9a91f-50e4-4991-b497-1bebd16789a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3469089395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.3469089395 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_burst_write/latest

Test location	/workspace/coverage/default/36.kmac_entropy_refresh.1814971797
Short name	T450
Test name
Test status
Simulation time	13019301148 ps
CPU time	126.31 seconds
Started	Jan 10 12:52:14 PM PST 24
Finished	Jan 10 12:55:33 PM PST 24
Peak memory	237680 kb
Host	smart-eb49b7a5-00e8-4266-b4fc-3931f3a52b4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1814971797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.1814971797 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/36.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/36.kmac_error.1936990352
Short name	T732
Test name
Test status
Simulation time	2660872907 ps
CPU time	214.76 seconds
Started	Jan 10 12:52:14 PM PST 24
Finished	Jan 10 12:57:10 PM PST 24
Peak memory	259912 kb
Host	smart-9505d216-75dc-4a10-a386-65d5f5630097
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1936990352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.1936990352 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_error/latest

Test location	/workspace/coverage/default/36.kmac_key_error.3351630359
Short name	T355
Test name
Test status
Simulation time	4328589807 ps
CPU time	6.99 seconds
Started	Jan 10 12:52:25 PM PST 24
Finished	Jan 10 12:53:46 PM PST 24
Peak memory	218900 kb
Host	smart-e36aad9c-c737-429c-99b5-b7b95491d0fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3351630359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.3351630359 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_key_error/latest

Test location	/workspace/coverage/default/36.kmac_lc_escalation.488244939
Short name	T319
Test name
Test status
Simulation time	350709457 ps
CPU time	8.75 seconds
Started	Jan 10 12:52:03 PM PST 24
Finished	Jan 10 12:53:44 PM PST 24
Peak memory	235540 kb
Host	smart-38608405-8800-47f8-9999-dcc19ba0d805
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=488244939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.488244939 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/36.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/36.kmac_long_msg_and_output.930624437
Short name	T339
Test name
Test status
Simulation time	34206093082 ps
CPU time	1641.38 seconds
Started	Jan 10 12:52:13 PM PST 24
Finished	Jan 10 01:20:50 PM PST 24
Peak memory	374284 kb
Host	smart-acdfd8f6-7813-45ef-8dbc-f5895d4dc4ae
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930624437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_an d_output.930624437 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/36.kmac_sideload.235942740
Short name	T517
Test name
Test status
Simulation time	46571273580 ps
CPU time	404.72 seconds
Started	Jan 10 12:52:11 PM PST 24
Finished	Jan 10 01:00:17 PM PST 24
Peak memory	255084 kb
Host	smart-51c523f6-71ae-4312-aa05-ac19b00e7685
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=235942740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.235942740 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_sideload/latest

Test location	/workspace/coverage/default/36.kmac_smoke.633224676
Short name	T1001
Test name
Test status
Simulation time	3639611637 ps
CPU time	29.83 seconds
Started	Jan 10 12:52:13 PM PST 24
Finished	Jan 10 12:53:58 PM PST 24
Peak memory	219928 kb
Host	smart-5ff33e34-06b1-4793-ace7-1421b9f6d499
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=633224676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.633224676 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_smoke/latest

Test location	/workspace/coverage/default/36.kmac_stress_all.444185426
Short name	T579
Test name
Test status
Simulation time	67105714179 ps
CPU time	1759.01 seconds
Started	Jan 10 12:52:11 PM PST 24
Finished	Jan 10 01:22:48 PM PST 24
Peak memory	411436 kb
Host	smart-50b26288-c8f8-4bbc-8153-39fdcaff0b2b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=444185426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.444185426 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_stress_all/latest

Test location	/workspace/coverage/default/36.kmac_stress_all_with_rand_reset.1175915697
Short name	T598
Test name
Test status
Simulation time	298461956992 ps
CPU time	1871.77 seconds
Started	Jan 10 12:52:00 PM PST 24
Finished	Jan 10 01:24:28 PM PST 24
Peak memory	370504 kb
Host	smart-04e1b60e-6995-4400-a004-c5f5ba7e3344
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1175915697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all_with_rand_reset.1175915697 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_kmac.2315786070
Short name	T192
Test name
Test status
Simulation time	2366713554 ps
CPU time	6.14 seconds
Started	Jan 10 12:52:16 PM PST 24
Finished	Jan 10 12:53:54 PM PST 24
Peak memory	219368 kb
Host	smart-3d1bf0c8-a0a9-4202-a704-1f0fa88638d6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315786070 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 36.kmac_test_vectors_kmac.2315786070 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_kmac_xof.2080743303
Short name	T697
Test name
Test status
Simulation time	269776631 ps
CPU time	5.93 seconds
Started	Jan 10 12:52:08 PM PST 24
Finished	Jan 10 12:53:33 PM PST 24
Peak memory	220936 kb
Host	smart-17558b81-fae1-4264-b68e-8d6affebb047
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080743303 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_kmac_xof.2080743303 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_224.3358891472
Short name	T873
Test name
Test status
Simulation time	263778178753 ps
CPU time	2061.53 seconds
Started	Jan 10 12:52:05 PM PST 24
Finished	Jan 10 01:27:42 PM PST 24
Peak memory	395940 kb
Host	smart-12e79903-0ed3-4456-a285-84fa205056c7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3358891472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.3358891472 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_256.460832164
Short name	T938
Test name
Test status
Simulation time	609195149189 ps
CPU time	2321.27 seconds
Started	Jan 10 12:52:09 PM PST 24
Finished	Jan 10 01:32:03 PM PST 24
Peak memory	381344 kb
Host	smart-20cb991a-e8c7-4383-9c1f-c2bb3f5a9661
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=460832164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.460832164 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_384.3678430825
Short name	T989
Test name
Test status
Simulation time	19849554185 ps
CPU time	1462.24 seconds
Started	Jan 10 12:52:14 PM PST 24
Finished	Jan 10 01:17:49 PM PST 24
Peak memory	343024 kb
Host	smart-3ae4179d-4f9f-438c-9885-62f8d1d50c85
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3678430825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.3678430825 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_512.1527099859
Short name	T983
Test name
Test status
Simulation time	10261153081 ps
CPU time	1029.72 seconds
Started	Jan 10 12:52:26 PM PST 24
Finished	Jan 10 01:10:49 PM PST 24
Peak memory	294864 kb
Host	smart-7d9c2bbe-eb85-4e47-b4e6-ca126d452f25
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1527099859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.1527099859 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_shake_128.169947058
Short name	T778
Test name
Test status
Simulation time	1448423339287 ps
CPU time	5992.21 seconds
Started	Jan 10 12:52:07 PM PST 24
Finished	Jan 10 02:33:15 PM PST 24
Peak memory	640348 kb
Host	smart-c8556691-bdbb-492f-96d0-c82739b279b4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=169947058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.169947058 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/37.kmac_alert_test.282862625
Short name	T479
Test name
Test status
Simulation time	12310973 ps
CPU time	0.77 seconds
Started	Jan 10 12:52:11 PM PST 24
Finished	Jan 10 12:53:29 PM PST 24
Peak memory	220228 kb
Host	smart-d64507ee-8b14-49a9-b522-0e21db5bdd7c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282862625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.282862625 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_alert_test/latest

Test location	/workspace/coverage/default/37.kmac_app.2492848705
Short name	T632
Test name
Test status
Simulation time	222847680 ps
CPU time	4.11 seconds
Started	Jan 10 12:52:08 PM PST 24
Finished	Jan 10 12:53:31 PM PST 24
Peak memory	219396 kb
Host	smart-9d2f81ae-5bda-4606-a98d-3fe37d5e1a5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2492848705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.2492848705 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_app/latest

Test location	/workspace/coverage/default/37.kmac_burst_write.2924082581
Short name	T753
Test name
Test status
Simulation time	14897743498 ps
CPU time	166.85 seconds
Started	Jan 10 12:52:18 PM PST 24
Finished	Jan 10 12:56:20 PM PST 24
Peak memory	238352 kb
Host	smart-2cd8b224-9df1-476b-8be2-287993f2d34e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2924082581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.2924082581 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_burst_write/latest

Test location	/workspace/coverage/default/37.kmac_entropy_refresh.3796191701
Short name	T469
Test name
Test status
Simulation time	5830997472 ps
CPU time	116.56 seconds
Started	Jan 10 12:52:15 PM PST 24
Finished	Jan 10 12:55:32 PM PST 24
Peak memory	236636 kb
Host	smart-fb82396f-1cd6-407c-989a-c57478857d37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3796191701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.3796191701 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/37.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/37.kmac_error.4264475093
Short name	T231
Test name
Test status
Simulation time	17618412078 ps
CPU time	93.37 seconds
Started	Jan 10 12:52:27 PM PST 24
Finished	Jan 10 12:55:12 PM PST 24
Peak memory	243520 kb
Host	smart-3bf57181-44d7-4eda-8e7d-2da55b74400f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4264475093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.4264475093 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_error/latest

Test location	/workspace/coverage/default/37.kmac_key_error.2790027705
Short name	T971
Test name
Test status
Simulation time	695767854 ps
CPU time	1.57 seconds
Started	Jan 10 12:52:17 PM PST 24
Finished	Jan 10 12:53:50 PM PST 24
Peak memory	219180 kb
Host	smart-31f86307-a58a-44ad-93b6-766c53766afa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2790027705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.2790027705 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_key_error/latest

Test location	/workspace/coverage/default/37.kmac_lc_escalation.1574259138
Short name	T1048
Test name
Test status
Simulation time	76525594 ps
CPU time	1.29 seconds
Started	Jan 10 12:52:13 PM PST 24
Finished	Jan 10 12:53:32 PM PST 24
Peak memory	220356 kb
Host	smart-871dba94-549b-4728-bc89-55dd8b9a446d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1574259138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.1574259138 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/37.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/37.kmac_long_msg_and_output.1073435507
Short name	T335
Test name
Test status
Simulation time	63126271221 ps
CPU time	869.03 seconds
Started	Jan 10 12:52:17 PM PST 24
Finished	Jan 10 01:08:18 PM PST 24
Peak memory	296272 kb
Host	smart-bbc4db28-839f-4799-a270-0ada8d3ac141
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073435507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a nd_output.1073435507 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/37.kmac_sideload.633085754
Short name	T834
Test name
Test status
Simulation time	3034349408 ps
CPU time	94.52 seconds
Started	Jan 10 12:52:25 PM PST 24
Finished	Jan 10 12:55:09 PM PST 24
Peak memory	240972 kb
Host	smart-e7c18e0d-cb7c-4e8a-a7c0-406a3737211d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=633085754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.633085754 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_sideload/latest

Test location	/workspace/coverage/default/37.kmac_smoke.1028824872
Short name	T999
Test name
Test status
Simulation time	2975496838 ps
CPU time	72.71 seconds
Started	Jan 10 12:52:08 PM PST 24
Finished	Jan 10 12:54:39 PM PST 24
Peak memory	227508 kb
Host	smart-9d993fd6-674f-4242-b68d-87cc672e5e43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1028824872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.1028824872 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_smoke/latest

Test location	/workspace/coverage/default/37.kmac_stress_all.2734679489
Short name	T568
Test name
Test status
Simulation time	43890520535 ps
CPU time	1487.85 seconds
Started	Jan 10 12:52:23 PM PST 24
Finished	Jan 10 01:18:33 PM PST 24
Peak memory	393224 kb
Host	smart-a97f29e2-fa45-4cfc-af71-96f78daffbbc
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2734679489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.2734679489 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_stress_all/latest

Test location	/workspace/coverage/default/37.kmac_stress_all_with_rand_reset.2756547314
Short name	T825
Test name
Test status
Simulation time	22645698167 ps
CPU time	753.56 seconds
Started	Jan 10 12:52:15 PM PST 24
Finished	Jan 10 01:06:00 PM PST 24
Peak memory	301484 kb
Host	smart-1ffe3246-d542-4bcf-a718-3b479f74be5e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2756547314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all_with_rand_reset.2756547314 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_kmac.2220333379
Short name	T1059
Test name
Test status
Simulation time	196434885 ps
CPU time	6.12 seconds
Started	Jan 10 12:52:10 PM PST 24
Finished	Jan 10 12:53:28 PM PST 24
Peak memory	220832 kb
Host	smart-4cb3305b-17be-4f96-b76a-32768f445aa6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220333379 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 37.kmac_test_vectors_kmac.2220333379 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_kmac_xof.93791290
Short name	T530
Test name
Test status
Simulation time	239927235 ps
CPU time	5.83 seconds
Started	Jan 10 12:52:19 PM PST 24
Finished	Jan 10 12:53:35 PM PST 24
Peak memory	220824 kb
Host	smart-d278fcb7-2f94-4084-b5a5-70b6c0423b46
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93791290 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 37.kmac_test_vectors_kmac_xof.93791290 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_224.1556977728
Short name	T345
Test name
Test status
Simulation time	213836516181 ps
CPU time	2206.03 seconds
Started	Jan 10 12:52:29 PM PST 24
Finished	Jan 10 01:30:33 PM PST 24
Peak memory	404680 kb
Host	smart-3dbefc8a-47d1-4efe-8118-9c77f73dbca8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1556977728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.1556977728 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_256.2157271365
Short name	T1018
Test name
Test status
Simulation time	331535897030 ps
CPU time	2265.96 seconds
Started	Jan 10 12:52:18 PM PST 24
Finished	Jan 10 01:31:15 PM PST 24
Peak memory	390828 kb
Host	smart-73b61877-bc19-4f54-8604-368f742757c2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2157271365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.2157271365 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_384.1782774365
Short name	T728
Test name
Test status
Simulation time	431997757443 ps
CPU time	1630.02 seconds
Started	Jan 10 12:53:07 PM PST 24
Finished	Jan 10 01:21:28 PM PST 24
Peak memory	341876 kb
Host	smart-6a251846-8de6-4b6f-a5e0-70365f9768b1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1782774365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.1782774365 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_512.3209276587
Short name	T267
Test name
Test status
Simulation time	10838401334 ps
CPU time	1047.19 seconds
Started	Jan 10 12:52:25 PM PST 24
Finished	Jan 10 01:11:06 PM PST 24
Peak memory	296916 kb
Host	smart-2b67f8fe-2abf-4886-8b46-f93964064c0d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3209276587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.3209276587 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_shake_128.1444060796
Short name	T363
Test name
Test status
Simulation time	969986271958 ps
CPU time	6077.84 seconds
Started	Jan 10 12:52:11 PM PST 24
Finished	Jan 10 02:34:44 PM PST 24
Peak memory	666496 kb
Host	smart-c86dde03-0c38-4a41-9311-dcda5f18d686
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1444060796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.1444060796 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_shake_256.2648910488
Short name	T488
Test name
Test status
Simulation time	316156520290 ps
CPU time	4801.11 seconds
Started	Jan 10 12:52:25 PM PST 24
Finished	Jan 10 02:13:41 PM PST 24
Peak memory	565800 kb
Host	smart-ef09ab29-d122-44bd-9836-d4701740f894
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2648910488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.2648910488 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/38.kmac_alert_test.2765882004
Short name	T896
Test name
Test status
Simulation time	30564297 ps
CPU time	0.84 seconds
Started	Jan 10 12:52:13 PM PST 24
Finished	Jan 10 12:53:25 PM PST 24
Peak memory	219096 kb
Host	smart-8cebbd78-789f-472e-9c00-44810503d285
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765882004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.2765882004 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_alert_test/latest

Test location	/workspace/coverage/default/38.kmac_app.623724621
Short name	T475
Test name
Test status
Simulation time	3759390666 ps
CPU time	26.17 seconds
Started	Jan 10 12:52:14 PM PST 24
Finished	Jan 10 12:54:01 PM PST 24
Peak memory	235408 kb
Host	smart-4cf3d649-cc9b-4118-8738-16a3be8bb360
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=623724621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.623724621 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_app/latest

Test location	/workspace/coverage/default/38.kmac_burst_write.3509395944
Short name	T208
Test name
Test status
Simulation time	12511863300 ps
CPU time	1058.81 seconds
Started	Jan 10 12:52:14 PM PST 24
Finished	Jan 10 01:11:14 PM PST 24
Peak memory	239256 kb
Host	smart-f37ff137-74ca-480f-9bea-3fc8cb2a8591
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3509395944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.3509395944 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_burst_write/latest

Test location	/workspace/coverage/default/38.kmac_entropy_refresh.3589744247
Short name	T627
Test name
Test status
Simulation time	11871469276 ps
CPU time	105.79 seconds
Started	Jan 10 12:52:15 PM PST 24
Finished	Jan 10 12:55:12 PM PST 24
Peak memory	236120 kb
Host	smart-3f37ceb7-c43b-4ad3-b43e-32ef249cfe09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3589744247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.3589744247 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/38.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/38.kmac_error.837970317
Short name	T1057
Test name
Test status
Simulation time	4505114571 ps
CPU time	117.83 seconds
Started	Jan 10 12:52:22 PM PST 24
Finished	Jan 10 12:55:34 PM PST 24
Peak memory	252136 kb
Host	smart-f9251f58-a118-4c5e-ab15-bab055cf8af7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=837970317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.837970317 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_error/latest

Test location	/workspace/coverage/default/38.kmac_key_error.1835036167
Short name	T599
Test name
Test status
Simulation time	1518543168 ps
CPU time	2.87 seconds
Started	Jan 10 12:52:14 PM PST 24
Finished	Jan 10 12:53:48 PM PST 24
Peak memory	219248 kb
Host	smart-c6cec7bd-4ba0-468a-98a1-cd3748480429
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1835036167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.1835036167 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_key_error/latest

Test location	/workspace/coverage/default/38.kmac_lc_escalation.1106034412
Short name	T246
Test name
Test status
Simulation time	42395540 ps
CPU time	1.34 seconds
Started	Jan 10 12:52:24 PM PST 24
Finished	Jan 10 12:53:40 PM PST 24
Peak memory	220292 kb
Host	smart-491f69e8-a131-4067-8d6b-77f1aaf0500a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1106034412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.1106034412 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/38.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/38.kmac_long_msg_and_output.293266992
Short name	T399
Test name
Test status
Simulation time	21113440701 ps
CPU time	2244.51 seconds
Started	Jan 10 12:52:24 PM PST 24
Finished	Jan 10 01:31:10 PM PST 24
Peak memory	425900 kb
Host	smart-598a3029-0275-4b3c-91ad-a3dd88440be9
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293266992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_an d_output.293266992 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/38.kmac_sideload.1562422317
Short name	T968
Test name
Test status
Simulation time	50571558895 ps
CPU time	255.83 seconds
Started	Jan 10 12:52:27 PM PST 24
Finished	Jan 10 12:58:05 PM PST 24
Peak memory	245324 kb
Host	smart-992c5624-21e1-4310-b3b3-62ae414feda0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1562422317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.1562422317 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_sideload/latest

Test location	/workspace/coverage/default/38.kmac_smoke.880573375
Short name	T207
Test name
Test status
Simulation time	3736081943 ps
CPU time	43.22 seconds
Started	Jan 10 12:52:18 PM PST 24
Finished	Jan 10 12:54:12 PM PST 24
Peak memory	227436 kb
Host	smart-9d130cda-9db4-4786-9147-5a7e6c65c3f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=880573375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.880573375 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_smoke/latest

Test location	/workspace/coverage/default/38.kmac_stress_all.1142233326
Short name	T800
Test name
Test status
Simulation time	32550753749 ps
CPU time	441.61 seconds
Started	Jan 10 12:52:23 PM PST 24
Finished	Jan 10 01:01:07 PM PST 24
Peak memory	303216 kb
Host	smart-091863fc-5b85-4f93-af98-0290ca0cb214
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1142233326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.1142233326 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_stress_all/latest

Test location	/workspace/coverage/default/38.kmac_stress_all_with_rand_reset.744903776
Short name	T239
Test name
Test status
Simulation time	38844013088 ps
CPU time	1256.56 seconds
Started	Jan 10 12:52:27 PM PST 24
Finished	Jan 10 01:14:34 PM PST 24
Peak memory	325024 kb
Host	smart-06e31800-f65f-4a14-8fb2-7e4f367f2752
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=744903776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all_with_rand_reset.744903776 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_kmac.2716106658
Short name	T180
Test name
Test status
Simulation time	831954543 ps
CPU time	6.07 seconds
Started	Jan 10 12:52:24 PM PST 24
Finished	Jan 10 12:53:42 PM PST 24
Peak memory	219128 kb
Host	smart-2def5c1c-62a3-4288-a1a8-079de3ac1a65
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716106658 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 38.kmac_test_vectors_kmac.2716106658 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_kmac_xof.87865306
Short name	T885
Test name
Test status
Simulation time	428505009 ps
CPU time	5.88 seconds
Started	Jan 10 12:52:16 PM PST 24
Finished	Jan 10 12:53:37 PM PST 24
Peak memory	220848 kb
Host	smart-068d82a0-98ea-46b4-b66b-3a259b1f8216
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87865306 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 38.kmac_test_vectors_kmac_xof.87865306 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_224.3858635314
Short name	T986
Test name
Test status
Simulation time	134410996407 ps
CPU time	2160.65 seconds
Started	Jan 10 12:52:27 PM PST 24
Finished	Jan 10 01:29:39 PM PST 24
Peak memory	398332 kb
Host	smart-a0e7b074-a5e1-4d4b-b90a-e526a8f3e5ae
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3858635314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.3858635314 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_256.942445424
Short name	T988
Test name
Test status
Simulation time	187295738694 ps
CPU time	2159.37 seconds
Started	Jan 10 12:52:26 PM PST 24
Finished	Jan 10 01:29:39 PM PST 24
Peak memory	382100 kb
Host	smart-93f856a8-9550-4ba8-9f65-2b997c9f5723
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=942445424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.942445424 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_384.2192641064
Short name	T906
Test name
Test status
Simulation time	65035250177 ps
CPU time	1663.29 seconds
Started	Jan 10 12:52:21 PM PST 24
Finished	Jan 10 01:21:21 PM PST 24
Peak memory	346972 kb
Host	smart-9a4bb6c5-c557-41a2-a4ff-31ecbc16ea40
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2192641064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.2192641064 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_512.3977514144
Short name	T1041
Test name
Test status
Simulation time	41168394974 ps
CPU time	1248.57 seconds
Started	Jan 10 12:52:24 PM PST 24
Finished	Jan 10 01:14:34 PM PST 24
Peak memory	305560 kb
Host	smart-b4d64822-c422-4424-bdfe-0b1d552570c9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3977514144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.3977514144 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_shake_128.3680952402
Short name	T1004
Test name
Test status
Simulation time	1328909332316 ps
CPU time	6066.56 seconds
Started	Jan 10 12:52:23 PM PST 24
Finished	Jan 10 02:34:44 PM PST 24
Peak memory	661396 kb
Host	smart-9c3955c0-56c2-4915-a471-dca78990f84d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3680952402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.3680952402 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_shake_256.2943031156
Short name	T1066
Test name
Test status
Simulation time	661221836322 ps
CPU time	4380.66 seconds
Started	Jan 10 12:52:24 PM PST 24
Finished	Jan 10 02:06:40 PM PST 24
Peak memory	569376 kb
Host	smart-c9c415c6-d4f3-4683-b706-d938acda0758
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2943031156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.2943031156 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/39.kmac_alert_test.1435886548
Short name	T516
Test name
Test status
Simulation time	29113873 ps
CPU time	0.85 seconds
Started	Jan 10 12:52:21 PM PST 24
Finished	Jan 10 12:53:42 PM PST 24
Peak memory	220268 kb
Host	smart-6306be77-ec69-4e03-80a9-2c8b1f9dc8ee
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435886548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.1435886548 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_alert_test/latest

Test location	/workspace/coverage/default/39.kmac_app.804628808
Short name	T715
Test name
Test status
Simulation time	3937910086 ps
CPU time	38.32 seconds
Started	Jan 10 12:52:26 PM PST 24
Finished	Jan 10 12:54:24 PM PST 24
Peak memory	229136 kb
Host	smart-c4b41ab7-f556-416e-81d2-7d0b78b51ae0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=804628808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.804628808 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_app/latest

Test location	/workspace/coverage/default/39.kmac_entropy_refresh.1689929211
Short name	T534
Test name
Test status
Simulation time	42392865745 ps
CPU time	252.83 seconds
Started	Jan 10 12:52:16 PM PST 24
Finished	Jan 10 12:58:01 PM PST 24
Peak memory	248172 kb
Host	smart-5ff21ecc-f9bd-453f-b939-66e94dfaad16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1689929211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.1689929211 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/39.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/39.kmac_error.3397453278
Short name	T889
Test name
Test status
Simulation time	31156257835 ps
CPU time	105.97 seconds
Started	Jan 10 12:52:18 PM PST 24
Finished	Jan 10 12:55:15 PM PST 24
Peak memory	252028 kb
Host	smart-a0319aff-cced-4d98-aadd-50de7959dfb3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3397453278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.3397453278 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_error/latest

Test location	/workspace/coverage/default/39.kmac_key_error.1757007635
Short name	T299
Test name
Test status
Simulation time	1204747345 ps
CPU time	3.72 seconds
Started	Jan 10 12:52:17 PM PST 24
Finished	Jan 10 12:53:52 PM PST 24
Peak memory	219240 kb
Host	smart-495a10c9-4c58-47f1-9fb7-11b20c27d6e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1757007635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.1757007635 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_key_error/latest

Test location	/workspace/coverage/default/39.kmac_lc_escalation.2597553428
Short name	T688
Test name
Test status
Simulation time	45934245 ps
CPU time	1.44 seconds
Started	Jan 10 12:52:22 PM PST 24
Finished	Jan 10 12:53:38 PM PST 24
Peak memory	220148 kb
Host	smart-0d8d59d0-89b6-44b1-b31f-4da8e5cd254d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2597553428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.2597553428 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/39.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/39.kmac_long_msg_and_output.1795536095
Short name	T661
Test name
Test status
Simulation time	24168228912 ps
CPU time	2307.03 seconds
Started	Jan 10 12:52:14 PM PST 24
Finished	Jan 10 01:31:54 PM PST 24
Peak memory	437584 kb
Host	smart-d6bd7821-4c40-4b2b-b8ad-723a3e2d113a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795536095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a nd_output.1795536095 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/39.kmac_sideload.1860232067
Short name	T266
Test name
Test status
Simulation time	19041945223 ps
CPU time	121.15 seconds
Started	Jan 10 12:52:18 PM PST 24
Finished	Jan 10 12:55:34 PM PST 24
Peak memory	242288 kb
Host	smart-c4f9d0ba-3684-4ec5-8f68-6fa17d16dbf3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1860232067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.1860232067 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_sideload/latest

Test location	/workspace/coverage/default/39.kmac_smoke.4088558885
Short name	T493
Test name
Test status
Simulation time	3411566730 ps
CPU time	30.16 seconds
Started	Jan 10 12:52:11 PM PST 24
Finished	Jan 10 12:53:59 PM PST 24
Peak memory	225180 kb
Host	smart-4570efe2-9158-47b3-b55f-af8d73ab735d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4088558885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.4088558885 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_smoke/latest

Test location	/workspace/coverage/default/39.kmac_stress_all.2318216285
Short name	T448
Test name
Test status
Simulation time	33039587669 ps
CPU time	587.94 seconds
Started	Jan 10 12:52:18 PM PST 24
Finished	Jan 10 01:03:21 PM PST 24
Peak memory	307668 kb
Host	smart-ba61e617-9725-4125-98d1-c249a4b74aec
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2318216285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.2318216285 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_stress_all/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_kmac.746595744
Short name	T310
Test name
Test status
Simulation time	225895254 ps
CPU time	6.35 seconds
Started	Jan 10 12:52:27 PM PST 24
Finished	Jan 10 12:53:55 PM PST 24
Peak memory	220804 kb
Host	smart-b9afa163-8a56-4104-842c-ae34614821df
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746595744 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 39.kmac_test_vectors_kmac.746595744 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_kmac_xof.1274274868
Short name	T225
Test name
Test status
Simulation time	388079085 ps
CPU time	5.65 seconds
Started	Jan 10 12:52:17 PM PST 24
Finished	Jan 10 12:53:43 PM PST 24
Peak memory	220856 kb
Host	smart-9f0800df-3e4b-48f8-93c1-6efbbe794103
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274274868 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_kmac_xof.1274274868 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_224.2502604669
Short name	T237
Test name
Test status
Simulation time	272249165234 ps
CPU time	2154.23 seconds
Started	Jan 10 12:52:22 PM PST 24
Finished	Jan 10 01:29:31 PM PST 24
Peak memory	398452 kb
Host	smart-01fc8aa4-8d5d-439a-a21e-fb25590596db
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2502604669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.2502604669 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_256.697656802
Short name	T861
Test name
Test status
Simulation time	76986820866 ps
CPU time	1945.96 seconds
Started	Jan 10 12:52:21 PM PST 24
Finished	Jan 10 01:25:58 PM PST 24
Peak memory	392396 kb
Host	smart-b54c4bfb-0aeb-4ce2-9cf1-8d3fa12e4430
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=697656802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.697656802 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_384.3478060410
Short name	T679
Test name
Test status
Simulation time	64656627291 ps
CPU time	1477.52 seconds
Started	Jan 10 12:52:14 PM PST 24
Finished	Jan 10 01:18:04 PM PST 24
Peak memory	353832 kb
Host	smart-f96a0afa-774b-43a7-bab1-c36ce4a1db68
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3478060410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.3478060410 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_512.2870377332
Short name	T156
Test name
Test status
Simulation time	49892044667 ps
CPU time	1301.9 seconds
Started	Jan 10 12:52:19 PM PST 24
Finished	Jan 10 01:15:12 PM PST 24
Peak memory	301652 kb
Host	smart-f52f0dc0-f083-4515-843e-03107140e030
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2870377332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.2870377332 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_shake_128.3247855718
Short name	T982
Test name
Test status
Simulation time	61027866939 ps
CPU time	5372.8 seconds
Started	Jan 10 12:52:16 PM PST 24
Finished	Jan 10 02:23:07 PM PST 24
Peak memory	669780 kb
Host	smart-95868c66-e49a-4b62-b8f6-3c89a0f9c2ab
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3247855718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.3247855718 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_shake_256.3940078003
Short name	T847
Test name
Test status
Simulation time	614088728872 ps
CPU time	4847.15 seconds
Started	Jan 10 12:52:26 PM PST 24
Finished	Jan 10 02:14:27 PM PST 24
Peak memory	577956 kb
Host	smart-f6bb0077-bf0f-4c03-9455-779cf6d3f035
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3940078003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.3940078003 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/4.kmac_alert_test.3091564522
Short name	T791
Test name
Test status
Simulation time	36930243 ps
CPU time	0.83 seconds
Started	Jan 10 12:50:53 PM PST 24
Finished	Jan 10 12:52:05 PM PST 24
Peak memory	219164 kb
Host	smart-da9d94f5-9fbb-4983-b6d0-be703dc01079
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091564522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.3091564522 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_alert_test/latest

Test location	/workspace/coverage/default/4.kmac_app.1763401053
Short name	T181
Test name
Test status
Simulation time	4148455145 ps
CPU time	90.81 seconds
Started	Jan 10 12:50:23 PM PST 24
Finished	Jan 10 12:53:12 PM PST 24
Peak memory	235160 kb
Host	smart-70379e80-7d14-4f68-b3f7-d566251d75a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1763401053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.1763401053 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_app/latest

Test location	/workspace/coverage/default/4.kmac_app_with_partial_data.3125205505
Short name	T472
Test name
Test status
Simulation time	95689932995 ps
CPU time	340.76 seconds
Started	Jan 10 12:50:24 PM PST 24
Finished	Jan 10 12:57:23 PM PST 24
Peak memory	252588 kb
Host	smart-eee828a8-d734-413e-8f9f-2cca1c53d0ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3125205505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.3125205505 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/4.kmac_burst_write.3182360760
Short name	T736
Test name
Test status
Simulation time	26601232596 ps
CPU time	1209.02 seconds
Started	Jan 10 12:50:23 PM PST 24
Finished	Jan 10 01:11:59 PM PST 24
Peak memory	241132 kb
Host	smart-68e70a73-6a61-4095-8b26-a082a3b53430
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3182360760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.3182360760 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_burst_write/latest

Test location	/workspace/coverage/default/4.kmac_edn_timeout_error.3596897627
Short name	T781
Test name
Test status
Simulation time	28301797 ps
CPU time	0.89 seconds
Started	Jan 10 12:50:55 PM PST 24
Finished	Jan 10 12:52:24 PM PST 24
Peak memory	219068 kb
Host	smart-0db58579-114a-4b7a-8a23-f3a380cc5476
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3596897627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.3596897627 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/4.kmac_entropy_mode_error.3502509079
Short name	T73
Test name
Test status
Simulation time	35197128 ps
CPU time	1.17 seconds
Started	Jan 10 12:50:24 PM PST 24
Finished	Jan 10 12:51:43 PM PST 24
Peak memory	219240 kb
Host	smart-86f1a25f-00cf-489c-9817-2efac90a5981
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3502509079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.3502509079 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/4.kmac_entropy_refresh.4061872395
Short name	T324
Test name
Test status
Simulation time	59673661615 ps
CPU time	387.27 seconds
Started	Jan 10 12:50:24 PM PST 24
Finished	Jan 10 12:58:17 PM PST 24
Peak memory	255760 kb
Host	smart-58f51556-1a99-4fcb-affc-c207407e07e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4061872395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.4061872395 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/4.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/4.kmac_error.3933405044
Short name	T583
Test name
Test status
Simulation time	8325837866 ps
CPU time	455.57 seconds
Started	Jan 10 12:50:29 PM PST 24
Finished	Jan 10 12:59:31 PM PST 24
Peak memory	268472 kb
Host	smart-828d9a72-bbe4-4635-8fec-0cd047e346ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3933405044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.3933405044 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_error/latest

Test location	/workspace/coverage/default/4.kmac_key_error.4195246194
Short name	T24
Test name
Test status
Simulation time	1794450446 ps
CPU time	3.49 seconds
Started	Jan 10 12:50:20 PM PST 24
Finished	Jan 10 12:51:59 PM PST 24
Peak memory	219272 kb
Host	smart-e93bc964-4073-4d04-9b99-9d80e84cc98f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4195246194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.4195246194 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_key_error/latest

Test location	/workspace/coverage/default/4.kmac_lc_escalation.1714808282
Short name	T807
Test name
Test status
Simulation time	33258535 ps
CPU time	1.28 seconds
Started	Jan 10 12:50:28 PM PST 24
Finished	Jan 10 12:51:49 PM PST 24
Peak memory	220368 kb
Host	smart-30c40b66-7ee1-480c-8609-1f44b0f05df3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1714808282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.1714808282 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/4.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/4.kmac_long_msg_and_output.2346867835
Short name	T556
Test name
Test status
Simulation time	129189925137 ps
CPU time	2132.12 seconds
Started	Jan 10 12:51:58 PM PST 24
Finished	Jan 10 01:28:44 PM PST 24
Peak memory	422228 kb
Host	smart-e4f0b429-4751-47c1-ae67-1e28efe21d82
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346867835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an d_output.2346867835 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/4.kmac_mubi.1395867619
Short name	T942
Test name
Test status
Simulation time	8525724948 ps
CPU time	250.44 seconds
Started	Jan 10 12:50:31 PM PST 24
Finished	Jan 10 12:55:58 PM PST 24
Peak memory	246756 kb
Host	smart-dafdaa18-a079-4af7-ad91-e7f1e28146a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1395867619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.1395867619 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_mubi/latest

Test location	/workspace/coverage/default/4.kmac_sec_cm.4215582253
Short name	T98
Test name
Test status
Simulation time	7534490957 ps
CPU time	116.83 seconds
Started	Jan 10 12:50:18 PM PST 24
Finished	Jan 10 12:53:42 PM PST 24
Peak memory	299388 kb
Host	smart-a533b938-f749-486a-8d53-89b45910e2c0
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215582253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.4215582253 +enable_maski ng=1 +sw_key_masked=0
Directory	/workspace/4.kmac_sec_cm/latest

Test location	/workspace/coverage/default/4.kmac_sideload.1889013875
Short name	T890
Test name
Test status
Simulation time	29203284384 ps
CPU time	185.9 seconds
Started	Jan 10 12:50:42 PM PST 24
Finished	Jan 10 12:55:09 PM PST 24
Peak memory	240804 kb
Host	smart-4b53d683-e871-4463-a108-af801ad67666
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1889013875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.1889013875 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_sideload/latest

Test location	/workspace/coverage/default/4.kmac_smoke.161445398
Short name	T855
Test name
Test status
Simulation time	1348121863 ps
CPU time	28.58 seconds
Started	Jan 10 12:50:14 PM PST 24
Finished	Jan 10 12:52:04 PM PST 24
Peak memory	219276 kb
Host	smart-22b36ff9-148a-42b6-adda-41a78372bed9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=161445398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.161445398 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_smoke/latest

Test location	/workspace/coverage/default/4.kmac_stress_all.1565847555
Short name	T457
Test name
Test status
Simulation time	53720587485 ps
CPU time	958.72 seconds
Started	Jan 10 12:50:31 PM PST 24
Finished	Jan 10 01:07:54 PM PST 24
Peak memory	339096 kb
Host	smart-a9551a3c-978e-43c5-b9aa-9195e7a0111c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1565847555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.1565847555 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_stress_all/latest

Test location	/workspace/coverage/default/4.kmac_stress_all_with_rand_reset.1500021875
Short name	T835
Test name
Test status
Simulation time	31698457387 ps
CPU time	787.8 seconds
Started	Jan 10 12:50:24 PM PST 24
Finished	Jan 10 01:04:49 PM PST 24
Peak memory	293428 kb
Host	smart-b5e7ac73-694f-4812-a2ca-12fc897917f2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1500021875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all_with_rand_reset.1500021875 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_kmac.2559881411
Short name	T330
Test name
Test status
Simulation time	882144886 ps
CPU time	6.47 seconds
Started	Jan 10 12:50:23 PM PST 24
Finished	Jan 10 12:51:48 PM PST 24
Peak memory	219408 kb
Host	smart-a41b7c4c-7229-4f91-b3ba-03735c551186
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559881411 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.kmac_test_vectors_kmac.2559881411 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_kmac_xof.678633775
Short name	T1093
Test name
Test status
Simulation time	191964698 ps
CPU time	5.54 seconds
Started	Jan 10 12:50:23 PM PST 24
Finished	Jan 10 12:51:55 PM PST 24
Peak memory	220568 kb
Host	smart-a8b4bf22-4d0b-42e7-8631-9060848bf9cc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678633775 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 4.kmac_test_vectors_kmac_xof.678633775 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_224.1139056459
Short name	T1085
Test name
Test status
Simulation time	234019568252 ps
CPU time	1894.8 seconds
Started	Jan 10 12:50:22 PM PST 24
Finished	Jan 10 01:23:26 PM PST 24
Peak memory	399600 kb
Host	smart-8eed7dde-f526-446b-b88f-e1f354d9dee7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1139056459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.1139056459 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_256.542703726
Short name	T501
Test name
Test status
Simulation time	20274145979 ps
CPU time	1794.08 seconds
Started	Jan 10 12:50:10 PM PST 24
Finished	Jan 10 01:21:52 PM PST 24
Peak memory	393700 kb
Host	smart-88521e63-c4f4-488d-bb2f-4567426495dc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=542703726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.542703726 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_384.676044009
Short name	T1058
Test name
Test status
Simulation time	60887909352 ps
CPU time	1329.16 seconds
Started	Jan 10 12:50:18 PM PST 24
Finished	Jan 10 01:14:04 PM PST 24
Peak memory	338584 kb
Host	smart-1f237415-7fc8-410d-8354-88fdc7fb4a94
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=676044009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.676044009 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_512.2603489810
Short name	T322
Test name
Test status
Simulation time	257682275573 ps
CPU time	1242.78 seconds
Started	Jan 10 12:50:18 PM PST 24
Finished	Jan 10 01:12:40 PM PST 24
Peak memory	303128 kb
Host	smart-a8e53d04-bb1e-4bd2-bf98-9cdaeb05d44f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2603489810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.2603489810 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_shake_128.4018276911
Short name	T326
Test name
Test status
Simulation time	128056014413 ps
CPU time	4863.34 seconds
Started	Jan 10 12:51:03 PM PST 24
Finished	Jan 10 02:13:25 PM PST 24
Peak memory	655400 kb
Host	smart-40f03748-83af-4b61-907d-469bc837a7f5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4018276911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.4018276911 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/40.kmac_alert_test.2456781152
Short name	T806
Test name
Test status
Simulation time	27410213 ps
CPU time	0.84 seconds
Started	Jan 10 12:52:21 PM PST 24
Finished	Jan 10 12:53:33 PM PST 24
Peak memory	219000 kb
Host	smart-377079a6-10f8-4b4c-a482-fc4ef1ad64e8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456781152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.2456781152 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_alert_test/latest

Test location	/workspace/coverage/default/40.kmac_app.2123415701
Short name	T677
Test name
Test status
Simulation time	1316936768 ps
CPU time	29.54 seconds
Started	Jan 10 12:52:42 PM PST 24
Finished	Jan 10 12:54:22 PM PST 24
Peak memory	236400 kb
Host	smart-62270024-0501-44e4-9382-e9cc7f651f74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2123415701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.2123415701 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_app/latest

Test location	/workspace/coverage/default/40.kmac_burst_write.2716797943
Short name	T666
Test name
Test status
Simulation time	26162850869 ps
CPU time	1358.61 seconds
Started	Jan 10 12:52:19 PM PST 24
Finished	Jan 10 01:16:17 PM PST 24
Peak memory	241028 kb
Host	smart-4af536d8-03c9-431e-b993-ac02f6a3a43d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2716797943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.2716797943 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_burst_write/latest

Test location	/workspace/coverage/default/40.kmac_entropy_refresh.3648430674
Short name	T435
Test name
Test status
Simulation time	13482045261 ps
CPU time	311.74 seconds
Started	Jan 10 12:52:52 PM PST 24
Finished	Jan 10 12:59:16 PM PST 24
Peak memory	252032 kb
Host	smart-9176824b-5743-4c4c-8068-7c18e8f8256b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3648430674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.3648430674 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/40.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/40.kmac_error.1853935262
Short name	T601
Test name
Test status
Simulation time	59796668020 ps
CPU time	404.76 seconds
Started	Jan 10 12:52:26 PM PST 24
Finished	Jan 10 01:00:28 PM PST 24
Peak memory	260180 kb
Host	smart-270041a0-c2f2-48f8-b7dd-ea80616c3ad9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1853935262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.1853935262 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_error/latest

Test location	/workspace/coverage/default/40.kmac_key_error.699410724
Short name	T510
Test name
Test status
Simulation time	3261598310 ps
CPU time	5.77 seconds
Started	Jan 10 12:52:32 PM PST 24
Finished	Jan 10 12:53:52 PM PST 24
Peak memory	219268 kb
Host	smart-40e2d96b-a802-4e15-bd8c-c190db35ce31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=699410724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.699410724 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_key_error/latest

Test location	/workspace/coverage/default/40.kmac_lc_escalation.1137431125
Short name	T416
Test name
Test status
Simulation time	50403765 ps
CPU time	1.37 seconds
Started	Jan 10 12:52:21 PM PST 24
Finished	Jan 10 12:53:37 PM PST 24
Peak memory	220180 kb
Host	smart-d5f9e709-6f83-4051-bf23-6e91d9722d67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1137431125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.1137431125 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/40.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/40.kmac_long_msg_and_output.2945308433
Short name	T491
Test name
Test status
Simulation time	110436228295 ps
CPU time	1494.88 seconds
Started	Jan 10 12:52:17 PM PST 24
Finished	Jan 10 01:18:33 PM PST 24
Peak memory	335572 kb
Host	smart-7416a711-816e-4cb7-a575-9f944886a465
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945308433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_a nd_output.2945308433 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/40.kmac_sideload.1184325512
Short name	T1027
Test name
Test status
Simulation time	1366863908 ps
CPU time	26.02 seconds
Started	Jan 10 12:52:52 PM PST 24
Finished	Jan 10 12:54:30 PM PST 24
Peak memory	237436 kb
Host	smart-37fd18d9-e4c2-4a39-8f9c-730a3845af83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1184325512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.1184325512 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_sideload/latest

Test location	/workspace/coverage/default/40.kmac_smoke.2620918311
Short name	T565
Test name
Test status
Simulation time	5973436263 ps
CPU time	79.73 seconds
Started	Jan 10 12:52:18 PM PST 24
Finished	Jan 10 12:54:58 PM PST 24
Peak memory	221308 kb
Host	smart-ef9a4089-5836-4f9b-aceb-cb3ecbd63593
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2620918311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.2620918311 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_smoke/latest

Test location	/workspace/coverage/default/40.kmac_stress_all.1213250199
Short name	T705
Test name
Test status
Simulation time	55372496677 ps
CPU time	817.23 seconds
Started	Jan 10 12:52:26 PM PST 24
Finished	Jan 10 01:07:20 PM PST 24
Peak memory	310684 kb
Host	smart-74b3e599-dfaa-4480-874f-5b167ed5d141
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1213250199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.1213250199 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_stress_all/latest

Test location	/workspace/coverage/default/40.kmac_stress_all_with_rand_reset.283198388
Short name	T543
Test name
Test status
Simulation time	99832504614 ps
CPU time	2055.7 seconds
Started	Jan 10 12:52:20 PM PST 24
Finished	Jan 10 01:27:52 PM PST 24
Peak memory	342368 kb
Host	smart-b555deb5-f910-4cd7-8298-b86d0adc1c82
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=283198388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all_with_rand_reset.283198388 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_kmac.3628658988
Short name	T1043
Test name
Test status
Simulation time	435793803 ps
CPU time	6.86 seconds
Started	Jan 10 12:52:26 PM PST 24
Finished	Jan 10 12:53:55 PM PST 24
Peak memory	220660 kb
Host	smart-2bab693a-270a-4ee8-8a74-1ea730ceb4b3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628658988 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 40.kmac_test_vectors_kmac.3628658988 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_kmac_xof.233165940
Short name	T350
Test name
Test status
Simulation time	124063035 ps
CPU time	5.75 seconds
Started	Jan 10 12:52:25 PM PST 24
Finished	Jan 10 12:53:40 PM PST 24
Peak memory	220892 kb
Host	smart-8651f09c-eaa1-4ff8-b9db-84a46084ca14
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233165940 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 40.kmac_test_vectors_kmac_xof.233165940 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_224.3915321711
Short name	T764
Test name
Test status
Simulation time	286227780784 ps
CPU time	2065.97 seconds
Started	Jan 10 12:52:19 PM PST 24
Finished	Jan 10 01:28:02 PM PST 24
Peak memory	401312 kb
Host	smart-336dda19-5bd5-4aa2-bd04-78cdfd8d0873
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3915321711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.3915321711 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_256.2062078358
Short name	T659
Test name
Test status
Simulation time	40607591929 ps
CPU time	1763.03 seconds
Started	Jan 10 12:52:24 PM PST 24
Finished	Jan 10 01:22:58 PM PST 24
Peak memory	382780 kb
Host	smart-ca75229f-e8cc-4844-9d12-81e9790a25e8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2062078358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.2062078358 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_384.66298480
Short name	T935
Test name
Test status
Simulation time	102141783237 ps
CPU time	1743.33 seconds
Started	Jan 10 12:52:18 PM PST 24
Finished	Jan 10 01:22:40 PM PST 24
Peak memory	340208 kb
Host	smart-7f881c7b-1a9a-4cc4-91bd-d571988abc8c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=66298480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.66298480 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_512.3645521046
Short name	T1065
Test name
Test status
Simulation time	65575093667 ps
CPU time	1008.79 seconds
Started	Jan 10 12:52:27 PM PST 24
Finished	Jan 10 01:10:37 PM PST 24
Peak memory	299968 kb
Host	smart-95211fc5-9489-4b35-8137-9929f3db38eb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3645521046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.3645521046 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_shake_128.1761426998
Short name	T647
Test name
Test status
Simulation time	60091825369 ps
CPU time	4456.81 seconds
Started	Jan 10 12:52:47 PM PST 24
Finished	Jan 10 02:08:27 PM PST 24
Peak memory	649596 kb
Host	smart-33de1e56-15cf-4637-92ee-e68638459141
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1761426998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.1761426998 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_shake_256.845835091
Short name	T532
Test name
Test status
Simulation time	217949246928 ps
CPU time	4191.33 seconds
Started	Jan 10 12:52:29 PM PST 24
Finished	Jan 10 02:03:38 PM PST 24
Peak memory	569040 kb
Host	smart-d59eea2d-76f5-45a3-822b-cdc59d067f33
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=845835091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.845835091 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/41.kmac_alert_test.2810993154
Short name	T401
Test name
Test status
Simulation time	27592387 ps
CPU time	0.82 seconds
Started	Jan 10 12:52:22 PM PST 24
Finished	Jan 10 12:53:37 PM PST 24
Peak memory	220332 kb
Host	smart-09adb52e-81c2-400e-a0e1-3cf7171f2112
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810993154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.2810993154 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_alert_test/latest

Test location	/workspace/coverage/default/41.kmac_app.1209830864
Short name	T175
Test name
Test status
Simulation time	26221710106 ps
CPU time	352.01 seconds
Started	Jan 10 12:52:28 PM PST 24
Finished	Jan 10 12:59:30 PM PST 24
Peak memory	251820 kb
Host	smart-3977383d-90fe-4122-a03f-ef7203b81d65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1209830864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.1209830864 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_app/latest

Test location	/workspace/coverage/default/41.kmac_burst_write.2769655200
Short name	T301
Test name
Test status
Simulation time	6660306013 ps
CPU time	245.9 seconds
Started	Jan 10 12:52:21 PM PST 24
Finished	Jan 10 12:57:38 PM PST 24
Peak memory	240276 kb
Host	smart-5353c703-200c-4da1-9b4f-9d58db66c3dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2769655200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.2769655200 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_burst_write/latest

Test location	/workspace/coverage/default/41.kmac_entropy_refresh.2717789071
Short name	T14
Test name
Test status
Simulation time	6038446649 ps
CPU time	232.57 seconds
Started	Jan 10 12:52:19 PM PST 24
Finished	Jan 10 12:57:22 PM PST 24
Peak memory	246616 kb
Host	smart-7f05a0e6-df51-47b1-b2b1-c0ad9ddc6cf3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2717789071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.2717789071 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/41.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/41.kmac_error.2900159205
Short name	T706
Test name
Test status
Simulation time	4302691505 ps
CPU time	185.21 seconds
Started	Jan 10 12:52:25 PM PST 24
Finished	Jan 10 12:56:45 PM PST 24
Peak memory	252852 kb
Host	smart-78f989e1-c102-4129-8146-1f110c1833d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2900159205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.2900159205 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_error/latest

Test location	/workspace/coverage/default/41.kmac_key_error.1208494513
Short name	T23
Test name
Test status
Simulation time	4230475470 ps
CPU time	4.25 seconds
Started	Jan 10 12:52:44 PM PST 24
Finished	Jan 10 12:53:59 PM PST 24
Peak memory	219292 kb
Host	smart-af070a4c-d1eb-4a89-a398-5bf022594aa3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1208494513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.1208494513 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_key_error/latest

Test location	/workspace/coverage/default/41.kmac_lc_escalation.2872764402
Short name	T16
Test name
Test status
Simulation time	86701690 ps
CPU time	1.31 seconds
Started	Jan 10 12:52:24 PM PST 24
Finished	Jan 10 12:53:37 PM PST 24
Peak memory	220912 kb
Host	smart-d5c8d57b-9b18-416c-9bce-555e075a62fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2872764402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.2872764402 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/41.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/41.kmac_long_msg_and_output.3112547612
Short name	T278
Test name
Test status
Simulation time	338171533485 ps
CPU time	3192.67 seconds
Started	Jan 10 12:52:24 PM PST 24
Finished	Jan 10 01:46:49 PM PST 24
Peak memory	475300 kb
Host	smart-9c2d796b-dc15-44a0-a465-6a01d9741bd7
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112547612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a nd_output.3112547612 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/41.kmac_sideload.2035592800
Short name	T361
Test name
Test status
Simulation time	11194809929 ps
CPU time	348.98 seconds
Started	Jan 10 12:52:27 PM PST 24
Finished	Jan 10 12:59:28 PM PST 24
Peak memory	251448 kb
Host	smart-377cc312-d198-4eaa-a140-8f5b819ab8fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2035592800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.2035592800 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_sideload/latest

Test location	/workspace/coverage/default/41.kmac_smoke.130054012
Short name	T587
Test name
Test status
Simulation time	16789305583 ps
CPU time	76.29 seconds
Started	Jan 10 12:52:24 PM PST 24
Finished	Jan 10 12:55:02 PM PST 24
Peak memory	221204 kb
Host	smart-08d9d4b3-7735-466e-8311-e3901ed63e5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=130054012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.130054012 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_smoke/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_kmac.1417666902
Short name	T591
Test name
Test status
Simulation time	930218479 ps
CPU time	6.76 seconds
Started	Jan 10 12:52:47 PM PST 24
Finished	Jan 10 12:54:03 PM PST 24
Peak memory	219284 kb
Host	smart-8a00c567-5b55-46b1-8741-a13f456736d7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417666902 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 41.kmac_test_vectors_kmac.1417666902 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_kmac_xof.2183654535
Short name	T270
Test name
Test status
Simulation time	197061893 ps
CPU time	5.92 seconds
Started	Jan 10 12:52:30 PM PST 24
Finished	Jan 10 12:53:57 PM PST 24
Peak memory	219248 kb
Host	smart-780ccfaa-c9e1-49c2-a1ac-79791f6d861a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183654535 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_kmac_xof.2183654535 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_224.1024270539
Short name	T182
Test name
Test status
Simulation time	218341665483 ps
CPU time	2188.58 seconds
Started	Jan 10 12:52:30 PM PST 24
Finished	Jan 10 01:30:20 PM PST 24
Peak memory	402016 kb
Host	smart-1233e813-61a9-4324-b409-cbe41c63bdfb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1024270539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.1024270539 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_256.3181082224
Short name	T277
Test name
Test status
Simulation time	42345741787 ps
CPU time	1768.6 seconds
Started	Jan 10 12:52:22 PM PST 24
Finished	Jan 10 01:23:01 PM PST 24
Peak memory	394652 kb
Host	smart-64599319-2fa3-4115-b3ae-6bb9a075c082
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3181082224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.3181082224 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_384.2671850697
Short name	T449
Test name
Test status
Simulation time	697324687374 ps
CPU time	1785.57 seconds
Started	Jan 10 12:52:36 PM PST 24
Finished	Jan 10 01:23:42 PM PST 24
Peak memory	337512 kb
Host	smart-357927c9-a5ac-4af1-970b-167082515a09
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2671850697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.2671850697 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_512.1526111006
Short name	T1012
Test name
Test status
Simulation time	137521302501 ps
CPU time	1266.35 seconds
Started	Jan 10 12:52:26 PM PST 24
Finished	Jan 10 01:14:55 PM PST 24
Peak memory	307272 kb
Host	smart-201e5c4d-a1de-4a83-bebc-1de6cfca2dd4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1526111006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.1526111006 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_shake_128.3424068714
Short name	T985
Test name
Test status
Simulation time	62865722735 ps
CPU time	5212.62 seconds
Started	Jan 10 12:52:24 PM PST 24
Finished	Jan 10 02:20:28 PM PST 24
Peak memory	663956 kb
Host	smart-83af0d3d-590e-4c76-8dd5-84b883ba196c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3424068714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.3424068714 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_shake_256.1078942100
Short name	T603
Test name
Test status
Simulation time	640154573558 ps
CPU time	5019.38 seconds
Started	Jan 10 12:52:24 PM PST 24
Finished	Jan 10 02:17:15 PM PST 24
Peak memory	585384 kb
Host	smart-55f2c77e-8f88-4a35-843a-e0c33ad73926
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1078942100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.1078942100 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/42.kmac_alert_test.1385411073
Short name	T645
Test name
Test status
Simulation time	19738481 ps
CPU time	0.86 seconds
Started	Jan 10 12:52:25 PM PST 24
Finished	Jan 10 12:53:37 PM PST 24
Peak memory	220316 kb
Host	smart-ce934ead-576e-4e49-b9fa-9661f2a953e6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385411073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.1385411073 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_alert_test/latest

Test location	/workspace/coverage/default/42.kmac_app.3721928452
Short name	T689
Test name
Test status
Simulation time	7969760764 ps
CPU time	30.92 seconds
Started	Jan 10 12:52:26 PM PST 24
Finished	Jan 10 12:54:17 PM PST 24
Peak memory	226872 kb
Host	smart-bdffcbe2-f1b7-472f-8c89-b2dc28a5dc91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3721928452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.3721928452 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_app/latest

Test location	/workspace/coverage/default/42.kmac_burst_write.92478048
Short name	T100
Test name
Test status
Simulation time	10017208598 ps
CPU time	1035.27 seconds
Started	Jan 10 12:52:56 PM PST 24
Finished	Jan 10 01:11:23 PM PST 24
Peak memory	238764 kb
Host	smart-a07c871d-733c-4531-a9b6-031a21a8c8ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=92478048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.92478048 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_burst_write/latest

Test location	/workspace/coverage/default/42.kmac_entropy_refresh.951854794
Short name	T496
Test name
Test status
Simulation time	16536398028 ps
CPU time	417.57 seconds
Started	Jan 10 12:52:26 PM PST 24
Finished	Jan 10 01:00:45 PM PST 24
Peak memory	256996 kb
Host	smart-9c983fe0-76de-4868-9af8-c6bf0b67bf8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=951854794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.951854794 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/42.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/42.kmac_error.3177069697
Short name	T630
Test name
Test status
Simulation time	2756535768 ps
CPU time	219.9 seconds
Started	Jan 10 12:52:24 PM PST 24
Finished	Jan 10 12:57:15 PM PST 24
Peak memory	252948 kb
Host	smart-a1598b0c-1056-414a-865e-cea5b22c3032
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3177069697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.3177069697 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_error/latest

Test location	/workspace/coverage/default/42.kmac_key_error.1760327024
Short name	T915
Test name
Test status
Simulation time	443595905 ps
CPU time	2.05 seconds
Started	Jan 10 12:52:24 PM PST 24
Finished	Jan 10 12:53:41 PM PST 24
Peak memory	219272 kb
Host	smart-0b33fba6-6057-47cd-b9f1-f40328deff15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1760327024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.1760327024 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_key_error/latest

Test location	/workspace/coverage/default/42.kmac_lc_escalation.1675599948
Short name	T1099
Test name
Test status
Simulation time	858691488 ps
CPU time	14.44 seconds
Started	Jan 10 12:52:24 PM PST 24
Finished	Jan 10 12:53:54 PM PST 24
Peak memory	232204 kb
Host	smart-631b7b3a-9142-4ceb-af82-7760bb2c30e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1675599948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.1675599948 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/42.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/42.kmac_long_msg_and_output.471159798
Short name	T812
Test name
Test status
Simulation time	194832074771 ps
CPU time	1930.09 seconds
Started	Jan 10 12:52:26 PM PST 24
Finished	Jan 10 01:25:58 PM PST 24
Peak memory	381368 kb
Host	smart-5719402e-482a-481f-acd8-6aadc7c860bd
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471159798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_an d_output.471159798 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/42.kmac_sideload.3974720469
Short name	T1039
Test name
Test status
Simulation time	51500921212 ps
CPU time	455.26 seconds
Started	Jan 10 12:52:41 PM PST 24
Finished	Jan 10 01:01:26 PM PST 24
Peak memory	258192 kb
Host	smart-19936a0b-5f80-40b9-8e63-ffb76294b2bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3974720469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.3974720469 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_sideload/latest

Test location	/workspace/coverage/default/42.kmac_smoke.2029688121
Short name	T11
Test name
Test status
Simulation time	13251873127 ps
CPU time	67.16 seconds
Started	Jan 10 12:52:30 PM PST 24
Finished	Jan 10 12:54:59 PM PST 24
Peak memory	224988 kb
Host	smart-46b5eb57-e9c4-4f4b-ad99-725d886b6b82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029688121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.2029688121 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_smoke/latest

Test location	/workspace/coverage/default/42.kmac_stress_all.1067522374
Short name	T380
Test name
Test status
Simulation time	13477326365 ps
CPU time	323.8 seconds
Started	Jan 10 12:52:31 PM PST 24
Finished	Jan 10 12:59:05 PM PST 24
Peak memory	285088 kb
Host	smart-47f38cd6-b48e-4317-978a-85f7cdab818b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1067522374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.1067522374 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_stress_all/latest

Test location	/workspace/coverage/default/42.kmac_stress_all_with_rand_reset.1852219731
Short name	T1100
Test name
Test status
Simulation time	78368531211 ps
CPU time	2463.62 seconds
Started	Jan 10 12:52:30 PM PST 24
Finished	Jan 10 01:34:44 PM PST 24
Peak memory	341380 kb
Host	smart-2fbe3fa3-c8d1-49a8-8b1a-ba58b1cd46ac
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1852219731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all_with_rand_reset.1852219731 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_kmac.279999665
Short name	T870
Test name
Test status
Simulation time	235937760 ps
CPU time	6.29 seconds
Started	Jan 10 12:52:19 PM PST 24
Finished	Jan 10 12:53:40 PM PST 24
Peak memory	219312 kb
Host	smart-f1846868-2089-448f-ba59-d308f4d707ea
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279999665 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 42.kmac_test_vectors_kmac.279999665 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_kmac_xof.1054147136
Short name	T391
Test name
Test status
Simulation time	479234533 ps
CPU time	7.24 seconds
Started	Jan 10 12:52:24 PM PST 24
Finished	Jan 10 12:53:42 PM PST 24
Peak memory	220612 kb
Host	smart-eef830b5-0b4a-4555-9530-ed980907d5d6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054147136 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_kmac_xof.1054147136 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_224.2561710609
Short name	T648
Test name
Test status
Simulation time	62583603654 ps
CPU time	2061.46 seconds
Started	Jan 10 12:52:20 PM PST 24
Finished	Jan 10 01:28:08 PM PST 24
Peak memory	404852 kb
Host	smart-47f195a9-b9a5-40ed-87f4-66899586bb8f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2561710609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.2561710609 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_256.156299145
Short name	T872
Test name
Test status
Simulation time	350137440568 ps
CPU time	2057.32 seconds
Started	Jan 10 12:52:23 PM PST 24
Finished	Jan 10 01:27:54 PM PST 24
Peak memory	394680 kb
Host	smart-bb8a66cf-ec77-4f17-a552-165d0c8bc390
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=156299145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.156299145 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_384.2105669575
Short name	T731
Test name
Test status
Simulation time	98325860938 ps
CPU time	1695.94 seconds
Started	Jan 10 12:52:30 PM PST 24
Finished	Jan 10 01:21:57 PM PST 24
Peak memory	341356 kb
Host	smart-41457bb5-ec0d-44fe-a915-dd88e20bc7e7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2105669575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.2105669575 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_512.3341363908
Short name	T252
Test name
Test status
Simulation time	10801710033 ps
CPU time	1070.4 seconds
Started	Jan 10 12:52:23 PM PST 24
Finished	Jan 10 01:11:40 PM PST 24
Peak memory	300944 kb
Host	smart-97289153-412a-4c7d-bdd8-865f9f1bc997
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3341363908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.3341363908 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_shake_128.27715021
Short name	T447
Test name
Test status
Simulation time	757304197374 ps
CPU time	5066.45 seconds
Started	Jan 10 12:52:24 PM PST 24
Finished	Jan 10 02:18:12 PM PST 24
Peak memory	670396 kb
Host	smart-1819c36b-c90f-43b3-bbad-a2357ac201ec
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=27715021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.27715021 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_shake_256.47041052
Short name	T389
Test name
Test status
Simulation time	660306540049 ps
CPU time	4711.88 seconds
Started	Jan 10 12:52:21 PM PST 24
Finished	Jan 10 02:12:04 PM PST 24
Peak memory	584032 kb
Host	smart-c7ec9878-ef41-415a-81d4-698932d27b61
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=47041052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.47041052 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/43.kmac_alert_test.3793986058
Short name	T232
Test name
Test status
Simulation time	95529510 ps
CPU time	0.8 seconds
Started	Jan 10 12:52:45 PM PST 24
Finished	Jan 10 12:53:57 PM PST 24
Peak memory	218976 kb
Host	smart-ea8cec81-84df-45a9-9aaa-5d207c3d7ea8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793986058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.3793986058 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_alert_test/latest

Test location	/workspace/coverage/default/43.kmac_app.2186354498
Short name	T1023
Test name
Test status
Simulation time	28766970165 ps
CPU time	348.48 seconds
Started	Jan 10 12:52:43 PM PST 24
Finished	Jan 10 12:59:42 PM PST 24
Peak memory	251420 kb
Host	smart-4c891eda-6a62-44a0-8ed2-c5410545d3e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2186354498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.2186354498 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_app/latest

Test location	/workspace/coverage/default/43.kmac_burst_write.631990138
Short name	T933
Test name
Test status
Simulation time	106522538723 ps
CPU time	1232.08 seconds
Started	Jan 10 12:52:21 PM PST 24
Finished	Jan 10 01:14:05 PM PST 24
Peak memory	241792 kb
Host	smart-b76480c3-cdbc-46cc-afff-5440a59024f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=631990138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.631990138 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_burst_write/latest

Test location	/workspace/coverage/default/43.kmac_entropy_refresh.510681443
Short name	T939
Test name
Test status
Simulation time	80583464113 ps
CPU time	265.74 seconds
Started	Jan 10 12:52:39 PM PST 24
Finished	Jan 10 12:58:16 PM PST 24
Peak memory	246144 kb
Host	smart-fd9ccbf0-6423-4369-81f6-8daa188ce068
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=510681443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.510681443 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/43.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/43.kmac_error.2340912796
Short name	T987
Test name
Test status
Simulation time	13683287594 ps
CPU time	248.16 seconds
Started	Jan 10 12:52:36 PM PST 24
Finished	Jan 10 12:58:00 PM PST 24
Peak memory	253896 kb
Host	smart-486137ea-219b-4448-bfbf-4d41ef471a4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2340912796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.2340912796 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_error/latest

Test location	/workspace/coverage/default/43.kmac_key_error.406905134
Short name	T508
Test name
Test status
Simulation time	201145142 ps
CPU time	1.87 seconds
Started	Jan 10 12:52:53 PM PST 24
Finished	Jan 10 12:54:08 PM PST 24
Peak memory	219268 kb
Host	smart-bb290dd7-c8ac-4d72-a98e-8f4d7dda88b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=406905134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.406905134 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_key_error/latest

Test location	/workspace/coverage/default/43.kmac_lc_escalation.1559792968
Short name	T709
Test name
Test status
Simulation time	38126785 ps
CPU time	1.29 seconds
Started	Jan 10 12:52:46 PM PST 24
Finished	Jan 10 12:53:58 PM PST 24
Peak memory	220380 kb
Host	smart-e6098d29-b060-455d-9342-2dcdbac15dd6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1559792968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.1559792968 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/43.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/43.kmac_long_msg_and_output.3055411699
Short name	T912
Test name
Test status
Simulation time	24757204907 ps
CPU time	2626.77 seconds
Started	Jan 10 12:52:35 PM PST 24
Finished	Jan 10 01:37:33 PM PST 24
Peak memory	445500 kb
Host	smart-a5863298-209a-4820-9e51-6161d1c27967
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055411699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a nd_output.3055411699 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/43.kmac_sideload.1722822623
Short name	T717
Test name
Test status
Simulation time	4942608097 ps
CPU time	142.55 seconds
Started	Jan 10 12:52:27 PM PST 24
Finished	Jan 10 12:56:00 PM PST 24
Peak memory	238760 kb
Host	smart-425ce076-9880-410d-a8c7-928a945f0788
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1722822623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.1722822623 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_sideload/latest

Test location	/workspace/coverage/default/43.kmac_smoke.2877482824
Short name	T722
Test name
Test status
Simulation time	4010770885 ps
CPU time	79.84 seconds
Started	Jan 10 12:52:34 PM PST 24
Finished	Jan 10 12:55:09 PM PST 24
Peak memory	227420 kb
Host	smart-fb00d8b9-caad-4060-9eeb-d9d6bbf34e97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2877482824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.2877482824 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_smoke/latest

Test location	/workspace/coverage/default/43.kmac_stress_all.428057926
Short name	T546
Test name
Test status
Simulation time	3266994246 ps
CPU time	121.39 seconds
Started	Jan 10 12:52:23 PM PST 24
Finished	Jan 10 12:55:51 PM PST 24
Peak memory	243832 kb
Host	smart-c21340ec-0472-4517-b4c4-562a70f5c3ae
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=428057926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.428057926 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_stress_all/latest

Test location	/workspace/coverage/default/43.kmac_stress_all_with_rand_reset.1153300787
Short name	T620
Test name
Test status
Simulation time	54141165257 ps
CPU time	2148.21 seconds
Started	Jan 10 12:52:43 PM PST 24
Finished	Jan 10 01:29:52 PM PST 24
Peak memory	343696 kb
Host	smart-09470a61-d722-4795-ac2b-0ac0e6a5458b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1153300787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all_with_rand_reset.1153300787 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_kmac.3062491810
Short name	T269
Test name
Test status
Simulation time	454591295 ps
CPU time	5.44 seconds
Started	Jan 10 12:52:31 PM PST 24
Finished	Jan 10 12:53:47 PM PST 24
Peak memory	220680 kb
Host	smart-053c2cfa-283c-41a9-8a4f-b36f26daddde
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062491810 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 43.kmac_test_vectors_kmac.3062491810 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_kmac_xof.708295615
Short name	T418
Test name
Test status
Simulation time	185555579 ps
CPU time	4.99 seconds
Started	Jan 10 12:52:22 PM PST 24
Finished	Jan 10 12:53:37 PM PST 24
Peak memory	220600 kb
Host	smart-b7032362-4b7b-4e4b-a08a-e21b29dbce54
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708295615 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 43.kmac_test_vectors_kmac_xof.708295615 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_224.3906204808
Short name	T839
Test name
Test status
Simulation time	433430826879 ps
CPU time	2058.93 seconds
Started	Jan 10 12:52:24 PM PST 24
Finished	Jan 10 01:27:58 PM PST 24
Peak memory	394960 kb
Host	smart-f5e37279-96a7-4af8-84ba-40a291bcbb66
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3906204808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.3906204808 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_256.2735017940
Short name	T1061
Test name
Test status
Simulation time	385358253198 ps
CPU time	2012.81 seconds
Started	Jan 10 12:52:36 PM PST 24
Finished	Jan 10 01:27:20 PM PST 24
Peak memory	380268 kb
Host	smart-994adace-ae7c-4dc3-8474-2967351b2e78
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2735017940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.2735017940 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_384.115985937
Short name	T87
Test name
Test status
Simulation time	246615930059 ps
CPU time	1706.4 seconds
Started	Jan 10 12:53:03 PM PST 24
Finished	Jan 10 01:22:43 PM PST 24
Peak memory	343588 kb
Host	smart-af745396-5657-4246-89b9-46ff7a0c455a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=115985937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.115985937 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_512.3279135359
Short name	T198
Test name
Test status
Simulation time	10879171817 ps
CPU time	1094.29 seconds
Started	Jan 10 12:52:23 PM PST 24
Finished	Jan 10 01:11:51 PM PST 24
Peak memory	302656 kb
Host	smart-6a02bf76-59d4-4e50-a2da-aadb9a5ac900
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3279135359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.3279135359 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_shake_128.384191028
Short name	T437
Test name
Test status
Simulation time	88190023164 ps
CPU time	5106.84 seconds
Started	Jan 10 12:52:30 PM PST 24
Finished	Jan 10 02:18:52 PM PST 24
Peak memory	665184 kb
Host	smart-599c0ca3-9445-4e5e-880e-cab0b39a665e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=384191028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.384191028 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_shake_256.1680794589
Short name	T387
Test name
Test status
Simulation time	617099458540 ps
CPU time	6266.49 seconds
Started	Jan 10 12:52:34 PM PST 24
Finished	Jan 10 02:38:11 PM PST 24
Peak memory	567808 kb
Host	smart-9bd3adcc-8fb6-4cd4-8fd4-5cb738607905
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1680794589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.1680794589 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/44.kmac_alert_test.2959928511
Short name	T297
Test name
Test status
Simulation time	78601117 ps
CPU time	0.79 seconds
Started	Jan 10 12:52:42 PM PST 24
Finished	Jan 10 12:53:58 PM PST 24
Peak memory	220260 kb
Host	smart-a56efaf3-d7ec-4879-8a4e-dbb151ee0472
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959928511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.2959928511 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_alert_test/latest

Test location	/workspace/coverage/default/44.kmac_app.3445948834
Short name	T403
Test name
Test status
Simulation time	3888696654 ps
CPU time	210.93 seconds
Started	Jan 10 12:52:40 PM PST 24
Finished	Jan 10 12:57:21 PM PST 24
Peak memory	246756 kb
Host	smart-f13dd820-8f3c-4cd5-97d0-8d8f84ddaa56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3445948834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.3445948834 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_app/latest

Test location	/workspace/coverage/default/44.kmac_burst_write.4122139531
Short name	T555
Test name
Test status
Simulation time	47014140875 ps
CPU time	1017.73 seconds
Started	Jan 10 12:52:45 PM PST 24
Finished	Jan 10 01:11:01 PM PST 24
Peak memory	240356 kb
Host	smart-69d6c415-9bb6-43bd-a093-10686cc8fd66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4122139531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.4122139531 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_burst_write/latest

Test location	/workspace/coverage/default/44.kmac_entropy_refresh.540657929
Short name	T462
Test name
Test status
Simulation time	25952865445 ps
CPU time	143.35 seconds
Started	Jan 10 12:53:22 PM PST 24
Finished	Jan 10 12:56:57 PM PST 24
Peak memory	243896 kb
Host	smart-71aba810-4509-4c0b-bf2b-6243b5e6d703
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=540657929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.540657929 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/44.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/44.kmac_error.3358556158
Short name	T336
Test name
Test status
Simulation time	85194492762 ps
CPU time	545.73 seconds
Started	Jan 10 12:52:46 PM PST 24
Finished	Jan 10 01:03:02 PM PST 24
Peak memory	272896 kb
Host	smart-217906b8-6c59-49a8-bfa2-54867c4ed4e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3358556158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.3358556158 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_error/latest

Test location	/workspace/coverage/default/44.kmac_key_error.2364238956
Short name	T108
Test name
Test status
Simulation time	61643851 ps
CPU time	1.1 seconds
Started	Jan 10 12:52:36 PM PST 24
Finished	Jan 10 12:53:58 PM PST 24
Peak memory	219064 kb
Host	smart-95ced67a-913a-4b5e-a447-6f214a9dfd38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2364238956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.2364238956 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_key_error/latest

Test location	/workspace/coverage/default/44.kmac_lc_escalation.362764972
Short name	T913
Test name
Test status
Simulation time	52073320 ps
CPU time	1.42 seconds
Started	Jan 10 12:52:39 PM PST 24
Finished	Jan 10 12:53:59 PM PST 24
Peak memory	220320 kb
Host	smart-52bdbaa4-f6f9-44b8-999f-1a8eedf24639
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=362764972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.362764972 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/44.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/44.kmac_long_msg_and_output.1769157535
Short name	T562
Test name
Test status
Simulation time	8623212841 ps
CPU time	855.84 seconds
Started	Jan 10 12:52:36 PM PST 24
Finished	Jan 10 01:08:03 PM PST 24
Peak memory	301404 kb
Host	smart-d6b7fe2b-26c1-4196-8744-26bfd152e965
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769157535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a nd_output.1769157535 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/44.kmac_sideload.3584153179
Short name	T704
Test name
Test status
Simulation time	10908105024 ps
CPU time	352.82 seconds
Started	Jan 10 12:52:30 PM PST 24
Finished	Jan 10 12:59:43 PM PST 24
Peak memory	253164 kb
Host	smart-01debc59-e473-4455-9bc8-4ae19617ba97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3584153179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.3584153179 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_sideload/latest

Test location	/workspace/coverage/default/44.kmac_smoke.2443842763
Short name	T463
Test name
Test status
Simulation time	3752259286 ps
CPU time	75.54 seconds
Started	Jan 10 12:52:22 PM PST 24
Finished	Jan 10 12:54:52 PM PST 24
Peak memory	227520 kb
Host	smart-533e96d7-5294-4d38-b159-e55a4fde021d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2443842763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.2443842763 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_smoke/latest

Test location	/workspace/coverage/default/44.kmac_stress_all.3834664265
Short name	T80
Test name
Test status
Simulation time	7935516580 ps
CPU time	706.52 seconds
Started	Jan 10 12:52:30 PM PST 24
Finished	Jan 10 01:05:27 PM PST 24
Peak memory	293120 kb
Host	smart-62edcba0-b54d-43e4-a54b-6f3772ca130e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3834664265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.3834664265 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_stress_all/latest

Test location	/workspace/coverage/default/44.kmac_stress_all_with_rand_reset.1946779518
Short name	T1071
Test name
Test status
Simulation time	27113105194 ps
CPU time	503.61 seconds
Started	Jan 10 12:52:30 PM PST 24
Finished	Jan 10 01:02:04 PM PST 24
Peak memory	270120 kb
Host	smart-c1aaa4c9-f61e-42ee-ac98-2a0af7dd0426
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1946779518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all_with_rand_reset.1946779518 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_kmac.920125283
Short name	T494
Test name
Test status
Simulation time	110756015 ps
CPU time	5.82 seconds
Started	Jan 10 12:52:35 PM PST 24
Finished	Jan 10 12:53:55 PM PST 24
Peak memory	219392 kb
Host	smart-ad810fc3-3c1f-42f5-bda1-8821607958c6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920125283 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 44.kmac_test_vectors_kmac.920125283 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_kmac_xof.3161476413
Short name	T860
Test name
Test status
Simulation time	102687693 ps
CPU time	5.28 seconds
Started	Jan 10 12:52:33 PM PST 24
Finished	Jan 10 12:53:50 PM PST 24
Peak memory	219308 kb
Host	smart-ab61e938-773d-4df5-a3c6-12f435f7ce71
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161476413 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_kmac_xof.3161476413 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_224.4246688054
Short name	T280
Test name
Test status
Simulation time	479709521321 ps
CPU time	2387.82 seconds
Started	Jan 10 12:52:43 PM PST 24
Finished	Jan 10 01:33:41 PM PST 24
Peak memory	394076 kb
Host	smart-7fc78f6b-5404-4b6c-a5da-b4fa8c1c6cb4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4246688054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.4246688054 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_256.1485376689
Short name	T264
Test name
Test status
Simulation time	241932587743 ps
CPU time	2288.62 seconds
Started	Jan 10 12:52:33 PM PST 24
Finished	Jan 10 01:31:59 PM PST 24
Peak memory	381108 kb
Host	smart-7fc673e0-b022-4894-a766-080fdf663e79
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1485376689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.1485376689 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_384.2420421567
Short name	T316
Test name
Test status
Simulation time	199119916497 ps
CPU time	1612.07 seconds
Started	Jan 10 12:52:33 PM PST 24
Finished	Jan 10 01:20:47 PM PST 24
Peak memory	342588 kb
Host	smart-3523c60f-47c4-4906-8937-0e1426ca4158
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2420421567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.2420421567 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_512.2379425800
Short name	T624
Test name
Test status
Simulation time	410050493594 ps
CPU time	1327.35 seconds
Started	Jan 10 12:53:14 PM PST 24
Finished	Jan 10 01:16:34 PM PST 24
Peak memory	300492 kb
Host	smart-b62626ce-2ec6-4f77-b7a4-8c35764a2fa9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2379425800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.2379425800 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_shake_128.552454128
Short name	T341
Test name
Test status
Simulation time	290279449246 ps
CPU time	5926.81 seconds
Started	Jan 10 12:52:40 PM PST 24
Finished	Jan 10 02:32:39 PM PST 24
Peak memory	653744 kb
Host	smart-397ed94d-a06c-425c-bdcc-a69ec30ad0f0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=552454128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.552454128 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_shake_256.2107717640
Short name	T529
Test name
Test status
Simulation time	150617192091 ps
CPU time	4851.99 seconds
Started	Jan 10 12:52:32 PM PST 24
Finished	Jan 10 02:14:39 PM PST 24
Peak memory	555384 kb
Host	smart-7a08e42e-7a2a-4ddb-9f2e-65b63493e011
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2107717640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.2107717640 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/45.kmac_alert_test.556028275
Short name	T402
Test name
Test status
Simulation time	74623626 ps
CPU time	0.89 seconds
Started	Jan 10 12:53:13 PM PST 24
Finished	Jan 10 12:54:27 PM PST 24
Peak memory	220264 kb
Host	smart-2c1377fd-3905-4c64-a7ac-82eb41a79669
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556028275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.556028275 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_alert_test/latest

Test location	/workspace/coverage/default/45.kmac_app.2869397480
Short name	T286
Test name
Test status
Simulation time	4650463061 ps
CPU time	90.21 seconds
Started	Jan 10 12:53:01 PM PST 24
Finished	Jan 10 12:55:43 PM PST 24
Peak memory	234484 kb
Host	smart-c5cbcd7a-66c1-40e8-88d6-4b2dfdaced85
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2869397480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2869397480 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_app/latest

Test location	/workspace/coverage/default/45.kmac_burst_write.233167914
Short name	T917
Test name
Test status
Simulation time	16936801270 ps
CPU time	269.99 seconds
Started	Jan 10 12:52:43 PM PST 24
Finished	Jan 10 12:58:23 PM PST 24
Peak memory	240012 kb
Host	smart-726ded70-07e9-4d4f-94f3-18e506e85d0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=233167914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.233167914 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_burst_write/latest

Test location	/workspace/coverage/default/45.kmac_entropy_refresh.241383713
Short name	T856
Test name
Test status
Simulation time	28225733603 ps
CPU time	357.86 seconds
Started	Jan 10 12:53:02 PM PST 24
Finished	Jan 10 01:00:11 PM PST 24
Peak memory	252272 kb
Host	smart-a188c614-bbfc-4783-b88d-072717004c07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=241383713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.241383713 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/45.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/45.kmac_error.446916860
Short name	T567
Test name
Test status
Simulation time	5958195038 ps
CPU time	52.2 seconds
Started	Jan 10 12:52:43 PM PST 24
Finished	Jan 10 12:54:45 PM PST 24
Peak memory	238564 kb
Host	smart-3ae44e85-d4a7-4e24-8f82-4f45fe2585f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=446916860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.446916860 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_error/latest

Test location	/workspace/coverage/default/45.kmac_key_error.3408838904
Short name	T723
Test name
Test status
Simulation time	1208725499 ps
CPU time	3.81 seconds
Started	Jan 10 12:53:17 PM PST 24
Finished	Jan 10 12:54:34 PM PST 24
Peak memory	219172 kb
Host	smart-dc6874a2-cb7d-494b-a56e-c385c8a48103
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3408838904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.3408838904 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_key_error/latest

Test location	/workspace/coverage/default/45.kmac_lc_escalation.1929138762
Short name	T682
Test name
Test status
Simulation time	99828206 ps
CPU time	1.4 seconds
Started	Jan 10 12:52:28 PM PST 24
Finished	Jan 10 12:53:44 PM PST 24
Peak memory	220352 kb
Host	smart-13ce4b0c-a55a-4331-ba27-00c75b7e5c46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1929138762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.1929138762 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/45.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/45.kmac_long_msg_and_output.2472272882
Short name	T953
Test name
Test status
Simulation time	13897003157 ps
CPU time	237.95 seconds
Started	Jan 10 12:52:45 PM PST 24
Finished	Jan 10 12:58:06 PM PST 24
Peak memory	247148 kb
Host	smart-1765ffd3-9109-4306-b58c-041eb90c7ec0
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472272882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a nd_output.2472272882 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/45.kmac_sideload.1799138215
Short name	T819
Test name
Test status
Simulation time	707244983 ps
CPU time	54.89 seconds
Started	Jan 10 12:52:43 PM PST 24
Finished	Jan 10 12:54:47 PM PST 24
Peak memory	229464 kb
Host	smart-f75e8acc-c111-4051-9d6d-628e0dc707f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1799138215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.1799138215 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_sideload/latest

Test location	/workspace/coverage/default/45.kmac_smoke.340470438
Short name	T489
Test name
Test status
Simulation time	7411515436 ps
CPU time	68.49 seconds
Started	Jan 10 12:52:43 PM PST 24
Finished	Jan 10 12:55:01 PM PST 24
Peak memory	227468 kb
Host	smart-ebb703d5-be88-4859-8db1-80da1b82154e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=340470438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.340470438 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_smoke/latest

Test location	/workspace/coverage/default/45.kmac_stress_all.857548644
Short name	T796
Test name
Test status
Simulation time	223732077495 ps
CPU time	758.77 seconds
Started	Jan 10 12:52:27 PM PST 24
Finished	Jan 10 01:06:16 PM PST 24
Peak memory	303116 kb
Host	smart-5cde1b24-6333-4704-a9f1-9580d673f572
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=857548644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.857548644 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_stress_all/latest

Test location	/workspace/coverage/default/45.kmac_stress_all_with_rand_reset.1197084949
Short name	T1064
Test name
Test status
Simulation time	374442880206 ps
CPU time	2281.18 seconds
Started	Jan 10 12:52:48 PM PST 24
Finished	Jan 10 01:32:01 PM PST 24
Peak memory	390708 kb
Host	smart-29b14da9-1ed9-4f2c-b3bc-e8567bf3e368
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1197084949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all_with_rand_reset.1197084949 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_kmac.747225340
Short name	T765
Test name
Test status
Simulation time	249177576 ps
CPU time	6.57 seconds
Started	Jan 10 12:52:40 PM PST 24
Finished	Jan 10 12:54:00 PM PST 24
Peak memory	220736 kb
Host	smart-cf4bfd40-04b7-4261-90e1-46dda2ebf715
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747225340 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 45.kmac_test_vectors_kmac.747225340 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_kmac_xof.3224371417
Short name	T214
Test name
Test status
Simulation time	462449538 ps
CPU time	5.32 seconds
Started	Jan 10 12:52:30 PM PST 24
Finished	Jan 10 12:53:57 PM PST 24
Peak memory	219372 kb
Host	smart-58d5cf6f-ed3c-4ef2-97ce-ae08a834bcec
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224371417 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_kmac_xof.3224371417 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_224.2207788839
Short name	T226
Test name
Test status
Simulation time	253358378579 ps
CPU time	2138.52 seconds
Started	Jan 10 12:52:33 PM PST 24
Finished	Jan 10 01:29:23 PM PST 24
Peak memory	402184 kb
Host	smart-b0d8eb2a-728b-4164-8432-a439970c4d22
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2207788839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.2207788839 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_256.530108064
Short name	T283
Test name
Test status
Simulation time	122833140658 ps
CPU time	2050.96 seconds
Started	Jan 10 12:52:34 PM PST 24
Finished	Jan 10 01:27:55 PM PST 24
Peak memory	380132 kb
Host	smart-229ad0ba-5ce1-400f-81ca-febaa70b3c92
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=530108064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.530108064 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_384.2575282677
Short name	T481
Test name
Test status
Simulation time	617272438014 ps
CPU time	1753.55 seconds
Started	Jan 10 12:52:52 PM PST 24
Finished	Jan 10 01:23:17 PM PST 24
Peak memory	344096 kb
Host	smart-ef47fd40-eee3-4e31-8fd2-89c856a5e6a7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2575282677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.2575282677 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_512.530685961
Short name	T509
Test name
Test status
Simulation time	35503971228 ps
CPU time	1205.55 seconds
Started	Jan 10 12:52:35 PM PST 24
Finished	Jan 10 01:13:51 PM PST 24
Peak memory	301812 kb
Host	smart-819616e9-c7e5-4076-a826-47d81d22536b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=530685961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.530685961 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_shake_128.3501148108
Short name	T315
Test name
Test status
Simulation time	182694089384 ps
CPU time	5505.69 seconds
Started	Jan 10 12:53:19 PM PST 24
Finished	Jan 10 02:26:18 PM PST 24
Peak memory	670056 kb
Host	smart-2d5c6373-72ea-41d8-8912-16625e28ace2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3501148108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.3501148108 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_shake_256.364874518
Short name	T940
Test name
Test status
Simulation time	215280728698 ps
CPU time	4277.42 seconds
Started	Jan 10 12:52:31 PM PST 24
Finished	Jan 10 02:04:59 PM PST 24
Peak memory	563428 kb
Host	smart-70913207-356a-4c7c-8e3d-6378d4103d34
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=364874518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.364874518 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/46.kmac_alert_test.2954515924
Short name	T725
Test name
Test status
Simulation time	22114004 ps
CPU time	0.87 seconds
Started	Jan 10 12:52:37 PM PST 24
Finished	Jan 10 12:53:48 PM PST 24
Peak memory	218976 kb
Host	smart-6797ae40-fa2a-49d7-9fd9-9ae40d4a3bd0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954515924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.2954515924 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_alert_test/latest

Test location	/workspace/coverage/default/46.kmac_app.1133754362
Short name	T41
Test name
Test status
Simulation time	2701980287 ps
CPU time	25.53 seconds
Started	Jan 10 12:52:36 PM PST 24
Finished	Jan 10 12:54:18 PM PST 24
Peak memory	225704 kb
Host	smart-d0fbd62d-1406-4f48-b43e-d28403ee6137
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1133754362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.1133754362 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_app/latest

Test location	/workspace/coverage/default/46.kmac_entropy_refresh.1797060800
Short name	T76
Test name
Test status
Simulation time	9043601078 ps
CPU time	67.55 seconds
Started	Jan 10 12:52:40 PM PST 24
Finished	Jan 10 12:54:59 PM PST 24
Peak memory	232948 kb
Host	smart-3421da6a-b294-4b93-8b51-60ca64fcf5fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1797060800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.1797060800 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/46.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/46.kmac_error.869673229
Short name	T455
Test name
Test status
Simulation time	84924731986 ps
CPU time	261.17 seconds
Started	Jan 10 12:52:35 PM PST 24
Finished	Jan 10 12:58:07 PM PST 24
Peak memory	260176 kb
Host	smart-5fcf6f94-00a6-49d8-917e-8102102ae80f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=869673229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.869673229 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_error/latest

Test location	/workspace/coverage/default/46.kmac_key_error.1845587
Short name	T922
Test name
Test status
Simulation time	6642750279 ps
CPU time	5.05 seconds
Started	Jan 10 12:52:30 PM PST 24
Finished	Jan 10 12:53:56 PM PST 24
Peak memory	219344 kb
Host	smart-2c2435ab-90c8-4882-a740-d2e023d4f922
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1845587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.1845587 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_key_error/latest

Test location	/workspace/coverage/default/46.kmac_lc_escalation.2384572883
Short name	T691
Test name
Test status
Simulation time	7645612711 ps
CPU time	19.45 seconds
Started	Jan 10 12:52:40 PM PST 24
Finished	Jan 10 12:54:12 PM PST 24
Peak memory	244032 kb
Host	smart-d846695e-c59b-4d96-bb86-9d68a678ef55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2384572883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.2384572883 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/46.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/46.kmac_long_msg_and_output.1058659756
Short name	T1075
Test name
Test status
Simulation time	93176824007 ps
CPU time	2457.63 seconds
Started	Jan 10 12:52:27 PM PST 24
Finished	Jan 10 01:34:46 PM PST 24
Peak memory	408136 kb
Host	smart-e079b54f-1904-44e3-acc7-21d236cd9023
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058659756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a nd_output.1058659756 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/46.kmac_sideload.2943581139
Short name	T974
Test name
Test status
Simulation time	12651226164 ps
CPU time	336.96 seconds
Started	Jan 10 12:52:40 PM PST 24
Finished	Jan 10 12:59:27 PM PST 24
Peak memory	251108 kb
Host	smart-edac741c-76c7-42bc-9ac7-7c081e79318c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2943581139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.2943581139 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_sideload/latest

Test location	/workspace/coverage/default/46.kmac_smoke.105648719
Short name	T1037
Test name
Test status
Simulation time	7945762057 ps
CPU time	80.51 seconds
Started	Jan 10 12:52:36 PM PST 24
Finished	Jan 10 12:55:07 PM PST 24
Peak memory	225340 kb
Host	smart-266f01c0-da06-4663-804c-ade86bb365af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=105648719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.105648719 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_smoke/latest

Test location	/workspace/coverage/default/46.kmac_stress_all.2077858709
Short name	T46
Test name
Test status
Simulation time	226638012450 ps
CPU time	1203.38 seconds
Started	Jan 10 12:52:52 PM PST 24
Finished	Jan 10 01:14:08 PM PST 24
Peak memory	357632 kb
Host	smart-7ad85756-83fa-4472-b610-beea912d7490
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2077858709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.2077858709 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_stress_all/latest

Test location	/workspace/coverage/default/46.kmac_stress_all_with_rand_reset.4084017130
Short name	T604
Test name
Test status
Simulation time	54306606635 ps
CPU time	847.44 seconds
Started	Jan 10 12:52:40 PM PST 24
Finished	Jan 10 01:07:58 PM PST 24
Peak memory	285628 kb
Host	smart-cf1e567f-b0c0-4f63-bd84-e5b1c34258e8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4084017130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all_with_rand_reset.4084017130 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_kmac.2647313441
Short name	T854
Test name
Test status
Simulation time	2806331501 ps
CPU time	6.59 seconds
Started	Jan 10 12:52:55 PM PST 24
Finished	Jan 10 12:54:13 PM PST 24
Peak memory	219352 kb
Host	smart-5be5d042-9a12-48ee-9bd1-26f35314ac67
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647313441 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 46.kmac_test_vectors_kmac.2647313441 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_kmac_xof.2146798911
Short name	T451
Test name
Test status
Simulation time	113416867 ps
CPU time	5.61 seconds
Started	Jan 10 12:52:34 PM PST 24
Finished	Jan 10 12:53:51 PM PST 24
Peak memory	219196 kb
Host	smart-82820829-26a4-4d18-8417-2647294e9818
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146798911 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_kmac_xof.2146798911 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_224.896584491
Short name	T739
Test name
Test status
Simulation time	183633406343 ps
CPU time	2399.79 seconds
Started	Jan 10 12:53:11 PM PST 24
Finished	Jan 10 01:34:22 PM PST 24
Peak memory	394152 kb
Host	smart-310a8ea5-c447-4e79-a983-f5249ba7f1ab
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=896584491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.896584491 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_256.1029105585
Short name	T931
Test name
Test status
Simulation time	82529077597 ps
CPU time	1888.92 seconds
Started	Jan 10 12:52:30 PM PST 24
Finished	Jan 10 01:25:10 PM PST 24
Peak memory	378668 kb
Host	smart-58f5a05e-c269-4db2-9e7a-d9dfc9c5acd2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1029105585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.1029105585 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_384.2060924406
Short name	T895
Test name
Test status
Simulation time	291146009919 ps
CPU time	1715.74 seconds
Started	Jan 10 12:52:33 PM PST 24
Finished	Jan 10 01:22:20 PM PST 24
Peak memory	339504 kb
Host	smart-3e51597b-0813-4e51-9702-a9b3f85ffa59
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2060924406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.2060924406 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_512.2997562649
Short name	T776
Test name
Test status
Simulation time	172536612327 ps
CPU time	1241.78 seconds
Started	Jan 10 12:52:32 PM PST 24
Finished	Jan 10 01:14:24 PM PST 24
Peak memory	304544 kb
Host	smart-eb75020c-67ce-402b-af37-56c2f3f34493
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2997562649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.2997562649 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_shake_128.3242621155
Short name	T426
Test name
Test status
Simulation time	463226217221 ps
CPU time	5848.45 seconds
Started	Jan 10 12:52:30 PM PST 24
Finished	Jan 10 02:31:20 PM PST 24
Peak memory	659976 kb
Host	smart-da37eecb-223a-420b-b1f3-0eb2c4e7e3fa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3242621155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.3242621155 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_shake_256.842779019
Short name	T1051
Test name
Test status
Simulation time	218306830919 ps
CPU time	4364.34 seconds
Started	Jan 10 12:52:46 PM PST 24
Finished	Jan 10 02:06:40 PM PST 24
Peak memory	572432 kb
Host	smart-6d6417a5-5522-4234-9250-f5a5b2d3269b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=842779019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.842779019 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/47.kmac_alert_test.2343422787
Short name	T393
Test name
Test status
Simulation time	22557122 ps
CPU time	0.82 seconds
Started	Jan 10 12:52:45 PM PST 24
Finished	Jan 10 12:53:56 PM PST 24
Peak memory	219148 kb
Host	smart-9945a45f-ca79-4172-a93f-ee35ff9b3216
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343422787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.2343422787 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_alert_test/latest

Test location	/workspace/coverage/default/47.kmac_app.4238880874
Short name	T934
Test name
Test status
Simulation time	20724938606 ps
CPU time	144.93 seconds
Started	Jan 10 12:52:58 PM PST 24
Finished	Jan 10 12:56:34 PM PST 24
Peak memory	239228 kb
Host	smart-c7a55ce7-41a5-4266-8e4b-be48d08b6adc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4238880874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.4238880874 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_app/latest

Test location	/workspace/coverage/default/47.kmac_burst_write.1054295630
Short name	T531
Test name
Test status
Simulation time	2337205744 ps
CPU time	117.03 seconds
Started	Jan 10 12:52:38 PM PST 24
Finished	Jan 10 12:55:56 PM PST 24
Peak memory	237012 kb
Host	smart-964c8a65-121d-4f09-96bc-4fb45a47c788
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1054295630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.1054295630 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_burst_write/latest

Test location	/workspace/coverage/default/47.kmac_entropy_refresh.3832081547
Short name	T955
Test name
Test status
Simulation time	4871190545 ps
CPU time	196.46 seconds
Started	Jan 10 12:52:39 PM PST 24
Finished	Jan 10 12:57:06 PM PST 24
Peak memory	243556 kb
Host	smart-854aba4d-4a12-411f-bf17-06bcbf8b82aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3832081547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.3832081547 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/47.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/47.kmac_error.2590518405
Short name	T520
Test name
Test status
Simulation time	11764483427 ps
CPU time	228.78 seconds
Started	Jan 10 12:52:43 PM PST 24
Finished	Jan 10 12:57:44 PM PST 24
Peak memory	260388 kb
Host	smart-77a2bd9e-b5cf-4fdf-8c4f-a3ab77b636f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2590518405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.2590518405 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_error/latest

Test location	/workspace/coverage/default/47.kmac_key_error.3205350385
Short name	T613
Test name
Test status
Simulation time	3980808586 ps
CPU time	6.77 seconds
Started	Jan 10 12:52:46 PM PST 24
Finished	Jan 10 12:54:03 PM PST 24
Peak memory	219320 kb
Host	smart-36cc4098-9453-4d36-b6b8-3cce08b6c84f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3205350385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.3205350385 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_key_error/latest

Test location	/workspace/coverage/default/47.kmac_lc_escalation.3159652267
Short name	T551
Test name
Test status
Simulation time	87110584 ps
CPU time	1.45 seconds
Started	Jan 10 12:52:48 PM PST 24
Finished	Jan 10 12:54:00 PM PST 24
Peak memory	220400 kb
Host	smart-4302409d-1ada-453e-ba37-8d88b5371e68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3159652267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.3159652267 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/47.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/47.kmac_long_msg_and_output.994855216
Short name	T1010
Test name
Test status
Simulation time	113078774023 ps
CPU time	2753.62 seconds
Started	Jan 10 12:53:05 PM PST 24
Finished	Jan 10 01:40:13 PM PST 24
Peak memory	489672 kb
Host	smart-e299864f-3bde-4ce6-a60b-25fe70bf3d92
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994855216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_an d_output.994855216 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/47.kmac_sideload.4017935147
Short name	T941
Test name
Test status
Simulation time	5651313484 ps
CPU time	483.25 seconds
Started	Jan 10 12:52:29 PM PST 24
Finished	Jan 10 01:01:46 PM PST 24
Peak memory	260032 kb
Host	smart-6e80bd14-f4d1-43d5-96c0-a159eddb8532
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4017935147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.4017935147 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_sideload/latest

Test location	/workspace/coverage/default/47.kmac_smoke.1748182987
Short name	T160
Test name
Test status
Simulation time	1227211495 ps
CPU time	30.85 seconds
Started	Jan 10 12:52:37 PM PST 24
Finished	Jan 10 12:54:20 PM PST 24
Peak memory	227248 kb
Host	smart-fa9c1ca7-ff3e-47b6-8bf6-f27d8e0a78be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1748182987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.1748182987 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_smoke/latest

Test location	/workspace/coverage/default/47.kmac_stress_all.3532964764
Short name	T480
Test name
Test status
Simulation time	54245100390 ps
CPU time	512.01 seconds
Started	Jan 10 12:52:40 PM PST 24
Finished	Jan 10 01:02:23 PM PST 24
Peak memory	261388 kb
Host	smart-a8ae5666-1306-46dd-952a-1727a4678a21
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3532964764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.3532964764 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_stress_all/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_kmac.3386292458
Short name	T428
Test name
Test status
Simulation time	279136763 ps
CPU time	5.6 seconds
Started	Jan 10 12:52:42 PM PST 24
Finished	Jan 10 12:53:59 PM PST 24
Peak memory	220736 kb
Host	smart-4cae70e9-4738-4edd-96d6-35f0fd3804d3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386292458 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 47.kmac_test_vectors_kmac.3386292458 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_kmac_xof.4262509321
Short name	T886
Test name
Test status
Simulation time	3206031031 ps
CPU time	6.69 seconds
Started	Jan 10 12:52:36 PM PST 24
Finished	Jan 10 12:53:54 PM PST 24
Peak memory	220892 kb
Host	smart-e34210ab-d171-4f52-ad69-90b521068fdf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262509321 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_kmac_xof.4262509321 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_224.3886818510
Short name	T798
Test name
Test status
Simulation time	41676499656 ps
CPU time	1930.57 seconds
Started	Jan 10 12:52:54 PM PST 24
Finished	Jan 10 01:26:17 PM PST 24
Peak memory	397560 kb
Host	smart-7c1c2623-9d40-4e92-8b6b-43b960252df4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3886818510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.3886818510 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_256.3750174040
Short name	T320
Test name
Test status
Simulation time	186589073273 ps
CPU time	2119.42 seconds
Started	Jan 10 12:52:50 PM PST 24
Finished	Jan 10 01:29:19 PM PST 24
Peak memory	398808 kb
Host	smart-ed5d5ad3-fef6-4905-a2bb-280ecaf98222
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3750174040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.3750174040 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_384.4189511344
Short name	T550
Test name
Test status
Simulation time	17360786738 ps
CPU time	1394.1 seconds
Started	Jan 10 12:52:49 PM PST 24
Finished	Jan 10 01:17:13 PM PST 24
Peak memory	335636 kb
Host	smart-dcf8eb1c-df3a-4cbc-b50e-c2a07bf06a5d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4189511344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.4189511344 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_512.1360534813
Short name	T506
Test name
Test status
Simulation time	323448360335 ps
CPU time	1266.84 seconds
Started	Jan 10 12:52:34 PM PST 24
Finished	Jan 10 01:14:52 PM PST 24
Peak memory	300720 kb
Host	smart-601c8f03-00d4-4dcd-9b26-b58135bec748
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1360534813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.1360534813 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_shake_128.825255669
Short name	T770
Test name
Test status
Simulation time	190714717784 ps
CPU time	5230.23 seconds
Started	Jan 10 12:52:53 PM PST 24
Finished	Jan 10 02:21:15 PM PST 24
Peak memory	669892 kb
Host	smart-8cd7d477-4fd6-4d7b-9268-27321ef67601
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=825255669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.825255669 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_shake_256.2570575044
Short name	T255
Test name
Test status
Simulation time	812456427628 ps
CPU time	4904.12 seconds
Started	Jan 10 12:52:54 PM PST 24
Finished	Jan 10 02:15:51 PM PST 24
Peak memory	587344 kb
Host	smart-67d32b21-2e21-47f3-9a87-f1216b6924f2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2570575044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.2570575044 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/48.kmac_alert_test.3108198506
Short name	T1070
Test name
Test status
Simulation time	16282466 ps
CPU time	0.83 seconds
Started	Jan 10 12:52:52 PM PST 24
Finished	Jan 10 12:54:05 PM PST 24
Peak memory	219164 kb
Host	smart-12a4bb32-47dc-4355-be29-b6a66918c51f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108198506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.3108198506 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_alert_test/latest

Test location	/workspace/coverage/default/48.kmac_burst_write.1706596479
Short name	T99
Test name
Test status
Simulation time	71894478569 ps
CPU time	497.85 seconds
Started	Jan 10 12:52:44 PM PST 24
Finished	Jan 10 01:02:19 PM PST 24
Peak memory	243796 kb
Host	smart-7480e2f5-c449-4cbc-960a-c19428396251
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1706596479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.1706596479 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_burst_write/latest

Test location	/workspace/coverage/default/48.kmac_entropy_refresh.744146284
Short name	T244
Test name
Test status
Simulation time	39293409515 ps
CPU time	202.07 seconds
Started	Jan 10 12:52:40 PM PST 24
Finished	Jan 10 12:57:14 PM PST 24
Peak memory	243932 kb
Host	smart-429e071e-8b1e-4243-ad67-ae77a2a3b7a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=744146284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.744146284 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/48.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/48.kmac_error.426241660
Short name	T258
Test name
Test status
Simulation time	23270033751 ps
CPU time	171.45 seconds
Started	Jan 10 12:52:42 PM PST 24
Finished	Jan 10 12:56:45 PM PST 24
Peak memory	259892 kb
Host	smart-8f2d3800-fdff-4703-8ed2-1771aecbfc0d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=426241660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.426241660 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_error/latest

Test location	/workspace/coverage/default/48.kmac_key_error.3594015463
Short name	T459
Test name
Test status
Simulation time	2558978738 ps
CPU time	3.26 seconds
Started	Jan 10 12:53:28 PM PST 24
Finished	Jan 10 12:54:44 PM PST 24
Peak memory	219284 kb
Host	smart-71fa2e6d-5bbe-43b2-8380-e581e4e16880
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3594015463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.3594015463 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_key_error/latest

Test location	/workspace/coverage/default/48.kmac_lc_escalation.3796447728
Short name	T967
Test name
Test status
Simulation time	38345309 ps
CPU time	1.26 seconds
Started	Jan 10 12:52:44 PM PST 24
Finished	Jan 10 12:53:58 PM PST 24
Peak memory	220368 kb
Host	smart-8ac7d95b-c702-40b7-a4a0-b4140b27330d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3796447728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.3796447728 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/48.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/48.kmac_long_msg_and_output.1234204656
Short name	T767
Test name
Test status
Simulation time	227582000937 ps
CPU time	1619.16 seconds
Started	Jan 10 12:52:41 PM PST 24
Finished	Jan 10 01:20:51 PM PST 24
Peak memory	348804 kb
Host	smart-231c3d94-6d02-40e1-ae99-cfd2fab1f821
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234204656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a nd_output.1234204656 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/48.kmac_sideload.445015070
Short name	T965
Test name
Test status
Simulation time	30070674571 ps
CPU time	298.97 seconds
Started	Jan 10 12:52:34 PM PST 24
Finished	Jan 10 12:58:43 PM PST 24
Peak memory	249772 kb
Host	smart-f9ffbc40-23d9-4f6e-9ca9-89ec968d494d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=445015070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.445015070 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_sideload/latest

Test location	/workspace/coverage/default/48.kmac_smoke.446732476
Short name	T521
Test name
Test status
Simulation time	25931091621 ps
CPU time	57.05 seconds
Started	Jan 10 12:52:45 PM PST 24
Finished	Jan 10 12:54:52 PM PST 24
Peak memory	224916 kb
Host	smart-93c8d4c0-5c0a-4628-9e8b-cdae2d6d67ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=446732476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.446732476 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_smoke/latest

Test location	/workspace/coverage/default/48.kmac_stress_all.4155340168
Short name	T995
Test name
Test status
Simulation time	16935107840 ps
CPU time	383.44 seconds
Started	Jan 10 12:52:43 PM PST 24
Finished	Jan 10 01:00:18 PM PST 24
Peak memory	293008 kb
Host	smart-e7d43ca9-8593-4027-9827-7bc7321b0a13
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4155340168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.4155340168 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_stress_all/latest

Test location	/workspace/coverage/default/48.kmac_stress_all_with_rand_reset.2188677854
Short name	T47
Test name
Test status
Simulation time	194892858077 ps
CPU time	878.43 seconds
Started	Jan 10 12:52:43 PM PST 24
Finished	Jan 10 01:08:31 PM PST 24
Peak memory	285232 kb
Host	smart-ab21341f-6d9c-46a2-b225-4a1b9a692a68
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2188677854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all_with_rand_reset.2188677854 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_kmac.3693555157
Short name	T1112
Test name
Test status
Simulation time	110195092 ps
CPU time	5.87 seconds
Started	Jan 10 12:52:41 PM PST 24
Finished	Jan 10 12:54:08 PM PST 24
Peak memory	219268 kb
Host	smart-5e6148bb-61f8-4ff1-84d2-4c469c5b7b07
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693555157 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 48.kmac_test_vectors_kmac.3693555157 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_kmac_xof.663312423
Short name	T616
Test name
Test status
Simulation time	250923968 ps
CPU time	6.45 seconds
Started	Jan 10 12:53:10 PM PST 24
Finished	Jan 10 12:54:29 PM PST 24
Peak memory	220796 kb
Host	smart-adf09fae-2727-4b26-bcc5-1b610243679d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663312423 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 48.kmac_test_vectors_kmac_xof.663312423 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_224.3097285283
Short name	T718
Test name
Test status
Simulation time	711785357630 ps
CPU time	2128.37 seconds
Started	Jan 10 12:52:43 PM PST 24
Finished	Jan 10 01:29:21 PM PST 24
Peak memory	390108 kb
Host	smart-7946fc1b-7607-4648-80eb-cc81fa0b0aaf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3097285283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.3097285283 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_256.3871562211
Short name	T859
Test name
Test status
Simulation time	75960175620 ps
CPU time	2029.39 seconds
Started	Jan 10 12:52:44 PM PST 24
Finished	Jan 10 01:27:52 PM PST 24
Peak memory	376924 kb
Host	smart-bae32d3a-6619-440e-97e9-ed8a1b50a5f8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3871562211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.3871562211 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_384.809001305
Short name	T646
Test name
Test status
Simulation time	61447026416 ps
CPU time	1611.47 seconds
Started	Jan 10 12:52:49 PM PST 24
Finished	Jan 10 01:20:50 PM PST 24
Peak memory	349436 kb
Host	smart-5c58706d-0609-4efb-b167-159e1068e5fb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=809001305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.809001305 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_512.1954581311
Short name	T1056
Test name
Test status
Simulation time	34415057446 ps
CPU time	1214.95 seconds
Started	Jan 10 12:52:42 PM PST 24
Finished	Jan 10 01:14:12 PM PST 24
Peak memory	304564 kb
Host	smart-05e00106-2fcb-42ba-94a4-e2569b189da3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1954581311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.1954581311 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_shake_128.2457989006
Short name	T792
Test name
Test status
Simulation time	188125047102 ps
CPU time	5457.65 seconds
Started	Jan 10 12:52:42 PM PST 24
Finished	Jan 10 02:24:51 PM PST 24
Peak memory	659128 kb
Host	smart-a0e918b9-562d-4437-b51e-36fe61af1258
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2457989006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.2457989006 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_shake_256.95344155
Short name	T195
Test name
Test status
Simulation time	249856523887 ps
CPU time	4415.97 seconds
Started	Jan 10 12:52:39 PM PST 24
Finished	Jan 10 02:07:35 PM PST 24
Peak memory	578632 kb
Host	smart-51f262e4-b409-4289-8d59-c3526a10e8d5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=95344155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.95344155 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/49.kmac_alert_test.3755279420
Short name	T946
Test name
Test status
Simulation time	15117368 ps
CPU time	0.85 seconds
Started	Jan 10 12:52:57 PM PST 24
Finished	Jan 10 12:54:10 PM PST 24
Peak memory	220248 kb
Host	smart-45ae22e5-f34e-4984-96d5-64a24f70901c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755279420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.3755279420 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_alert_test/latest

Test location	/workspace/coverage/default/49.kmac_app.1697981045
Short name	T327
Test name
Test status
Simulation time	17993948298 ps
CPU time	196.59 seconds
Started	Jan 10 12:52:53 PM PST 24
Finished	Jan 10 12:57:21 PM PST 24
Peak memory	244252 kb
Host	smart-9e8d1aca-55e0-4c26-92cf-d9dc3171af6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1697981045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.1697981045 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_app/latest

Test location	/workspace/coverage/default/49.kmac_burst_write.2311718068
Short name	T850
Test name
Test status
Simulation time	10550723235 ps
CPU time	539.06 seconds
Started	Jan 10 12:52:48 PM PST 24
Finished	Jan 10 01:02:58 PM PST 24
Peak memory	234384 kb
Host	smart-ac21ebb1-a8b4-4db0-8a9c-b11e3bccd8c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2311718068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.2311718068 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_burst_write/latest

Test location	/workspace/coverage/default/49.kmac_entropy_refresh.1285852068
Short name	T571
Test name
Test status
Simulation time	9717966363 ps
CPU time	205.38 seconds
Started	Jan 10 12:52:52 PM PST 24
Finished	Jan 10 12:57:29 PM PST 24
Peak memory	242944 kb
Host	smart-0a9144d5-fd99-419c-b2b4-c1d44617f2fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1285852068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.1285852068 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/49.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/49.kmac_error.3528926387
Short name	T392
Test name
Test status
Simulation time	5382585789 ps
CPU time	45.14 seconds
Started	Jan 10 12:52:54 PM PST 24
Finished	Jan 10 12:54:51 PM PST 24
Peak memory	243840 kb
Host	smart-e4567ed2-7aae-4368-ada2-054a7868f0f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3528926387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.3528926387 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_error/latest

Test location	/workspace/coverage/default/49.kmac_key_error.1077856333
Short name	T814
Test name
Test status
Simulation time	4159814454 ps
CPU time	5.26 seconds
Started	Jan 10 12:52:41 PM PST 24
Finished	Jan 10 12:53:56 PM PST 24
Peak memory	219468 kb
Host	smart-8a75cde1-773c-4208-bfbf-499197bbfeb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1077856333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.1077856333 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_key_error/latest

Test location	/workspace/coverage/default/49.kmac_lc_escalation.3022820575
Short name	T318
Test name
Test status
Simulation time	644670754 ps
CPU time	1.61 seconds
Started	Jan 10 12:52:46 PM PST 24
Finished	Jan 10 12:53:57 PM PST 24
Peak memory	220228 kb
Host	smart-0b0bf050-11c1-4090-90ae-2905a0b5d7b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3022820575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.3022820575 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/49.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/49.kmac_long_msg_and_output.2347337358
Short name	T979
Test name
Test status
Simulation time	148028808062 ps
CPU time	2424.5 seconds
Started	Jan 10 12:52:48 PM PST 24
Finished	Jan 10 01:34:24 PM PST 24
Peak memory	436496 kb
Host	smart-81888de6-91c6-42c2-97a1-643e09d1afc7
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347337358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a nd_output.2347337358 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/49.kmac_sideload.276717341
Short name	T1101
Test name
Test status
Simulation time	29223942037 ps
CPU time	215.01 seconds
Started	Jan 10 12:53:14 PM PST 24
Finished	Jan 10 12:58:01 PM PST 24
Peak memory	244332 kb
Host	smart-765e6422-7022-4ab8-b39e-0cdf4bd0379a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=276717341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.276717341 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_sideload/latest

Test location	/workspace/coverage/default/49.kmac_smoke.548621787
Short name	T405
Test name
Test status
Simulation time	878477767 ps
CPU time	19.03 seconds
Started	Jan 10 12:53:01 PM PST 24
Finished	Jan 10 12:54:30 PM PST 24
Peak memory	227472 kb
Host	smart-60dddeaa-c03e-492b-ac1c-4890f1ea5023
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=548621787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.548621787 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_smoke/latest

Test location	/workspace/coverage/default/49.kmac_stress_all.1234372420
Short name	T146
Test name
Test status
Simulation time	79966436218 ps
CPU time	1336.43 seconds
Started	Jan 10 12:52:41 PM PST 24
Finished	Jan 10 01:16:08 PM PST 24
Peak memory	370284 kb
Host	smart-e145372b-1232-460c-9a57-a6c2661b9296
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1234372420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.1234372420 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_stress_all/latest

Test location	/workspace/coverage/default/49.kmac_stress_all_with_rand_reset.624488573
Short name	T836
Test name
Test status
Simulation time	30129205505 ps
CPU time	490.6 seconds
Started	Jan 10 12:52:44 PM PST 24
Finished	Jan 10 01:02:05 PM PST 24
Peak memory	274192 kb
Host	smart-7ef84725-1960-409f-9d45-65da770c3e00
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=624488573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all_with_rand_reset.624488573 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_kmac.2300431760
Short name	T541
Test name
Test status
Simulation time	411134358 ps
CPU time	6.09 seconds
Started	Jan 10 12:52:46 PM PST 24
Finished	Jan 10 12:54:02 PM PST 24
Peak memory	220616 kb
Host	smart-f60f9b69-761e-45c2-a7a0-6441ce944422
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300431760 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 49.kmac_test_vectors_kmac.2300431760 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_kmac_xof.2306408712
Short name	T1017
Test name
Test status
Simulation time	389961232 ps
CPU time	5.85 seconds
Started	Jan 10 12:53:03 PM PST 24
Finished	Jan 10 12:54:21 PM PST 24
Peak memory	220832 kb
Host	smart-24e75685-b112-40f4-8aec-9bdf2a4341b2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306408712 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_kmac_xof.2306408712 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_224.1305305917
Short name	T158
Test name
Test status
Simulation time	174381213373 ps
CPU time	2154.24 seconds
Started	Jan 10 12:52:55 PM PST 24
Finished	Jan 10 01:30:01 PM PST 24
Peak memory	402400 kb
Host	smart-79a4a1cb-7b78-445a-82e2-c6e197793cb8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1305305917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.1305305917 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_256.3540746963
Short name	T993
Test name
Test status
Simulation time	19426979895 ps
CPU time	1895.16 seconds
Started	Jan 10 12:52:46 PM PST 24
Finished	Jan 10 01:25:30 PM PST 24
Peak memory	393420 kb
Host	smart-fee35471-605a-4ab3-b18a-c741efd6ef95
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3540746963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.3540746963 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_384.3033273107
Short name	T467
Test name
Test status
Simulation time	283333656949 ps
CPU time	1635.11 seconds
Started	Jan 10 12:53:04 PM PST 24
Finished	Jan 10 01:21:30 PM PST 24
Peak memory	345976 kb
Host	smart-59da4485-84c1-4311-a8c7-68487e8694cc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3033273107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.3033273107 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_512.3005997082
Short name	T265
Test name
Test status
Simulation time	212630845916 ps
CPU time	1163.45 seconds
Started	Jan 10 12:52:54 PM PST 24
Finished	Jan 10 01:13:30 PM PST 24
Peak memory	305144 kb
Host	smart-ca7868f0-05f2-42ae-b82e-e0a0aad5e1b5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3005997082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.3005997082 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_shake_128.281472847
Short name	T829
Test name
Test status
Simulation time	365998791409 ps
CPU time	5751.46 seconds
Started	Jan 10 12:52:44 PM PST 24
Finished	Jan 10 02:29:47 PM PST 24
Peak memory	654664 kb
Host	smart-65a16461-b93d-409b-aed3-648a82a72b4b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=281472847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.281472847 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_shake_256.3532262199
Short name	T111
Test name
Test status
Simulation time	158684056564 ps
CPU time	4793.26 seconds
Started	Jan 10 12:53:11 PM PST 24
Finished	Jan 10 02:14:16 PM PST 24
Peak memory	575552 kb
Host	smart-b34d7b84-d384-4dbb-8845-cb38a7f3dda9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3532262199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.3532262199 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/5.kmac_alert_test.3323179186
Short name	T191
Test name
Test status
Simulation time	14564977 ps
CPU time	0.81 seconds
Started	Jan 10 12:50:32 PM PST 24
Finished	Jan 10 12:52:09 PM PST 24
Peak memory	220284 kb
Host	smart-2a227299-b15c-40e6-bb10-2985a1e6d5be
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323179186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.3323179186 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_alert_test/latest

Test location	/workspace/coverage/default/5.kmac_app.1775316660
Short name	T1113
Test name
Test status
Simulation time	35943805413 ps
CPU time	407.22 seconds
Started	Jan 10 12:50:27 PM PST 24
Finished	Jan 10 12:58:34 PM PST 24
Peak memory	254644 kb
Host	smart-cd2c9409-75b0-416f-b6ff-57b7eadaebb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1775316660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.1775316660 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_app/latest

Test location	/workspace/coverage/default/5.kmac_app_with_partial_data.3744903458
Short name	T573
Test name
Test status
Simulation time	9576476447 ps
CPU time	234.26 seconds
Started	Jan 10 12:50:25 PM PST 24
Finished	Jan 10 12:55:49 PM PST 24
Peak memory	243828 kb
Host	smart-4cb55473-b516-4298-81ac-19e0e18775de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3744903458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.3744903458 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/5.kmac_burst_write.2897318377
Short name	T828
Test name
Test status
Simulation time	57686564214 ps
CPU time	888.5 seconds
Started	Jan 10 12:50:28 PM PST 24
Finished	Jan 10 01:06:39 PM PST 24
Peak memory	243884 kb
Host	smart-458c2f1e-56b8-4df7-9751-5fe277e962d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2897318377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.2897318377 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_burst_write/latest

Test location	/workspace/coverage/default/5.kmac_edn_timeout_error.1300842166
Short name	T497
Test name
Test status
Simulation time	1158448946 ps
CPU time	38.97 seconds
Started	Jan 10 12:50:57 PM PST 24
Finished	Jan 10 12:52:59 PM PST 24
Peak memory	229252 kb
Host	smart-a677cc45-cc68-43a6-9024-d50f29c790fd
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1300842166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.1300842166 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/5.kmac_entropy_mode_error.463038277
Short name	T184
Test name
Test status
Simulation time	243292643 ps
CPU time	16.34 seconds
Started	Jan 10 12:50:19 PM PST 24
Finished	Jan 10 12:52:04 PM PST 24
Peak memory	227336 kb
Host	smart-b814235e-70d6-44de-b6be-bd4bcc70b1ba
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=463038277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.463038277 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/5.kmac_entropy_ready_error.2606209420
Short name	T678
Test name
Test status
Simulation time	39705257382 ps
CPU time	53.43 seconds
Started	Jan 10 12:50:22 PM PST 24
Finished	Jan 10 12:52:49 PM PST 24
Peak memory	220612 kb
Host	smart-ab32463a-503c-4f9c-8667-050ee1c9c5da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2606209420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.2606209420 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/5.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/5.kmac_entropy_refresh.4123934907
Short name	T611
Test name
Test status
Simulation time	7899625234 ps
CPU time	90.68 seconds
Started	Jan 10 12:50:23 PM PST 24
Finished	Jan 10 12:53:21 PM PST 24
Peak memory	236636 kb
Host	smart-570902fa-ae04-4377-a8fb-9788735389bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4123934907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.4123934907 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/5.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/5.kmac_error.2431463225
Short name	T439
Test name
Test status
Simulation time	13178734757 ps
CPU time	106.12 seconds
Started	Jan 10 12:50:27 PM PST 24
Finished	Jan 10 12:54:14 PM PST 24
Peak memory	243888 kb
Host	smart-d603da58-a138-4556-9f95-320ae3031e98
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2431463225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.2431463225 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_error/latest

Test location	/workspace/coverage/default/5.kmac_key_error.1270549199
Short name	T436
Test name
Test status
Simulation time	266848999 ps
CPU time	2.03 seconds
Started	Jan 10 12:50:23 PM PST 24
Finished	Jan 10 12:51:43 PM PST 24
Peak memory	219168 kb
Host	smart-2259f796-8207-4ab3-81c6-e2c61893f22e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1270549199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.1270549199 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_key_error/latest

Test location	/workspace/coverage/default/5.kmac_lc_escalation.2831928710
Short name	T466
Test name
Test status
Simulation time	35572757 ps
CPU time	1.32 seconds
Started	Jan 10 12:50:52 PM PST 24
Finished	Jan 10 12:52:16 PM PST 24
Peak memory	220524 kb
Host	smart-353d1ef4-5ab8-4a8b-b82a-21af50a4d2da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2831928710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.2831928710 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/5.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/5.kmac_long_msg_and_output.790683244
Short name	T716
Test name
Test status
Simulation time	41320810745 ps
CPU time	275.21 seconds
Started	Jan 10 12:50:24 PM PST 24
Finished	Jan 10 12:56:17 PM PST 24
Peak memory	245836 kb
Host	smart-8c02c269-de94-4ccd-a53c-9756bee5bb7b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790683244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and _output.790683244 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/5.kmac_mubi.3366214648
Short name	T453
Test name
Test status
Simulation time	4692391427 ps
CPU time	153.48 seconds
Started	Jan 10 12:50:56 PM PST 24
Finished	Jan 10 12:54:54 PM PST 24
Peak memory	240888 kb
Host	smart-6004c8fe-17ea-4008-bf9d-ea326df066e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3366214648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.3366214648 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_mubi/latest

Test location	/workspace/coverage/default/5.kmac_sideload.2117348205
Short name	T844
Test name
Test status
Simulation time	5786730370 ps
CPU time	221.08 seconds
Started	Jan 10 12:50:19 PM PST 24
Finished	Jan 10 12:55:19 PM PST 24
Peak memory	245096 kb
Host	smart-541ea0f1-2f08-4c66-8c8d-dfd9433c8a93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2117348205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.2117348205 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_sideload/latest

Test location	/workspace/coverage/default/5.kmac_smoke.3147452611
Short name	T309
Test name
Test status
Simulation time	4719629152 ps
CPU time	46.19 seconds
Started	Jan 10 12:50:23 PM PST 24
Finished	Jan 10 12:52:32 PM PST 24
Peak memory	224764 kb
Host	smart-628b1cb0-74f0-4626-9848-03eb6d3adc9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3147452611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.3147452611 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_smoke/latest

Test location	/workspace/coverage/default/5.kmac_stress_all.2795701787
Short name	T919
Test name
Test status
Simulation time	30644920135 ps
CPU time	583.21 seconds
Started	Jan 10 12:50:18 PM PST 24
Finished	Jan 10 01:01:31 PM PST 24
Peak memory	306012 kb
Host	smart-fd48a5e4-5c32-4672-ac11-7a5573abca74
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2795701787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.2795701787 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_stress_all/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_kmac.192838510
Short name	T296
Test name
Test status
Simulation time	235264342 ps
CPU time	5.72 seconds
Started	Jan 10 12:50:49 PM PST 24
Finished	Jan 10 12:52:12 PM PST 24
Peak memory	220656 kb
Host	smart-33e16d53-d8a0-4343-b15b-4f762336968f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192838510 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 5.kmac_test_vectors_kmac.192838510 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_kmac_xof.3806276959
Short name	T926
Test name
Test status
Simulation time	432945354 ps
CPU time	5.36 seconds
Started	Jan 10 12:50:23 PM PST 24
Finished	Jan 10 12:52:03 PM PST 24
Peak memory	219276 kb
Host	smart-9a4dd504-e0c9-42c5-99e2-a92202ebd51c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806276959 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_kmac_xof.3806276959 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_224.39357034
Short name	T1013
Test name
Test status
Simulation time	66861613291 ps
CPU time	2245.1 seconds
Started	Jan 10 12:50:24 PM PST 24
Finished	Jan 10 01:29:33 PM PST 24
Peak memory	404260 kb
Host	smart-6fd3469c-914f-47af-9e2c-094838593278
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=39357034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.39357034 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_256.1365357093
Short name	T698
Test name
Test status
Simulation time	39467968564 ps
CPU time	1821.29 seconds
Started	Jan 10 12:50:50 PM PST 24
Finished	Jan 10 01:22:24 PM PST 24
Peak memory	381640 kb
Host	smart-d90ffa6e-7866-425f-bd9c-d4461902bc7c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1365357093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.1365357093 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_384.488454161
Short name	T592
Test name
Test status
Simulation time	74073554174 ps
CPU time	1829.98 seconds
Started	Jan 10 12:50:27 PM PST 24
Finished	Jan 10 01:22:18 PM PST 24
Peak memory	349288 kb
Host	smart-65c0e04d-0373-425b-9df3-21c849ee3581
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=488454161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.488454161 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_512.2017766143
Short name	T419
Test name
Test status
Simulation time	63878498480 ps
CPU time	1229.58 seconds
Started	Jan 10 12:50:18 PM PST 24
Finished	Jan 10 01:12:25 PM PST 24
Peak memory	310632 kb
Host	smart-623c5d40-704b-4f4a-8c3d-e8b3222a0fbf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2017766143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.2017766143 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_shake_128.3231588562
Short name	T157
Test name
Test status
Simulation time	368540681654 ps
CPU time	5761.74 seconds
Started	Jan 10 12:50:51 PM PST 24
Finished	Jan 10 02:28:19 PM PST 24
Peak memory	656852 kb
Host	smart-11a86158-2d03-40ed-87cb-769f6df72edf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3231588562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.3231588562 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_shake_256.3181462720
Short name	T273
Test name
Test status
Simulation time	306785106724 ps
CPU time	5220.91 seconds
Started	Jan 10 12:50:23 PM PST 24
Finished	Jan 10 02:18:44 PM PST 24
Peak memory	588316 kb
Host	smart-4c8f7361-1649-4fec-b758-56c1fae1ab57
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3181462720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.3181462720 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/6.kmac_alert_test.2788792685
Short name	T104
Test name
Test status
Simulation time	21200863 ps
CPU time	0.86 seconds
Started	Jan 10 12:51:15 PM PST 24
Finished	Jan 10 12:52:46 PM PST 24
Peak memory	218932 kb
Host	smart-8c254bf6-2931-4c97-9ec7-06975ebb789a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788792685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.2788792685 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_alert_test/latest

Test location	/workspace/coverage/default/6.kmac_app.2551434086
Short name	T40
Test name
Test status
Simulation time	9638384508 ps
CPU time	108.82 seconds
Started	Jan 10 12:51:00 PM PST 24
Finished	Jan 10 12:54:01 PM PST 24
Peak memory	236736 kb
Host	smart-ac2305a9-0bfe-4a38-a021-e0e1d8619803
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2551434086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.2551434086 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_app/latest

Test location	/workspace/coverage/default/6.kmac_app_with_partial_data.1465437049
Short name	T306
Test name
Test status
Simulation time	11845930643 ps
CPU time	299.15 seconds
Started	Jan 10 12:50:31 PM PST 24
Finished	Jan 10 12:56:57 PM PST 24
Peak memory	248936 kb
Host	smart-beb59c2e-05a1-4b3a-ac80-d6e06cc2dd23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1465437049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.1465437049 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/6.kmac_burst_write.512793176
Short name	T887
Test name
Test status
Simulation time	18180358941 ps
CPU time	638.03 seconds
Started	Jan 10 12:51:09 PM PST 24
Finished	Jan 10 01:03:09 PM PST 24
Peak memory	243980 kb
Host	smart-19336d4f-5134-4077-9de1-f9216b00a754
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=512793176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.512793176 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_burst_write/latest

Test location	/workspace/coverage/default/6.kmac_edn_timeout_error.3141598229
Short name	T549
Test name
Test status
Simulation time	2274207666 ps
CPU time	38.45 seconds
Started	Jan 10 12:50:35 PM PST 24
Finished	Jan 10 12:52:42 PM PST 24
Peak memory	238244 kb
Host	smart-08ba7725-91c6-4f7d-9045-b2686546d592
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3141598229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.3141598229 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/6.kmac_entropy_mode_error.3553968715
Short name	T86
Test name
Test status
Simulation time	13462959 ps
CPU time	0.81 seconds
Started	Jan 10 12:51:00 PM PST 24
Finished	Jan 10 12:52:19 PM PST 24
Peak memory	218932 kb
Host	smart-5352242a-1ee5-4039-b2b1-6b15453d7e29
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3553968715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.3553968715 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/6.kmac_entropy_ready_error.901760651
Short name	T29
Test name
Test status
Simulation time	5762568130 ps
CPU time	68.82 seconds
Started	Jan 10 12:50:43 PM PST 24
Finished	Jan 10 12:53:15 PM PST 24
Peak memory	222168 kb
Host	smart-e1043c62-3b05-4c8c-b4d2-733598c174ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=901760651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.901760651 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspace/6.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/6.kmac_entropy_refresh.2404853573
Short name	T185
Test name
Test status
Simulation time	208769039 ps
CPU time	16.55 seconds
Started	Jan 10 12:51:12 PM PST 24
Finished	Jan 10 12:52:59 PM PST 24
Peak memory	233804 kb
Host	smart-c245beba-cdd9-45e6-b282-a16b659a66a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2404853573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.2404853573 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/6.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/6.kmac_key_error.4004780150
Short name	T30
Test name
Test status
Simulation time	1243453571 ps
CPU time	3.34 seconds
Started	Jan 10 12:51:13 PM PST 24
Finished	Jan 10 12:52:41 PM PST 24
Peak memory	219288 kb
Host	smart-b82f2cd4-4dc8-4e49-931b-1bb2d4e49dba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4004780150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.4004780150 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_key_error/latest

Test location	/workspace/coverage/default/6.kmac_lc_escalation.4131450538
Short name	T254
Test name
Test status
Simulation time	49119127 ps
CPU time	1.47 seconds
Started	Jan 10 12:50:45 PM PST 24
Finished	Jan 10 12:52:22 PM PST 24
Peak memory	220744 kb
Host	smart-a413dcd4-36ba-41bd-9796-ec504b16384c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4131450538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.4131450538 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/6.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/6.kmac_long_msg_and_output.3536011529
Short name	T313
Test name
Test status
Simulation time	576383025 ps
CPU time	49.46 seconds
Started	Jan 10 12:50:24 PM PST 24
Finished	Jan 10 12:52:40 PM PST 24
Peak memory	233028 kb
Host	smart-d8541ce2-0382-4ab2-9c1f-ea64173da0f9
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536011529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an d_output.3536011529 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/6.kmac_mubi.948512074
Short name	T384
Test name
Test status
Simulation time	7389460867 ps
CPU time	44.73 seconds
Started	Jan 10 12:50:36 PM PST 24
Finished	Jan 10 12:52:40 PM PST 24
Peak memory	244136 kb
Host	smart-84eff3e7-c469-4f20-8545-d848b2114824
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=948512074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.948512074 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_mubi/latest

Test location	/workspace/coverage/default/6.kmac_sideload.1598433652
Short name	T554
Test name
Test status
Simulation time	294217555 ps
CPU time	5.05 seconds
Started	Jan 10 12:50:28 PM PST 24
Finished	Jan 10 12:52:00 PM PST 24
Peak memory	226944 kb
Host	smart-88a14970-1f8f-49e9-a142-18f3b7b6b7f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1598433652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.1598433652 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_sideload/latest

Test location	/workspace/coverage/default/6.kmac_smoke.2235926317
Short name	T754
Test name
Test status
Simulation time	18639377646 ps
CPU time	82.27 seconds
Started	Jan 10 12:50:52 PM PST 24
Finished	Jan 10 12:53:32 PM PST 24
Peak memory	227564 kb
Host	smart-ef5b40cf-8aa0-44d9-91d8-7d2837fed4b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2235926317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.2235926317 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_smoke/latest

Test location	/workspace/coverage/default/6.kmac_stress_all.202084846
Short name	T585
Test name
Test status
Simulation time	41276612030 ps
CPU time	1328.97 seconds
Started	Jan 10 12:50:33 PM PST 24
Finished	Jan 10 01:14:16 PM PST 24
Peak memory	319960 kb
Host	smart-ebe3643d-8133-46ff-8f4d-dfdcb94912ed
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=202084846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.202084846 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_stress_all/latest

Test location	/workspace/coverage/default/6.kmac_stress_all_with_rand_reset.4025546715
Short name	T43
Test name
Test status
Simulation time	35732744811 ps
CPU time	689.19 seconds
Started	Jan 10 12:50:33 PM PST 24
Finished	Jan 10 01:03:36 PM PST 24
Peak memory	286184 kb
Host	smart-0875bb25-e872-4189-ab06-2d710d2657eb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4025546715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_with_rand_reset.4025546715 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_kmac.3537980597
Short name	T586
Test name
Test status
Simulation time	844750098 ps
CPU time	5.78 seconds
Started	Jan 10 12:51:03 PM PST 24
Finished	Jan 10 12:52:34 PM PST 24
Peak memory	219192 kb
Host	smart-85ad72f1-5a13-40bd-8412-3342053f0573
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537980597 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.kmac_test_vectors_kmac.3537980597 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_kmac_xof.1279917933
Short name	T605
Test name
Test status
Simulation time	492477428 ps
CPU time	6.8 seconds
Started	Jan 10 12:51:07 PM PST 24
Finished	Jan 10 12:52:39 PM PST 24
Peak memory	219340 kb
Host	smart-984f76b1-79f4-4091-8859-e625682140a0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279917933 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_kmac_xof.1279917933 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_224.611671070
Short name	T174
Test name
Test status
Simulation time	20661036867 ps
CPU time	1867.36 seconds
Started	Jan 10 12:50:20 PM PST 24
Finished	Jan 10 01:22:46 PM PST 24
Peak memory	393052 kb
Host	smart-78f71da0-b107-4a0a-a8e5-aa7c0101826b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=611671070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.611671070 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_256.1862415306
Short name	T1021
Test name
Test status
Simulation time	19966478618 ps
CPU time	1875.67 seconds
Started	Jan 10 12:50:58 PM PST 24
Finished	Jan 10 01:23:33 PM PST 24
Peak memory	391008 kb
Host	smart-4c014283-0dda-413b-a92e-6133b6b1514e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1862415306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.1862415306 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_384.3256135733
Short name	T476
Test name
Test status
Simulation time	31602273567 ps
CPU time	1455.26 seconds
Started	Jan 10 12:51:00 PM PST 24
Finished	Jan 10 01:16:29 PM PST 24
Peak memory	335772 kb
Host	smart-ece61035-063c-4ad7-9f51-b78a990d854f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3256135733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.3256135733 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_512.2933722416
Short name	T566
Test name
Test status
Simulation time	139710315161 ps
CPU time	1246.34 seconds
Started	Jan 10 12:50:43 PM PST 24
Finished	Jan 10 01:12:51 PM PST 24
Peak memory	299156 kb
Host	smart-2afaf8fd-a228-4234-bc68-c77ced628172
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2933722416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.2933722416 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_shake_128.2535525530
Short name	T211
Test name
Test status
Simulation time	763877682052 ps
CPU time	5585.13 seconds
Started	Jan 10 12:50:51 PM PST 24
Finished	Jan 10 02:25:29 PM PST 24
Peak memory	658020 kb
Host	smart-33bd3d99-606d-423b-aeb1-ed1441918e87
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2535525530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.2535525530 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_shake_256.1582430302
Short name	T354
Test name
Test status
Simulation time	421162560217 ps
CPU time	5264.78 seconds
Started	Jan 10 12:50:29 PM PST 24
Finished	Jan 10 02:19:41 PM PST 24
Peak memory	585360 kb
Host	smart-b5bd4d84-9f63-454b-8a71-6e8eea4d211a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1582430302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.1582430302 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/7.kmac_alert_test.4221227409
Short name	T303
Test name
Test status
Simulation time	34973753 ps
CPU time	0.8 seconds
Started	Jan 10 12:51:01 PM PST 24
Finished	Jan 10 12:52:18 PM PST 24
Peak memory	219084 kb
Host	smart-92513ce4-bd46-4259-af2f-51dea5d451f5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221227409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.4221227409 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_alert_test/latest

Test location	/workspace/coverage/default/7.kmac_app.3190523130
Short name	T289
Test name
Test status
Simulation time	6003107208 ps
CPU time	357.86 seconds
Started	Jan 10 12:50:39 PM PST 24
Finished	Jan 10 12:58:33 PM PST 24
Peak memory	252856 kb
Host	smart-5df6b68e-407a-4222-9fa7-a77e837467ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3190523130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.3190523130 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_app/latest

Test location	/workspace/coverage/default/7.kmac_app_with_partial_data.4230561777
Short name	T271
Test name
Test status
Simulation time	4548347662 ps
CPU time	25.5 seconds
Started	Jan 10 12:51:13 PM PST 24
Finished	Jan 10 12:53:00 PM PST 24
Peak memory	225068 kb
Host	smart-52d24548-a6a6-446e-8328-ae2b954a78e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4230561777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.4230561777 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/7.kmac_burst_write.4172191116
Short name	T420
Test name
Test status
Simulation time	4083089590 ps
CPU time	43.98 seconds
Started	Jan 10 12:51:04 PM PST 24
Finished	Jan 10 12:53:19 PM PST 24
Peak memory	223908 kb
Host	smart-d89a0bd9-a06a-48fe-b742-dfb1b76ebb45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4172191116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.4172191116 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_burst_write/latest

Test location	/workspace/coverage/default/7.kmac_edn_timeout_error.2985869783
Short name	T77
Test name
Test status
Simulation time	14776205 ps
CPU time	0.86 seconds
Started	Jan 10 12:50:36 PM PST 24
Finished	Jan 10 12:51:53 PM PST 24
Peak memory	219036 kb
Host	smart-e311d0fd-52c0-430b-8262-26b57fbbe48a
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2985869783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.2985869783 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/7.kmac_entropy_mode_error.2512404825
Short name	T372
Test name
Test status
Simulation time	240674332 ps
CPU time	4.71 seconds
Started	Jan 10 12:50:35 PM PST 24
Finished	Jan 10 12:51:54 PM PST 24
Peak memory	222328 kb
Host	smart-7e2c9a65-c56e-4142-ba61-34865ad3aeaa
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2512404825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.2512404825 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/7.kmac_entropy_ready_error.977364501
Short name	T671
Test name
Test status
Simulation time	306952172 ps
CPU time	2.88 seconds
Started	Jan 10 12:50:33 PM PST 24
Finished	Jan 10 12:52:00 PM PST 24
Peak memory	219424 kb
Host	smart-cefef350-d7a9-4b79-85ee-844b59803974
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=977364501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.977364501 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspace/7.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/7.kmac_entropy_refresh.1689058550
Short name	T868
Test name
Test status
Simulation time	148793384 ps
CPU time	2.68 seconds
Started	Jan 10 12:50:38 PM PST 24
Finished	Jan 10 12:51:59 PM PST 24
Peak memory	219248 kb
Host	smart-01ee85ce-9526-4b94-a790-5556e5c91fb3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1689058550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.1689058550 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/7.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/7.kmac_error.2366237258
Short name	T655
Test name
Test status
Simulation time	7468285181 ps
CPU time	127.86 seconds
Started	Jan 10 12:50:39 PM PST 24
Finished	Jan 10 12:54:11 PM PST 24
Peak memory	252224 kb
Host	smart-444f0eff-df2e-43c4-83d6-fdcd7406ba9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2366237258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.2366237258 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_error/latest

Test location	/workspace/coverage/default/7.kmac_key_error.1175292178
Short name	T325
Test name
Test status
Simulation time	1080480491 ps
CPU time	6.21 seconds
Started	Jan 10 12:50:40 PM PST 24
Finished	Jan 10 12:52:10 PM PST 24
Peak memory	219200 kb
Host	smart-a4b7efa9-9d6c-4268-aa14-08064576f98d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1175292178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.1175292178 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_key_error/latest

Test location	/workspace/coverage/default/7.kmac_lc_escalation.1632433312
Short name	T105
Test name
Test status
Simulation time	54276798 ps
CPU time	1.29 seconds
Started	Jan 10 12:50:33 PM PST 24
Finished	Jan 10 12:51:54 PM PST 24
Peak memory	220260 kb
Host	smart-a91219c6-8117-4e22-a5c2-52e646423821
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1632433312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1632433312 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/7.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/7.kmac_long_msg_and_output.1045330305
Short name	T284
Test name
Test status
Simulation time	83731691799 ps
CPU time	2161.07 seconds
Started	Jan 10 12:50:33 PM PST 24
Finished	Jan 10 01:28:08 PM PST 24
Peak memory	422640 kb
Host	smart-315e06fe-c62e-4213-89ef-064a329fa12c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045330305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an d_output.1045330305 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/7.kmac_mubi.2394775981
Short name	T1115
Test name
Test status
Simulation time	14053636315 ps
CPU time	173.82 seconds
Started	Jan 10 12:51:03 PM PST 24
Finished	Jan 10 12:55:20 PM PST 24
Peak memory	242712 kb
Host	smart-8d4e0db4-2895-49b8-b9b5-9f159b885ac4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2394775981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.2394775981 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_mubi/latest

Test location	/workspace/coverage/default/7.kmac_sideload.546241300
Short name	T454
Test name
Test status
Simulation time	6383690433 ps
CPU time	199.8 seconds
Started	Jan 10 12:50:47 PM PST 24
Finished	Jan 10 12:55:23 PM PST 24
Peak memory	242604 kb
Host	smart-6239a281-5e03-4c23-9139-19aa9b37d145
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=546241300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.546241300 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_sideload/latest

Test location	/workspace/coverage/default/7.kmac_smoke.2294642190
Short name	T504
Test name
Test status
Simulation time	4919747426 ps
CPU time	22.46 seconds
Started	Jan 10 12:50:33 PM PST 24
Finished	Jan 10 12:52:29 PM PST 24
Peak memory	224404 kb
Host	smart-ed2aaa8b-ae06-4d27-a8de-253b66e5adba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2294642190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.2294642190 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_smoke/latest

Test location	/workspace/coverage/default/7.kmac_stress_all.2060588402
Short name	T235
Test name
Test status
Simulation time	5936578763 ps
CPU time	10.86 seconds
Started	Jan 10 12:50:40 PM PST 24
Finished	Jan 10 12:52:37 PM PST 24
Peak memory	227524 kb
Host	smart-798219df-84fb-4ceb-9eb8-ae5227fe4b3e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2060588402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.2060588402 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_stress_all/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_kmac.736493426
Short name	T769
Test name
Test status
Simulation time	451839809 ps
CPU time	5.59 seconds
Started	Jan 10 12:50:36 PM PST 24
Finished	Jan 10 12:51:55 PM PST 24
Peak memory	220820 kb
Host	smart-d262af93-f8e0-4efc-bede-39cbcd61b47f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736493426 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 7.kmac_test_vectors_kmac.736493426 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_kmac_xof.1758169659
Short name	T425
Test name
Test status
Simulation time	715793491 ps
CPU time	5.69 seconds
Started	Jan 10 12:50:56 PM PST 24
Finished	Jan 10 12:52:17 PM PST 24
Peak memory	219364 kb
Host	smart-de6578d8-5fc9-4154-a728-886c0a90b594
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758169659 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_kmac_xof.1758169659 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_224.2950104690
Short name	T250
Test name
Test status
Simulation time	269166524945 ps
CPU time	2133.95 seconds
Started	Jan 10 12:50:31 PM PST 24
Finished	Jan 10 01:27:25 PM PST 24
Peak memory	393488 kb
Host	smart-5ef85639-fb01-4166-90eb-f966d6427a0b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2950104690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.2950104690 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_256.1070247716
Short name	T797
Test name
Test status
Simulation time	317232939509 ps
CPU time	2034.52 seconds
Started	Jan 10 12:51:00 PM PST 24
Finished	Jan 10 01:26:12 PM PST 24
Peak memory	379548 kb
Host	smart-d4b9f171-37b7-4457-b055-a4e6339de32a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1070247716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.1070247716 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_384.508321091
Short name	T1042
Test name
Test status
Simulation time	281664759674 ps
CPU time	1784.31 seconds
Started	Jan 10 12:50:59 PM PST 24
Finished	Jan 10 01:21:59 PM PST 24
Peak memory	341992 kb
Host	smart-e16d4ea1-8635-40bc-a6df-d4499120b505
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=508321091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.508321091 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_512.2104407811
Short name	T421
Test name
Test status
Simulation time	49169517997 ps
CPU time	1299.38 seconds
Started	Jan 10 12:50:36 PM PST 24
Finished	Jan 10 01:13:40 PM PST 24
Peak memory	302128 kb
Host	smart-ea8c01ce-f472-42e5-ad9a-8d93c5fa2331
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2104407811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.2104407811 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_shake_128.2791410146
Short name	T406
Test name
Test status
Simulation time	364741392568 ps
CPU time	5614.61 seconds
Started	Jan 10 12:51:03 PM PST 24
Finished	Jan 10 02:26:04 PM PST 24
Peak memory	648692 kb
Host	smart-94c2f6ba-bc22-485b-804d-e1dd59b1aa5c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2791410146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.2791410146 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_shake_256.2460281579
Short name	T909
Test name
Test status
Simulation time	494671307169 ps
CPU time	4301.55 seconds
Started	Jan 10 12:50:59 PM PST 24
Finished	Jan 10 02:04:06 PM PST 24
Peak memory	578884 kb
Host	smart-1c4d32dc-de77-4f23-a894-090e3035822f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2460281579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.2460281579 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/8.kmac_alert_test.2425184933
Short name	T542
Test name
Test status
Simulation time	45189404 ps
CPU time	0.88 seconds
Started	Jan 10 12:50:41 PM PST 24
Finished	Jan 10 12:52:11 PM PST 24
Peak memory	220196 kb
Host	smart-594b9ce0-60e1-4493-97e9-62e7428fd543
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425184933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.2425184933 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_alert_test/latest

Test location	/workspace/coverage/default/8.kmac_app.2215016324
Short name	T216
Test name
Test status
Simulation time	3257050526 ps
CPU time	230.23 seconds
Started	Jan 10 12:51:04 PM PST 24
Finished	Jan 10 12:56:12 PM PST 24
Peak memory	247576 kb
Host	smart-56e5e182-f8b7-4e76-8bd4-34f68fad0f3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2215016324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.2215016324 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_app/latest

Test location	/workspace/coverage/default/8.kmac_app_with_partial_data.439554404
Short name	T617
Test name
Test status
Simulation time	9838477936 ps
CPU time	62.29 seconds
Started	Jan 10 12:50:47 PM PST 24
Finished	Jan 10 12:53:06 PM PST 24
Peak memory	237748 kb
Host	smart-d592f764-5958-4393-83bb-21508f7bf9a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=439554404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.439554404 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/8.kmac_burst_write.1919047830
Short name	T726
Test name
Test status
Simulation time	17174680985 ps
CPU time	819.87 seconds
Started	Jan 10 12:50:38 PM PST 24
Finished	Jan 10 01:05:37 PM PST 24
Peak memory	242900 kb
Host	smart-d56920de-33fb-49f4-931d-5dbb7a172887
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1919047830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.1919047830 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_burst_write/latest

Test location	/workspace/coverage/default/8.kmac_edn_timeout_error.3775219582
Short name	T802
Test name
Test status
Simulation time	85766576 ps
CPU time	0.99 seconds
Started	Jan 10 12:50:45 PM PST 24
Finished	Jan 10 12:52:02 PM PST 24
Peak memory	218988 kb
Host	smart-5893d1d5-191b-4d2f-88d0-d1fdaa6a6a17
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3775219582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.3775219582 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/8.kmac_entropy_mode_error.2411750955
Short name	T822
Test name
Test status
Simulation time	74907002 ps
CPU time	1.01 seconds
Started	Jan 10 12:50:59 PM PST 24
Finished	Jan 10 12:52:14 PM PST 24
Peak memory	219060 kb
Host	smart-a82ec8d4-1bcd-495a-969a-304abe3d9d1a
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2411750955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.2411750955 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/8.kmac_entropy_ready_error.1661356139
Short name	T744
Test name
Test status
Simulation time	6159023708 ps
CPU time	18.69 seconds
Started	Jan 10 12:50:36 PM PST 24
Finished	Jan 10 12:52:08 PM PST 24
Peak memory	219392 kb
Host	smart-4632e1da-aa0f-4fb7-9a18-f63c00f30e35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1661356139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.1661356139 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/8.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/8.kmac_entropy_refresh.483644799
Short name	T619
Test name
Test status
Simulation time	24015582685 ps
CPU time	73.4 seconds
Started	Jan 10 12:50:40 PM PST 24
Finished	Jan 10 12:53:13 PM PST 24
Peak memory	240456 kb
Host	smart-ea109d9a-25ef-47af-8028-44ebc8847324
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=483644799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.483644799 +enable_masking=1 +sw_ key_masked=0
Directory	/workspace/8.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/8.kmac_key_error.718130937
Short name	T1110
Test name
Test status
Simulation time	3120907166 ps
CPU time	4.77 seconds
Started	Jan 10 12:51:10 PM PST 24
Finished	Jan 10 12:52:30 PM PST 24
Peak memory	219376 kb
Host	smart-a5c9c092-bb6d-4009-a18c-f77cec27cc84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=718130937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.718130937 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_key_error/latest

Test location	/workspace/coverage/default/8.kmac_lc_escalation.418148095
Short name	T925
Test name
Test status
Simulation time	86810214 ps
CPU time	1.34 seconds
Started	Jan 10 12:50:33 PM PST 24
Finished	Jan 10 12:52:15 PM PST 24
Peak memory	222536 kb
Host	smart-75e85b6a-d2f2-4ba4-bc07-9711b44ef7fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=418148095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.418148095 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/8.kmac_long_msg_and_output.2487270638
Short name	T540
Test name
Test status
Simulation time	78008103809 ps
CPU time	2837.03 seconds
Started	Jan 10 12:51:01 PM PST 24
Finished	Jan 10 01:39:43 PM PST 24
Peak memory	448788 kb
Host	smart-1722ce72-cf6e-458d-b64d-b091e52eddac
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487270638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an d_output.2487270638 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/8.kmac_mubi.2616109194
Short name	T730
Test name
Test status
Simulation time	3342698080 ps
CPU time	209.3 seconds
Started	Jan 10 12:50:54 PM PST 24
Finished	Jan 10 12:55:37 PM PST 24
Peak memory	247132 kb
Host	smart-b5da15b9-0e6c-43a0-b2e8-3a61637e3292
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2616109194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.2616109194 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_mubi/latest

Test location	/workspace/coverage/default/8.kmac_sideload.830125851
Short name	T708
Test name
Test status
Simulation time	1585750426 ps
CPU time	113.73 seconds
Started	Jan 10 12:51:15 PM PST 24
Finished	Jan 10 12:54:35 PM PST 24
Peak memory	236228 kb
Host	smart-389c0299-1870-45c1-9847-7549f717c678
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=830125851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.830125851 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_sideload/latest

Test location	/workspace/coverage/default/8.kmac_smoke.240150740
Short name	T911
Test name
Test status
Simulation time	20261126781 ps
CPU time	61.2 seconds
Started	Jan 10 12:51:07 PM PST 24
Finished	Jan 10 12:53:33 PM PST 24
Peak memory	227472 kb
Host	smart-d9f68810-3450-4375-b9b7-d1e95073f81e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=240150740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.240150740 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_smoke/latest

Test location	/workspace/coverage/default/8.kmac_stress_all.1737526392
Short name	T473
Test name
Test status
Simulation time	41734235855 ps
CPU time	233.29 seconds
Started	Jan 10 12:50:39 PM PST 24
Finished	Jan 10 12:55:45 PM PST 24
Peak memory	271496 kb
Host	smart-fa7cdb0b-b277-4e9b-91be-70ad34bec4e0
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1737526392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.1737526392 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_stress_all/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_kmac.3941462032
Short name	T713
Test name
Test status
Simulation time	703625788 ps
CPU time	6.08 seconds
Started	Jan 10 12:50:36 PM PST 24
Finished	Jan 10 12:52:02 PM PST 24
Peak memory	220700 kb
Host	smart-b2d2938c-4d2b-43ba-ab54-36d767d2b29a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941462032 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.kmac_test_vectors_kmac.3941462032 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_kmac_xof.2919414968
Short name	T720
Test name
Test status
Simulation time	499178524 ps
CPU time	6.48 seconds
Started	Jan 10 12:50:48 PM PST 24
Finished	Jan 10 12:52:14 PM PST 24
Peak memory	220592 kb
Host	smart-4d5970d5-6d96-4907-b637-4f758c0a9a86
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919414968 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_kmac_xof.2919414968 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_224.3994143617
Short name	T684
Test name
Test status
Simulation time	259666186474 ps
CPU time	2187.31 seconds
Started	Jan 10 12:50:44 PM PST 24
Finished	Jan 10 01:28:35 PM PST 24
Peak memory	397100 kb
Host	smart-1a6b2326-9fe2-435e-8b3f-199e8d8ae767
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3994143617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.3994143617 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_256.204806530
Short name	T904
Test name
Test status
Simulation time	87933515242 ps
CPU time	2157.56 seconds
Started	Jan 10 12:50:59 PM PST 24
Finished	Jan 10 01:28:17 PM PST 24
Peak memory	405476 kb
Host	smart-f693d1f4-2017-4b66-9de3-216ba42e4fe8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=204806530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.204806530 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_384.1243829819
Short name	T893
Test name
Test status
Simulation time	74950418245 ps
CPU time	1674.09 seconds
Started	Jan 10 12:50:37 PM PST 24
Finished	Jan 10 01:19:58 PM PST 24
Peak memory	347572 kb
Host	smart-4d374057-c70c-4f68-89d9-72484c661930
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1243829819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.1243829819 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_512.1086346142
Short name	T1084
Test name
Test status
Simulation time	34198428982 ps
CPU time	1188.79 seconds
Started	Jan 10 12:50:45 PM PST 24
Finished	Jan 10 01:12:01 PM PST 24
Peak memory	302684 kb
Host	smart-5e6b70f5-4750-45a9-a088-617d7e2089ad
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1086346142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.1086346142 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_shake_128.2955156326
Short name	T444
Test name
Test status
Simulation time	464790873163 ps
CPU time	5821.86 seconds
Started	Jan 10 12:50:32 PM PST 24
Finished	Jan 10 02:28:49 PM PST 24
Peak memory	665672 kb
Host	smart-b081c5ab-bc19-4648-977c-d8bf894a6b4d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2955156326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.2955156326 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_shake_256.1400747730
Short name	T793
Test name
Test status
Simulation time	157746981084 ps
CPU time	4628.34 seconds
Started	Jan 10 12:50:37 PM PST 24
Finished	Jan 10 02:09:09 PM PST 24
Peak memory	566860 kb
Host	smart-545f64d8-6f4e-4b2a-9696-7ddc965c4d0b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1400747730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.1400747730 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/9.kmac_alert_test.3182291719
Short name	T724
Test name
Test status
Simulation time	26530400 ps
CPU time	0.8 seconds
Started	Jan 10 12:51:14 PM PST 24
Finished	Jan 10 12:52:29 PM PST 24
Peak memory	218908 kb
Host	smart-0fed8564-f70e-4377-ac52-b61d5778a514
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182291719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.3182291719 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_alert_test/latest

Test location	/workspace/coverage/default/9.kmac_app.400111040
Short name	T487
Test name
Test status
Simulation time	45161374189 ps
CPU time	309.27 seconds
Started	Jan 10 12:51:10 PM PST 24
Finished	Jan 10 12:57:41 PM PST 24
Peak memory	250496 kb
Host	smart-a705918d-cfa5-487d-9773-f669c5dc287a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=400111040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.400111040 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_app/latest

Test location	/workspace/coverage/default/9.kmac_app_with_partial_data.2466876348
Short name	T88
Test name
Test status
Simulation time	172141906091 ps
CPU time	307.88 seconds
Started	Jan 10 12:50:40 PM PST 24
Finished	Jan 10 12:57:34 PM PST 24
Peak memory	245856 kb
Host	smart-a4acd356-2639-4cb6-92f8-f21afcacbc62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2466876348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.2466876348 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/9.kmac_burst_write.3589329186
Short name	T1047
Test name
Test status
Simulation time	32483098587 ps
CPU time	1629.95 seconds
Started	Jan 10 12:51:16 PM PST 24
Finished	Jan 10 01:19:46 PM PST 24
Peak memory	242064 kb
Host	smart-63a0895c-c851-4038-9a91-eadc678e4b3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3589329186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.3589329186 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_burst_write/latest

Test location	/workspace/coverage/default/9.kmac_edn_timeout_error.589723293
Short name	T342
Test name
Test status
Simulation time	16219998 ps
CPU time	0.9 seconds
Started	Jan 10 12:51:08 PM PST 24
Finished	Jan 10 12:52:28 PM PST 24
Peak memory	219124 kb
Host	smart-b9548c86-c2e2-4089-b336-b7709724814a
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=589723293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.589723293 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/9.kmac_entropy_mode_error.3882266127
Short name	T512
Test name
Test status
Simulation time	29312829 ps
CPU time	1.2 seconds
Started	Jan 10 12:50:37 PM PST 24
Finished	Jan 10 12:51:57 PM PST 24
Peak memory	219288 kb
Host	smart-989595af-d374-43f3-ac6f-f57b22f82860
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3882266127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.3882266127 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/9.kmac_entropy_ready_error.415078949
Short name	T832
Test name
Test status
Simulation time	11412766940 ps
CPU time	57.38 seconds
Started	Jan 10 12:50:45 PM PST 24
Finished	Jan 10 12:53:06 PM PST 24
Peak memory	227324 kb
Host	smart-f10e1095-0260-4d9e-9611-6117a12603ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=415078949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.415078949 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspace/9.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/9.kmac_entropy_refresh.2606435298
Short name	T19
Test name
Test status
Simulation time	23180754346 ps
CPU time	90.82 seconds
Started	Jan 10 12:50:40 PM PST 24
Finished	Jan 10 12:53:47 PM PST 24
Peak memory	234360 kb
Host	smart-f24a0d36-ac84-46e0-a1a2-2ee14b264b8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2606435298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.2606435298 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/9.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/9.kmac_error.2265079096
Short name	T608
Test name
Test status
Simulation time	18442886019 ps
CPU time	414.06 seconds
Started	Jan 10 12:50:44 PM PST 24
Finished	Jan 10 12:58:50 PM PST 24
Peak memory	259612 kb
Host	smart-405ce50e-a2dc-46c3-84d4-648cb7527ffa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2265079096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.2265079096 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_error/latest

Test location	/workspace/coverage/default/9.kmac_key_error.1984271153
Short name	T205
Test name
Test status
Simulation time	1281308708 ps
CPU time	4.16 seconds
Started	Jan 10 12:50:36 PM PST 24
Finished	Jan 10 12:51:53 PM PST 24
Peak memory	219324 kb
Host	smart-7e39690b-f2d2-4413-87af-8eb01d2c4b96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1984271153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.1984271153 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_key_error/latest

Test location	/workspace/coverage/default/9.kmac_lc_escalation.728497020
Short name	T877
Test name
Test status
Simulation time	425941342 ps
CPU time	12.05 seconds
Started	Jan 10 12:50:57 PM PST 24
Finished	Jan 10 12:52:26 PM PST 24
Peak memory	235596 kb
Host	smart-b888b43f-8c62-48d4-9bce-e064987276bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=728497020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.728497020 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/9.kmac_long_msg_and_output.2157010037
Short name	T308
Test name
Test status
Simulation time	34499493731 ps
CPU time	1182.2 seconds
Started	Jan 10 12:50:32 PM PST 24
Finished	Jan 10 01:11:33 PM PST 24
Peak memory	321472 kb
Host	smart-0d1fc89a-e241-4955-99ca-a7ecfd7395a6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157010037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an d_output.2157010037 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/9.kmac_mubi.1942181253
Short name	T45
Test name
Test status
Simulation time	20997610844 ps
CPU time	220.29 seconds
Started	Jan 10 12:50:36 PM PST 24
Finished	Jan 10 12:55:36 PM PST 24
Peak memory	245092 kb
Host	smart-4cb53ccc-a385-43a7-ba09-696bb081ea23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1942181253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.1942181253 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_mubi/latest

Test location	/workspace/coverage/default/9.kmac_sideload.1060369245
Short name	T1033
Test name
Test status
Simulation time	4498051360 ps
CPU time	121.64 seconds
Started	Jan 10 12:50:36 PM PST 24
Finished	Jan 10 12:53:54 PM PST 24
Peak memory	242896 kb
Host	smart-22aff260-6059-4aa9-bb59-21a4c0fbd9d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1060369245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.1060369245 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_sideload/latest

Test location	/workspace/coverage/default/9.kmac_smoke.2694065633
Short name	T712
Test name
Test status
Simulation time	2764520798 ps
CPU time	21.58 seconds
Started	Jan 10 12:50:55 PM PST 24
Finished	Jan 10 12:52:32 PM PST 24
Peak memory	221920 kb
Host	smart-54b47a41-6f82-4c76-9cfb-f1b70c3ab350
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2694065633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.2694065633 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_smoke/latest

Test location	/workspace/coverage/default/9.kmac_stress_all.1460751895
Short name	T743
Test name
Test status
Simulation time	60781230864 ps
CPU time	1138.19 seconds
Started	Jan 10 12:51:09 PM PST 24
Finished	Jan 10 01:11:25 PM PST 24
Peak memory	334324 kb
Host	smart-cfec1be8-afc4-47c2-b968-dd1c404fac10
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1460751895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.1460751895 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_stress_all/latest

Test location	/workspace/coverage/default/9.kmac_stress_all_with_rand_reset.295857952
Short name	T852
Test name
Test status
Simulation time	48594964334 ps
CPU time	1558.14 seconds
Started	Jan 10 12:51:14 PM PST 24
Finished	Jan 10 01:18:26 PM PST 24
Peak memory	338472 kb
Host	smart-286cbc8e-5514-401a-940f-33edc877147b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=295857952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all_with_rand_reset.295857952 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_kmac.271550173
Short name	T553
Test name
Test status
Simulation time	781308876 ps
CPU time	5.56 seconds
Started	Jan 10 12:50:48 PM PST 24
Finished	Jan 10 12:52:26 PM PST 24
Peak memory	220972 kb
Host	smart-b446893a-0285-4c4a-974e-76b1acd202bd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271550173 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 9.kmac_test_vectors_kmac.271550173 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_kmac_xof.3307634882
Short name	T775
Test name
Test status
Simulation time	708037906 ps
CPU time	6.69 seconds
Started	Jan 10 12:51:10 PM PST 24
Finished	Jan 10 12:52:47 PM PST 24
Peak memory	220588 kb
Host	smart-c9c7f2eb-0e73-45a4-8bba-5ea8a589e657
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307634882 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_kmac_xof.3307634882 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_224.2900086124
Short name	T213
Test name
Test status
Simulation time	279329244866 ps
CPU time	2282.93 seconds
Started	Jan 10 12:51:11 PM PST 24
Finished	Jan 10 01:30:34 PM PST 24
Peak memory	409272 kb
Host	smart-3748f908-38d4-434b-9e26-4a184b0526b6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2900086124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.2900086124 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_256.3509844594
Short name	T503
Test name
Test status
Simulation time	80476753786 ps
CPU time	2052 seconds
Started	Jan 10 12:50:44 PM PST 24
Finished	Jan 10 01:26:08 PM PST 24
Peak memory	381184 kb
Host	smart-f7259802-8edf-4009-b7af-de22a1a3dadb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3509844594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.3509844594 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_384.1061665136
Short name	T977
Test name
Test status
Simulation time	48007681814 ps
CPU time	1591.33 seconds
Started	Jan 10 12:50:40 PM PST 24
Finished	Jan 10 01:18:35 PM PST 24
Peak memory	340192 kb
Host	smart-fcb01ab4-e4c0-414d-b180-9e08cf1be9d9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1061665136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.1061665136 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_512.4286510316
Short name	T1053
Test name
Test status
Simulation time	21831286120 ps
CPU time	1122.9 seconds
Started	Jan 10 12:51:17 PM PST 24
Finished	Jan 10 01:11:29 PM PST 24
Peak memory	303336 kb
Host	smart-4663ea33-99e3-436e-ba51-39a5e061f8e1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4286510316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.4286510316 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_shake_128.3470128897
Short name	T294
Test name
Test status
Simulation time	1186196110862 ps
CPU time	6019.69 seconds
Started	Jan 10 12:50:51 PM PST 24
Finished	Jan 10 02:32:28 PM PST 24
Peak memory	661628 kb
Host	smart-25b2aca3-aebb-472e-ac21-5989ec44df94
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3470128897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.3470128897 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_shake_256.1055763289
Short name	T332
Test name
Test status
Simulation time	52518351887 ps
CPU time	4380.65 seconds
Started	Jan 10 12:51:08 PM PST 24
Finished	Jan 10 02:05:28 PM PST 24
Peak memory	561716 kb
Host	smart-6926d5e1-7ef7-4ed3-85b5-49f88c01ec1a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1055763289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.1055763289 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_shake_256/latest

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