Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101792901	1			T65	7		T66	5		T69	1
all_values[1]	101792901	1			T65	7		T66	5		T69	1
all_values[2]	101792901	1			T65	7		T66	5		T69	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

614921

1

T65

5

T66

4

T69

3

auto[1]

304763782

1

T65

16

T66

11

T113

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

303832578

1

T65

6

T66

15

T69

3

auto[1]

1546125

1

T65

15

T113

12

T131

9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	210522	1			T65	2		T66	2		T69	1
all_values[0]	auto[0]	auto[1]	2426	1			T65	1		T113	2		T131	1
all_values[0]	auto[1]	auto[0]	101067004	1			T66	3		T113	4		T131	3
all_values[0]	auto[1]	auto[1]	512949	1			T65	4		T113	2		T131	2
all_values[1]	auto[0]	auto[0]	188945	1			T66	2		T69	1		T72	1
all_values[1]	auto[0]	auto[1]	1748	1			T65	1		T113	2		T131	2
all_values[1]	auto[1]	auto[0]	101088581	1			T65	2		T66	3		T113	1
all_values[1]	auto[1]	auto[1]	513627	1			T65	4		T113	2		T131	1
all_values[2]	auto[0]	auto[0]	209506	1			T69	1		T72	1		T113	1
all_values[2]	auto[0]	auto[1]	1774	1			T65	1		T113	2		T131	3
all_values[2]	auto[1]	auto[0]	101068020	1			T65	2		T66	5		T113	3
all_values[2]	auto[1]	auto[1]	513601	1			T65	4		T113	2		T152	3