Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
332551 |
1 |
|
|
T5 |
18 |
|
T10 |
2 |
|
T11 |
2 |
auto[1] |
368856 |
1 |
|
|
T10 |
490 |
|
T15 |
4672 |
|
T35 |
618 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
175680 |
1 |
|
|
T5 |
2 |
|
T10 |
114 |
|
T15 |
1158 |
lower_val |
173143 |
1 |
|
|
T5 |
5 |
|
T10 |
98 |
|
T15 |
1184 |
zero_val |
2018 |
1 |
|
|
T5 |
1 |
|
T10 |
1 |
|
T11 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
257652 |
1 |
|
|
T5 |
12 |
|
T10 |
126 |
|
T11 |
2 |
lower_val |
259159 |
1 |
|
|
T5 |
6 |
|
T10 |
112 |
|
T15 |
1206 |
zero_val |
184596 |
1 |
|
|
T10 |
254 |
|
T15 |
2280 |
|
T35 |
314 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
41500 |
1 |
|
|
T5 |
1 |
|
T13 |
2 |
|
T14 |
18 |
higher_val |
higher_val |
auto[1] |
23135 |
1 |
|
|
T10 |
29 |
|
T15 |
290 |
|
T35 |
41 |
higher_val |
lower_val |
auto[0] |
41652 |
1 |
|
|
T5 |
1 |
|
T13 |
3 |
|
T14 |
8 |
higher_val |
lower_val |
auto[1] |
23351 |
1 |
|
|
T10 |
20 |
|
T15 |
282 |
|
T35 |
33 |
higher_val |
zero_val |
auto[0] |
109 |
1 |
|
|
T10 |
1 |
|
T15 |
1 |
|
T36 |
1 |
higher_val |
zero_val |
auto[1] |
45933 |
1 |
|
|
T10 |
64 |
|
T15 |
585 |
|
T35 |
74 |
lower_val |
higher_val |
auto[0] |
40472 |
1 |
|
|
T5 |
4 |
|
T13 |
3 |
|
T14 |
17 |
lower_val |
higher_val |
auto[1] |
22717 |
1 |
|
|
T10 |
30 |
|
T15 |
309 |
|
T35 |
31 |
lower_val |
lower_val |
auto[0] |
41149 |
1 |
|
|
T5 |
1 |
|
T13 |
5 |
|
T14 |
19 |
lower_val |
lower_val |
auto[1] |
22962 |
1 |
|
|
T10 |
18 |
|
T15 |
327 |
|
T35 |
47 |
lower_val |
zero_val |
auto[0] |
99 |
1 |
|
|
T44 |
1 |
|
T38 |
1 |
|
T32 |
1 |
lower_val |
zero_val |
auto[1] |
45744 |
1 |
|
|
T10 |
50 |
|
T15 |
548 |
|
T35 |
84 |
zero_val |
higher_val |
auto[0] |
567 |
1 |
|
|
T5 |
1 |
|
T11 |
1 |
|
T14 |
1 |
zero_val |
higher_val |
auto[1] |
168 |
1 |
|
|
T167 |
1 |
|
T168 |
1 |
|
T169 |
2 |
zero_val |
lower_val |
auto[0] |
587 |
1 |
|
|
T12 |
1 |
|
T16 |
1 |
|
T13 |
1 |
zero_val |
lower_val |
auto[1] |
150 |
1 |
|
|
T36 |
1 |
|
T167 |
1 |
|
T170 |
1 |
zero_val |
zero_val |
auto[0] |
297 |
1 |
|
|
T10 |
1 |
|
T15 |
1 |
|
T35 |
1 |
zero_val |
zero_val |
auto[1] |
249 |
1 |
|
|
T36 |
1 |
|
T167 |
4 |
|
T170 |
1 |