Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10201	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9317	1			T15	30		T35	24		T12	2
len_5001_7500	15269	1			T10	33		T15	30		T35	24
len_2501_5000	9376	1			T10	34		T15	30		T35	24
len_1025_2500	5513	1			T10	20		T15	16		T35	14
len_769_1024	6616	1			T10	4		T15	4		T35	2
len_513_768	7216	1			T10	3		T15	2		T35	3
len_257_512	21352	1			T10	4		T15	244		T35	2
len_0_256	258313	1			T5	9		T10	148		T15	1897
len_keccak_block_sizes[72]	729	1			T10	2		T15	3		T35	2
len_keccak_block_sizes[104]	611	1			T15	3		T35	2		T45	2
len_keccak_block_sizes[136]	528	1			T15	3		T14	1		T45	2
len_keccak_block_sizes[144]	420	1			T15	3		T37	1		T63	2
len_keccak_block_sizes[168]	323	1			T15	3		T42	1		T167	3
len_1	743	1			T10	2		T15	3		T35	2
len_0	1292	1			T10	2		T15	3		T35	2