Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101792901	1			T65	7		T66	5		T69	1
all_pins[1]	101792901	1			T65	7		T66	5		T69	1
all_pins[2]	101792901	1			T65	7		T66	5		T69	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	253506143	1			T65	10		T66	12		T69	3
values[0x1]	51872560	1			T65	11		T66	3		T113	6
transitions[0x0=>0x1]	51412651	1			T65	1		T66	2		T113	5
transitions[0x1=>0x0]	51412678	1			T65	2		T66	3		T113	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	101279952	1			T65	3		T66	5		T69	1
all_pins[0]	values[0x1]	512949	1			T65	4		T113	2		T131	2
all_pins[0]	transitions[0x0=>0x1]	215585	1			T65	1		T113	2		T131	2
all_pins[0]	transitions[0x1=>0x0]	50666210	1			T66	2		T113	1		T131	2
all_pins[1]	values[0x0]	50829327	1			T65	4		T66	3		T69	1
all_pins[1]	values[0x1]	50963574	1			T65	3		T66	2		T113	1
all_pins[1]	transitions[0x0=>0x1]	50803539	1			T66	2		T113	1		T131	2
all_pins[1]	transitions[0x1=>0x0]	236002	1			T65	1		T66	1		T113	3
all_pins[2]	values[0x0]	101396864	1			T65	3		T66	4		T69	1
all_pins[2]	values[0x1]	396037	1			T65	4		T66	1		T113	3
all_pins[2]	transitions[0x0=>0x1]	393527	1			T113	2		T131	1		T153	2
all_pins[2]	transitions[0x1=>0x0]	510466	1			T65	1		T113	1		T131	2