Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11365876 |
1 |
|
|
T5 |
96 |
|
T10 |
3936 |
|
T15 |
27235 |
auto[1] |
11365587 |
1 |
|
|
T5 |
96 |
|
T10 |
3936 |
|
T15 |
27235 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
22487480 |
1 |
|
|
T5 |
192 |
|
T10 |
7872 |
|
T15 |
52796 |
triple_byte_access |
80857 |
1 |
|
|
T15 |
558 |
|
T12 |
12 |
|
T13 |
12 |
halfword_access |
81864 |
1 |
|
|
T15 |
558 |
|
T12 |
4 |
|
T13 |
10 |
byte_access |
81262 |
1 |
|
|
T15 |
558 |
|
T12 |
16 |
|
T13 |
4 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
11243883 |
1 |
|
|
T5 |
96 |
|
T10 |
3936 |
|
T15 |
26398 |
auto[0] |
triple_byte_access |
40429 |
1 |
|
|
T15 |
279 |
|
T12 |
6 |
|
T13 |
6 |
auto[0] |
halfword_access |
40932 |
1 |
|
|
T15 |
279 |
|
T12 |
2 |
|
T13 |
5 |
auto[0] |
byte_access |
40632 |
1 |
|
|
T15 |
279 |
|
T12 |
8 |
|
T13 |
2 |
auto[1] |
word_access |
11243597 |
1 |
|
|
T5 |
96 |
|
T10 |
3936 |
|
T15 |
26398 |
auto[1] |
triple_byte_access |
40428 |
1 |
|
|
T15 |
279 |
|
T12 |
6 |
|
T13 |
6 |
auto[1] |
halfword_access |
40932 |
1 |
|
|
T15 |
279 |
|
T12 |
2 |
|
T13 |
5 |
auto[1] |
byte_access |
40630 |
1 |
|
|
T15 |
279 |
|
T12 |
8 |
|
T13 |
2 |