Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 275 1 T65 7 T66 4 T113 7
all_values[1] 275 1 T65 7 T66 4 T113 7
all_values[2] 275 1 T65 7 T66 4 T113 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 422 1 T65 5 T66 4 T113 8
auto[1] 403 1 T65 16 T66 8 T113 13


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 295 1 T65 8 T66 6 T113 2
auto[1] 530 1 T65 13 T66 6 T113 19


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 479 1 T65 12 T66 8 T113 10
auto[1] 346 1 T65 9 T66 4 T113 11


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 53 1 T65 1 T66 2 T131 1
all_values[0] auto[0] auto[0] auto[1] 27 1 T152 2 T154 1 T155 1
all_values[0] auto[0] auto[1] auto[0] 46 1 T66 1 T113 1 T131 2
all_values[0] auto[0] auto[1] auto[1] 37 1 T65 2 T113 3 T131 1
all_values[0] auto[1] auto[0] auto[1] 57 1 T65 2 T113 2 T131 2
all_values[0] auto[1] auto[1] auto[1] 55 1 T65 2 T66 1 T113 1
all_values[1] auto[0] auto[0] auto[0] 49 1 T131 1 T152 2 T153 2
all_values[1] auto[0] auto[0] auto[1] 30 1 T113 3 T152 1 T156 1
all_values[1] auto[0] auto[1] auto[0] 45 1 T65 4 T113 1 T152 2
all_values[1] auto[0] auto[1] auto[1] 30 1 T66 2 T131 3 T154 1
all_values[1] auto[1] auto[0] auto[1] 73 1 T65 1 T66 2 T131 3
all_values[1] auto[1] auto[1] auto[1] 48 1 T65 2 T113 3 T153 1
all_values[2] auto[0] auto[0] auto[0] 47 1 T65 1 T131 2 T154 3
all_values[2] auto[0] auto[0] auto[1] 28 1 T113 1 T131 2 T152 1
all_values[2] auto[0] auto[1] auto[0] 55 1 T65 2 T66 3 T152 3
all_values[2] auto[0] auto[1] auto[1] 32 1 T65 2 T113 1 T153 1
all_values[2] auto[1] auto[0] auto[1] 58 1 T113 2 T131 3 T152 2
all_values[2] auto[1] auto[1] auto[1] 55 1 T65 2 T66 1 T113 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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