Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100561191	1			T59	7		T61	5		T62	1
all_values[1]	100561191	1			T59	7		T61	5		T62	1
all_values[2]	100561191	1			T59	7		T61	5		T62	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

653588

1

T59

13

T61

6

T62

3

auto[1]

301029985

1

T59

8

T61

9

T64

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300133842

1

T59

12

T61

9

T62

3

auto[1]

1549731

1

T59

9

T61

6

T64

12

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	192148	1			T59	3		T61	1		T62	1
all_values[0]	auto[0]	auto[1]	2329	1			T59	1		T61	2		T64	1
all_values[0]	auto[1]	auto[0]	99852466	1			T59	1		T61	2		T64	3
all_values[0]	auto[1]	auto[1]	514248	1			T59	2		T64	3		T147	1
all_values[1]	auto[0]	auto[0]	230630	1			T59	3		T62	1		T63	1
all_values[1]	auto[0]	auto[1]	1757	1			T59	1		T64	1		T147	1
all_values[1]	auto[1]	auto[0]	99813984	1			T59	1		T61	3		T64	2
all_values[1]	auto[1]	auto[1]	514820	1			T59	2		T61	2		T64	3
all_values[2]	auto[0]	auto[0]	224897	1			T59	4		T61	1		T62	1
all_values[2]	auto[0]	auto[1]	1827	1			T59	1		T61	2		T64	3
all_values[2]	auto[1]	auto[0]	99819717	1			T61	2		T64	2		T146	2
all_values[2]	auto[1]	auto[1]	514750	1			T59	2		T64	1		T146	2