Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
350840 |
1 |
|
|
T4 |
2 |
|
T5 |
2 |
|
T6 |
748 |
auto[1] |
351636 |
1 |
|
|
T4 |
288 |
|
T5 |
778 |
|
T34 |
746 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
175607 |
1 |
|
|
T4 |
76 |
|
T5 |
218 |
|
T6 |
166 |
lower_val |
174128 |
1 |
|
|
T4 |
69 |
|
T5 |
178 |
|
T6 |
176 |
zero_val |
2012 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
262456 |
1 |
|
|
T4 |
78 |
|
T5 |
178 |
|
T6 |
394 |
lower_val |
263914 |
1 |
|
|
T4 |
66 |
|
T5 |
192 |
|
T6 |
354 |
zero_val |
176106 |
1 |
|
|
T4 |
146 |
|
T5 |
410 |
|
T34 |
342 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
43501 |
1 |
|
|
T6 |
81 |
|
T10 |
25 |
|
T47 |
60 |
higher_val |
higher_val |
auto[1] |
22161 |
1 |
|
|
T4 |
17 |
|
T5 |
50 |
|
T34 |
45 |
higher_val |
lower_val |
auto[0] |
43771 |
1 |
|
|
T6 |
85 |
|
T10 |
23 |
|
T11 |
1 |
higher_val |
lower_val |
auto[1] |
21894 |
1 |
|
|
T4 |
22 |
|
T5 |
59 |
|
T34 |
45 |
higher_val |
zero_val |
auto[0] |
88 |
1 |
|
|
T35 |
1 |
|
T84 |
1 |
|
T16 |
1 |
higher_val |
zero_val |
auto[1] |
44192 |
1 |
|
|
T4 |
37 |
|
T5 |
109 |
|
T34 |
82 |
lower_val |
higher_val |
auto[0] |
43129 |
1 |
|
|
T6 |
99 |
|
T10 |
29 |
|
T47 |
74 |
lower_val |
higher_val |
auto[1] |
21808 |
1 |
|
|
T4 |
20 |
|
T5 |
40 |
|
T34 |
39 |
lower_val |
lower_val |
auto[0] |
43859 |
1 |
|
|
T4 |
1 |
|
T6 |
77 |
|
T34 |
1 |
lower_val |
lower_val |
auto[1] |
21802 |
1 |
|
|
T4 |
12 |
|
T5 |
39 |
|
T34 |
56 |
lower_val |
zero_val |
auto[0] |
102 |
1 |
|
|
T43 |
1 |
|
T17 |
1 |
|
T18 |
3 |
lower_val |
zero_val |
auto[1] |
43428 |
1 |
|
|
T4 |
36 |
|
T5 |
99 |
|
T34 |
86 |
zero_val |
higher_val |
auto[0] |
578 |
1 |
|
|
T6 |
1 |
|
T38 |
5 |
|
T39 |
3 |
zero_val |
higher_val |
auto[1] |
154 |
1 |
|
|
T16 |
1 |
|
T17 |
2 |
|
T18 |
2 |
zero_val |
lower_val |
auto[0] |
581 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T34 |
1 |
zero_val |
lower_val |
auto[1] |
182 |
1 |
|
|
T84 |
1 |
|
T27 |
1 |
|
T16 |
3 |
zero_val |
zero_val |
auto[0] |
264 |
1 |
|
|
T35 |
1 |
|
T84 |
1 |
|
T42 |
1 |
zero_val |
zero_val |
auto[1] |
253 |
1 |
|
|
T84 |
1 |
|
T165 |
1 |
|
T80 |
1 |