Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10350	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9165	1			T5	17		T6	19		T34	19
len_5001_7500	14809	1			T5	17		T6	18		T34	18
len_2501_5000	9244	1			T5	17		T6	18		T34	18
len_1025_2500	5512	1			T5	10		T6	11		T34	11
len_769_1024	6551	1			T4	30		T5	2		T6	2
len_513_768	6865	1			T4	32		T5	2		T6	2
len_257_512	21386	1			T4	36		T5	2		T6	2
len_0_256	260089	1			T4	31		T5	290		T6	274
len_keccak_block_sizes[72]	722	1			T5	2		T6	2		T34	2
len_keccak_block_sizes[104]	614	1			T5	2		T6	2		T34	2
len_keccak_block_sizes[136]	519	1			T5	2		T6	2		T34	2
len_keccak_block_sizes[144]	425	1			T4	1		T5	2		T38	3
len_keccak_block_sizes[168]	322	1			T38	3		T79	1		T28	3
len_1	775	1			T5	2		T6	2		T34	2
len_0	1240	1			T5	2		T6	2		T34	2