Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100561191	1			T59	7		T61	5		T62	1
all_pins[1]	100561191	1			T59	7		T61	5		T62	1
all_pins[2]	100561191	1			T59	7		T61	5		T62	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	250192564	1			T59	16		T61	15		T62	3
values[0x1]	51491009	1			T59	5		T64	4		T146	3
transitions[0x0=>0x1]	51080563	1			T59	5		T64	4		T146	3
transitions[0x1=>0x0]	51080588	1			T59	5		T64	4		T146	3

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100046943	1			T59	5		T61	5		T62	1
all_pins[0]	values[0x1]	514248	1			T59	2		T64	3		T147	1
all_pins[0]	transitions[0x0=>0x1]	216765	1			T59	2		T64	3		T147	1
all_pins[0]	transitions[0x1=>0x0]	50392378	1			T59	1		T64	1		T146	3
all_pins[1]	values[0x0]	49871330	1			T59	6		T61	5		T62	1
all_pins[1]	values[0x1]	50689861	1			T59	1		T64	1		T146	3
all_pins[1]	transitions[0x0=>0x1]	50578582	1			T59	1		T64	1		T146	3
all_pins[1]	transitions[0x1=>0x0]	175621	1			T59	2		T157	1		T131	4
all_pins[2]	values[0x0]	100274291	1			T59	5		T61	5		T62	1
all_pins[2]	values[0x1]	286900	1			T59	2		T147	2		T158	2
all_pins[2]	transitions[0x0=>0x1]	285216	1			T59	2		T147	1		T158	2
all_pins[2]	transitions[0x1=>0x0]	512589	1			T59	2		T64	3		T159	2