Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 272 1 T59 7 T61 4 T64 7
all_values[1] 272 1 T59 7 T61 4 T64 7
all_values[2] 272 1 T59 7 T61 4 T64 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 461 1 T59 14 T61 2 T64 10
auto[1] 355 1 T59 7 T61 10 T64 11


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 327 1 T59 7 T61 4 T64 10
auto[1] 489 1 T59 14 T61 8 T64 11


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 492 1 T59 9 T61 6 T64 12
auto[1] 324 1 T59 12 T61 6 T64 9


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 66 1 T59 2 T64 1 T146 1
all_values[0] auto[0] auto[0] auto[1] 27 1 T59 1 T61 1 T146 1
all_values[0] auto[0] auto[1] auto[0] 46 1 T59 1 T64 1 T146 1
all_values[0] auto[0] auto[1] auto[1] 35 1 T64 1 T159 1 T160 2
all_values[0] auto[1] auto[0] auto[1] 44 1 T59 1 T64 2 T147 1
all_values[0] auto[1] auto[1] auto[1] 54 1 T59 2 T61 3 T64 2
all_values[1] auto[0] auto[0] auto[0] 59 1 T59 3 T64 2 T146 1
all_values[1] auto[0] auto[0] auto[1] 28 1 T64 1 T161 1 T158 1
all_values[1] auto[0] auto[1] auto[0] 41 1 T61 3 T64 2 T161 1
all_values[1] auto[0] auto[1] auto[1] 30 1 T59 1 T146 2 T147 1
all_values[1] auto[1] auto[0] auto[1] 72 1 T59 1 T64 2 T148 1
all_values[1] auto[1] auto[1] auto[1] 42 1 T59 2 T61 1 T146 1
all_values[2] auto[0] auto[0] auto[0] 73 1 T59 1 T64 2 T146 1
all_values[2] auto[0] auto[0] auto[1] 24 1 T61 1 T159 1 T162 1
all_values[2] auto[0] auto[1] auto[0] 42 1 T61 1 T64 2 T146 3
all_values[2] auto[0] auto[1] auto[1] 21 1 T147 1 T158 1 T131 2
all_values[2] auto[1] auto[0] auto[1] 68 1 T59 5 T147 1 T148 4
all_values[2] auto[1] auto[1] auto[1] 44 1 T59 1 T61 2 T64 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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