Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99780429	1			T3	7		T63	8		T67	1
all_values[1]	99780429	1			T3	7		T63	8		T67	1
all_values[2]	99780429	1			T3	7		T63	8		T67	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

666886

1

T3

12

T63

9

T67

3

auto[1]

298674401

1

T3

9

T63

15

T69

11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297803904

1

T3

9

T63

18

T67

3

auto[1]

1537383

1

T3

12

T63

6

T69

15

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	228512	1			T3	2		T63	2		T67	1
all_values[0]	auto[0]	auto[1]	2359	1			T3	1		T63	1		T69	4
all_values[0]	auto[1]	auto[0]	99039456	1			T3	1		T63	4		T69	3
all_values[0]	auto[1]	auto[1]	510102	1			T3	3		T63	1		T69	1
all_values[1]	auto[0]	auto[0]	208631	1			T3	2		T63	3		T67	1
all_values[1]	auto[0]	auto[1]	1737	1			T3	2		T63	1		T69	2
all_values[1]	auto[1]	auto[0]	99059337	1			T3	1		T63	3		T74	7
all_values[1]	auto[1]	auto[1]	510724	1			T3	2		T63	1		T69	3
all_values[2]	auto[0]	auto[0]	223857	1			T3	3		T67	1		T74	4
all_values[2]	auto[0]	auto[1]	1790	1			T3	2		T63	2		T69	4
all_values[2]	auto[1]	auto[0]	99044111	1			T63	6		T69	3		T74	4
all_values[2]	auto[1]	auto[1]	510671	1			T3	2		T69	1		T155	3