Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
351652 |
1 |
|
|
T4 |
2 |
|
T5 |
2 |
|
T6 |
2 |
auto[1] |
346489 |
1 |
|
|
T4 |
216 |
|
T5 |
350 |
|
T6 |
108 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174475 |
1 |
|
|
T4 |
61 |
|
T5 |
74 |
|
T6 |
22 |
lower_val |
173212 |
1 |
|
|
T4 |
56 |
|
T5 |
90 |
|
T6 |
25 |
zero_val |
2114 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
262801 |
1 |
|
|
T4 |
48 |
|
T5 |
82 |
|
T6 |
18 |
lower_val |
261254 |
1 |
|
|
T4 |
58 |
|
T5 |
100 |
|
T6 |
40 |
zero_val |
174086 |
1 |
|
|
T4 |
112 |
|
T5 |
170 |
|
T6 |
52 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
44074 |
1 |
|
|
T32 |
107 |
|
T35 |
88 |
|
T38 |
6 |
higher_val |
higher_val |
auto[1] |
21594 |
1 |
|
|
T4 |
17 |
|
T5 |
16 |
|
T6 |
3 |
higher_val |
lower_val |
auto[0] |
43616 |
1 |
|
|
T32 |
114 |
|
T35 |
101 |
|
T38 |
13 |
higher_val |
lower_val |
auto[1] |
21913 |
1 |
|
|
T4 |
14 |
|
T5 |
24 |
|
T6 |
6 |
higher_val |
zero_val |
auto[0] |
84 |
1 |
|
|
T41 |
1 |
|
T15 |
2 |
|
T17 |
2 |
higher_val |
zero_val |
auto[1] |
43194 |
1 |
|
|
T4 |
30 |
|
T5 |
34 |
|
T6 |
13 |
lower_val |
higher_val |
auto[0] |
43542 |
1 |
|
|
T32 |
84 |
|
T33 |
1 |
|
T35 |
95 |
lower_val |
higher_val |
auto[1] |
21552 |
1 |
|
|
T4 |
12 |
|
T5 |
22 |
|
T6 |
5 |
lower_val |
lower_val |
auto[0] |
42903 |
1 |
|
|
T32 |
90 |
|
T35 |
99 |
|
T37 |
1 |
lower_val |
lower_val |
auto[1] |
21689 |
1 |
|
|
T4 |
19 |
|
T5 |
22 |
|
T6 |
11 |
lower_val |
zero_val |
auto[0] |
128 |
1 |
|
|
T10 |
1 |
|
T36 |
1 |
|
T59 |
1 |
lower_val |
zero_val |
auto[1] |
43398 |
1 |
|
|
T4 |
25 |
|
T5 |
46 |
|
T6 |
9 |
zero_val |
higher_val |
auto[0] |
563 |
1 |
|
|
T33 |
1 |
|
T39 |
1 |
|
T168 |
4 |
zero_val |
higher_val |
auto[1] |
196 |
1 |
|
|
T33 |
1 |
|
T34 |
1 |
|
T44 |
2 |
zero_val |
lower_val |
auto[0] |
629 |
1 |
|
|
T4 |
1 |
|
T6 |
1 |
|
T32 |
1 |
zero_val |
lower_val |
auto[1] |
184 |
1 |
|
|
T10 |
2 |
|
T33 |
1 |
|
T34 |
2 |
zero_val |
zero_val |
auto[0] |
300 |
1 |
|
|
T5 |
1 |
|
T11 |
1 |
|
T10 |
1 |
zero_val |
zero_val |
auto[1] |
242 |
1 |
|
|
T33 |
4 |
|
T34 |
5 |
|
T94 |
1 |