Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10183	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9240	1			T32	17		T33	30		T34	30
len_5001_7500	14965	1			T32	17		T33	30		T34	30
len_2501_5000	9352	1			T32	17		T33	30		T34	30
len_1025_2500	5463	1			T32	10		T33	16		T34	16
len_769_1024	6634	1			T4	17		T6	7		T32	2
len_513_768	6981	1			T4	16		T6	8		T32	2
len_257_512	21161	1			T4	19		T6	5		T32	2
len_0_256	257520	1			T4	19		T5	176		T6	11
len_keccak_block_sizes[72]	715	1			T32	2		T33	3		T34	3
len_keccak_block_sizes[104]	612	1			T32	2		T33	3		T34	3
len_keccak_block_sizes[136]	518	1			T32	2		T33	3		T34	3
len_keccak_block_sizes[144]	418	1			T32	2		T33	3		T34	3
len_keccak_block_sizes[168]	320	1			T33	3		T34	3		T168	3
len_1	757	1			T32	2		T33	3		T34	3
len_0	1286	1			T5	2		T32	2		T33	3