Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99780429	1			T3	7		T63	8		T67	1
all_pins[1]	99780429	1			T3	7		T63	8		T67	1
all_pins[2]	99780429	1			T3	7		T63	8		T67	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	247954342	1			T3	15		T63	19		T67	3
values[0x1]	51386945	1			T3	6		T63	5		T69	5
transitions[0x0=>0x1]	50971961	1			T3	3		T63	2		T69	3
transitions[0x1=>0x0]	50971992	1			T3	3		T63	2		T69	3

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99270327	1			T3	4		T63	7		T67	1
all_pins[0]	values[0x1]	510102	1			T3	3		T63	1		T69	1
all_pins[0]	transitions[0x0=>0x1]	213613	1			T3	2		T63	1		T155	2
all_pins[0]	transitions[0x1=>0x0]	50270744	1			T63	2		T69	2		T74	5
all_pins[1]	values[0x0]	49213196	1			T3	6		T63	6		T67	1
all_pins[1]	values[0x1]	50567233	1			T3	1		T63	2		T69	3
all_pins[1]	transitions[0x0=>0x1]	50450560	1			T69	2		T74	5		T155	2
all_pins[1]	transitions[0x1=>0x0]	192937	1			T3	1		T74	1		T155	2
all_pins[2]	values[0x0]	99470819	1			T3	5		T63	6		T67	1
all_pins[2]	values[0x1]	309610	1			T3	2		T63	2		T69	1
all_pins[2]	transitions[0x0=>0x1]	307788	1			T3	1		T63	1		T69	1
all_pins[2]	transitions[0x1=>0x0]	508311	1			T3	2		T69	1		T155	3