Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	726	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5909	1			T4	16		T6	7		T10	19
len_601_800	13631	1			T4	21		T6	8		T10	51
len_401_600	9056	1			T4	16		T6	12		T10	34
len_201_400	16729	1			T4	11		T6	3		T10	14
len_65_200	73639	1			T4	1		T5	80		T10	10
len_min_for_xof_require_squeeze	1006	1			T10	1		T33	9		T34	9
len_keccak_block_sizes[72]	742	1			T5	2		T33	9		T34	9
len_keccak_block_sizes[104]	750	1			T5	2		T10	1		T33	9
len_keccak_block_sizes[136]	744	1			T5	1		T33	9		T34	9
len_keccak_block_sizes[144]	286	1			T169	5		T30	5		T170	5
len_keccak_block_sizes[168]	282	1			T169	5		T171	1		T30	5
len_datapath_width	14513	1			T5	8		T10	1		T33	9
len_2_63	213009	1			T4	41		T5	87		T6	25
len_1	65	1			T5	1		T172	1		T17	2