Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11270500 |
1 |
|
|
T4 |
13667 |
|
T5 |
5894 |
|
T6 |
6032 |
auto[1] |
11270097 |
1 |
|
|
T4 |
13667 |
|
T5 |
5894 |
|
T6 |
6032 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
22298483 |
1 |
|
|
T4 |
27230 |
|
T5 |
11558 |
|
T6 |
12028 |
triple_byte_access |
80411 |
1 |
|
|
T4 |
26 |
|
T5 |
72 |
|
T6 |
10 |
halfword_access |
81521 |
1 |
|
|
T4 |
38 |
|
T5 |
70 |
|
T6 |
14 |
byte_access |
80182 |
1 |
|
|
T4 |
40 |
|
T5 |
88 |
|
T6 |
12 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
11149442 |
1 |
|
|
T4 |
13615 |
|
T5 |
5779 |
|
T6 |
6014 |
auto[0] |
triple_byte_access |
40206 |
1 |
|
|
T4 |
13 |
|
T5 |
36 |
|
T6 |
5 |
auto[0] |
halfword_access |
40761 |
1 |
|
|
T4 |
19 |
|
T5 |
35 |
|
T6 |
7 |
auto[0] |
byte_access |
40091 |
1 |
|
|
T4 |
20 |
|
T5 |
44 |
|
T6 |
6 |
auto[1] |
word_access |
11149041 |
1 |
|
|
T4 |
13615 |
|
T5 |
5779 |
|
T6 |
6014 |
auto[1] |
triple_byte_access |
40205 |
1 |
|
|
T4 |
13 |
|
T5 |
36 |
|
T6 |
5 |
auto[1] |
halfword_access |
40760 |
1 |
|
|
T4 |
19 |
|
T5 |
35 |
|
T6 |
7 |
auto[1] |
byte_access |
40091 |
1 |
|
|
T4 |
20 |
|
T5 |
44 |
|
T6 |
6 |