Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 278 1 T3 7 T63 7 T69 7
all_values[1] 278 1 T3 7 T63 7 T69 7
all_values[2] 278 1 T3 7 T63 7 T69 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 477 1 T3 10 T63 11 T69 12
auto[1] 357 1 T3 11 T63 10 T69 9


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 333 1 T3 7 T63 10 T69 4
auto[1] 501 1 T3 14 T63 11 T69 17


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 491 1 T3 10 T63 15 T69 10
auto[1] 343 1 T3 11 T63 6 T69 11


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 58 1 T3 1 T63 2 T74 4
all_values[0] auto[0] auto[0] auto[1] 30 1 T69 1 T161 3 T162 2
all_values[0] auto[0] auto[1] auto[0] 55 1 T3 1 T63 2 T69 1
all_values[0] auto[0] auto[1] auto[1] 18 1 T3 1 T63 2 T155 3
all_values[0] auto[1] auto[0] auto[1] 71 1 T3 1 T63 1 T69 4
all_values[0] auto[1] auto[1] auto[1] 46 1 T3 3 T69 1 T74 1
all_values[1] auto[0] auto[0] auto[0] 64 1 T3 1 T63 2 T69 1
all_values[1] auto[0] auto[0] auto[1] 32 1 T69 3 T155 2 T161 3
all_values[1] auto[0] auto[1] auto[0] 43 1 T3 3 T63 1 T74 1
all_values[1] auto[0] auto[1] auto[1] 25 1 T63 1 T69 1 T74 2
all_values[1] auto[1] auto[0] auto[1] 63 1 T3 2 T63 2 T155 1
all_values[1] auto[1] auto[1] auto[1] 51 1 T3 1 T63 1 T69 2
all_values[2] auto[0] auto[0] auto[0] 64 1 T3 1 T63 1 T74 1
all_values[2] auto[0] auto[0] auto[1] 29 1 T3 2 T63 1 T74 1
all_values[2] auto[0] auto[1] auto[0] 49 1 T63 2 T69 2 T74 1
all_values[2] auto[0] auto[1] auto[1] 24 1 T63 1 T69 1 T155 2
all_values[2] auto[1] auto[0] auto[1] 66 1 T3 2 T63 2 T69 3
all_values[2] auto[1] auto[1] auto[1] 46 1 T3 2 T69 1 T155 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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