Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
95958163 |
1 |
|
|
T57 |
8 |
|
T66 |
4 |
|
T115 |
5 |
all_values[1] |
95958163 |
1 |
|
|
T57 |
8 |
|
T66 |
4 |
|
T115 |
5 |
all_values[2] |
95958163 |
1 |
|
|
T57 |
8 |
|
T66 |
4 |
|
T115 |
5 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
667090 |
1 |
|
|
T57 |
11 |
|
T66 |
6 |
|
T115 |
10 |
auto[1] |
287207399 |
1 |
|
|
T57 |
13 |
|
T66 |
6 |
|
T115 |
5 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
286407900 |
1 |
|
|
T57 |
9 |
|
T66 |
6 |
|
T115 |
15 |
auto[1] |
1466589 |
1 |
|
|
T57 |
15 |
|
T66 |
6 |
|
T100 |
9 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
12 |
0 |
12 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
222563 |
1 |
|
|
T57 |
1 |
|
T66 |
2 |
|
T115 |
3 |
all_values[0] |
auto[0] |
auto[1] |
2177 |
1 |
|
|
T57 |
4 |
|
T66 |
1 |
|
T100 |
2 |
all_values[0] |
auto[1] |
auto[0] |
95246737 |
1 |
|
|
T57 |
2 |
|
T115 |
2 |
|
T100 |
1 |
all_values[0] |
auto[1] |
auto[1] |
486686 |
1 |
|
|
T57 |
1 |
|
T66 |
1 |
|
T100 |
1 |
all_values[1] |
auto[0] |
auto[0] |
247437 |
1 |
|
|
T57 |
1 |
|
T115 |
5 |
|
T100 |
4 |
all_values[1] |
auto[0] |
auto[1] |
1665 |
1 |
|
|
T57 |
4 |
|
T66 |
1 |
|
T100 |
2 |
all_values[1] |
auto[1] |
auto[0] |
95221863 |
1 |
|
|
T57 |
2 |
|
T66 |
2 |
|
T100 |
1 |
all_values[1] |
auto[1] |
auto[1] |
487198 |
1 |
|
|
T57 |
1 |
|
T66 |
1 |
|
T100 |
1 |
all_values[2] |
auto[0] |
auto[0] |
191615 |
1 |
|
|
T115 |
2 |
|
T100 |
1 |
|
T141 |
1 |
all_values[2] |
auto[0] |
auto[1] |
1633 |
1 |
|
|
T57 |
1 |
|
T66 |
2 |
|
T141 |
3 |
all_values[2] |
auto[1] |
auto[0] |
95277685 |
1 |
|
|
T57 |
3 |
|
T66 |
2 |
|
T115 |
3 |
all_values[2] |
auto[1] |
auto[1] |
487230 |
1 |
|
|
T57 |
4 |
|
T100 |
3 |
|
T141 |
2 |