Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00
Crosses 12 0 12 100.00


Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_cg_cc 12 0 12 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 95958163 1 T57 8 T66 4 T115 5
all_values[1] 95958163 1 T57 8 T66 4 T115 5
all_values[2] 95958163 1 T57 8 T66 4 T115 5



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 667090 1 T57 11 T66 6 T115 10
auto[1] 287207399 1 T57 13 T66 6 T115 5



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 286407900 1 T57 9 T66 6 T115 15
auto[1] 1466589 1 T57 15 T66 6 T100 9



Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 12 0 12 100.00


Automatically Generated Cross Bins for intr_cg_cc

Bins
cp_intrcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] 222563 1 T57 1 T66 2 T115 3
all_values[0] auto[0] auto[1] 2177 1 T57 4 T66 1 T100 2
all_values[0] auto[1] auto[0] 95246737 1 T57 2 T115 2 T100 1
all_values[0] auto[1] auto[1] 486686 1 T57 1 T66 1 T100 1
all_values[1] auto[0] auto[0] 247437 1 T57 1 T115 5 T100 4
all_values[1] auto[0] auto[1] 1665 1 T57 4 T66 1 T100 2
all_values[1] auto[1] auto[0] 95221863 1 T57 2 T66 2 T100 1
all_values[1] auto[1] auto[1] 487198 1 T57 1 T66 1 T100 1
all_values[2] auto[0] auto[0] 191615 1 T115 2 T100 1 T141 1
all_values[2] auto[0] auto[1] 1633 1 T57 1 T66 2 T141 3
all_values[2] auto[1] auto[0] 95277685 1 T57 3 T66 2 T115 3
all_values[2] auto[1] auto[1] 487230 1 T57 4 T100 3 T141 2

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