Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
317140 |
1 |
|
|
T4 |
2 |
|
T5 |
492 |
|
T6 |
2 |
auto[1] |
349842 |
1 |
|
|
T4 |
210 |
|
T6 |
196 |
|
T32 |
376 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
166390 |
1 |
|
|
T4 |
55 |
|
T5 |
96 |
|
T6 |
50 |
lower_val |
165360 |
1 |
|
|
T4 |
58 |
|
T5 |
153 |
|
T6 |
41 |
zero_val |
1955 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
245252 |
1 |
|
|
T4 |
62 |
|
T5 |
242 |
|
T6 |
44 |
lower_val |
246514 |
1 |
|
|
T4 |
46 |
|
T5 |
250 |
|
T6 |
46 |
zero_val |
175216 |
1 |
|
|
T4 |
104 |
|
T6 |
108 |
|
T32 |
188 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
39298 |
1 |
|
|
T5 |
47 |
|
T10 |
44 |
|
T34 |
1 |
higher_val |
higher_val |
auto[1] |
21985 |
1 |
|
|
T4 |
13 |
|
T6 |
10 |
|
T32 |
29 |
higher_val |
lower_val |
auto[0] |
39200 |
1 |
|
|
T5 |
49 |
|
T10 |
40 |
|
T34 |
2 |
higher_val |
lower_val |
auto[1] |
21966 |
1 |
|
|
T4 |
15 |
|
T6 |
10 |
|
T32 |
44 |
higher_val |
zero_val |
auto[0] |
106 |
1 |
|
|
T13 |
2 |
|
T76 |
1 |
|
T156 |
1 |
higher_val |
zero_val |
auto[1] |
43835 |
1 |
|
|
T4 |
27 |
|
T6 |
30 |
|
T32 |
52 |
lower_val |
higher_val |
auto[0] |
39494 |
1 |
|
|
T4 |
1 |
|
T5 |
66 |
|
T6 |
1 |
lower_val |
higher_val |
auto[1] |
21445 |
1 |
|
|
T4 |
21 |
|
T6 |
12 |
|
T32 |
8 |
lower_val |
lower_val |
auto[0] |
39690 |
1 |
|
|
T5 |
87 |
|
T10 |
44 |
|
T33 |
1 |
lower_val |
lower_val |
auto[1] |
21577 |
1 |
|
|
T4 |
12 |
|
T6 |
8 |
|
T32 |
17 |
lower_val |
zero_val |
auto[0] |
100 |
1 |
|
|
T42 |
1 |
|
T13 |
1 |
|
T26 |
1 |
lower_val |
zero_val |
auto[1] |
43054 |
1 |
|
|
T4 |
24 |
|
T6 |
20 |
|
T32 |
49 |
zero_val |
higher_val |
auto[0] |
563 |
1 |
|
|
T4 |
1 |
|
T6 |
1 |
|
T35 |
1 |
zero_val |
higher_val |
auto[1] |
164 |
1 |
|
|
T33 |
3 |
|
T13 |
2 |
|
T43 |
2 |
zero_val |
lower_val |
auto[0] |
565 |
1 |
|
|
T5 |
1 |
|
T32 |
1 |
|
T10 |
1 |
zero_val |
lower_val |
auto[1] |
159 |
1 |
|
|
T33 |
1 |
|
T13 |
3 |
|
T43 |
1 |
zero_val |
zero_val |
auto[0] |
280 |
1 |
|
|
T42 |
1 |
|
T41 |
1 |
|
T25 |
1 |
zero_val |
zero_val |
auto[1] |
224 |
1 |
|
|
T13 |
1 |
|
T26 |
1 |
|
T43 |
5 |