Group : kmac_env_pkg::kmac_env_cov::msg_len_cg
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Group : kmac_env_pkg::kmac_env_cov::msg_len_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 0 15 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
msg_len 15 0 15 100.00 100 1 1 0


Summary for Variable msg_len

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 0 15 100.00


User Defined Bins for msg_len

Excluded/Illegal bins
NAMECOUNTSTATUS
remainder 9771 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
len_7501_10000 8784 1 T33 38 T157 30 T40 2
len_5001_7500 14166 1 T5 33 T33 36 T42 33
len_2501_5000 8850 1 T5 34 T33 36 T42 34
len_1025_2500 5147 1 T5 20 T33 22 T42 20
len_769_1024 6525 1 T4 12 T5 4 T6 18
len_513_768 7021 1 T4 20 T5 3 T6 17
len_257_512 20767 1 T4 18 T5 4 T6 11
len_0_256 245168 1 T4 25 T5 148 T6 17
len_keccak_block_sizes[72] 682 1 T5 2 T33 3 T42 2
len_keccak_block_sizes[104] 593 1 T33 3 T157 3 T43 3
len_keccak_block_sizes[136] 500 1 T33 3 T157 3 T41 1
len_keccak_block_sizes[144] 393 1 T33 3 T157 3 T13 1
len_keccak_block_sizes[168] 305 1 T33 3 T157 3 T43 3
len_1 733 1 T5 2 T33 3 T42 2
len_0 1231 1 T5 2 T33 3 T38 1

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