Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	95958163	1			T57	8		T66	4		T115	5
all_pins[1]	95958163	1			T57	8		T66	4		T115	5
all_pins[2]	95958163	1			T57	8		T66	4		T115	5

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	238842275	1			T57	15		T66	10		T115	13
values[0x1]	49032214	1			T57	9		T66	2		T115	2
transitions[0x0=>0x1]	48610719	1			T57	5		T66	2		T115	2
transitions[0x1=>0x0]	48610746	1			T57	6		T66	2		T115	2

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	95471477	1			T57	7		T66	3		T115	5
all_pins[0]	values[0x1]	486686	1			T57	1		T66	1		T100	1
all_pins[0]	transitions[0x0=>0x1]	202545	1			T57	1		T66	1		T100	1
all_pins[0]	transitions[0x1=>0x0]	47912130	1			T57	2		T66	1		T100	2
all_pins[1]	values[0x0]	47761892	1			T57	6		T66	3		T115	5
all_pins[1]	values[0x1]	48196271	1			T57	2		T66	1		T100	2
all_pins[1]	transitions[0x0=>0x1]	48061047	1			T66	1		T141	1		T142	1
all_pins[1]	transitions[0x1=>0x0]	214033	1			T57	4		T115	2		T100	4
all_pins[2]	values[0x0]	95608906	1			T57	2		T66	4		T115	3
all_pins[2]	values[0x1]	349257	1			T57	6		T115	2		T100	6
all_pins[2]	transitions[0x0=>0x1]	347127	1			T57	4		T115	2		T100	5
all_pins[2]	transitions[0x1=>0x0]	484583	1			T66	1		T141	2		T142	1