Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	692	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5822	1			T4	18		T6	8		T10	27
len_601_800	13023	1			T4	22		T6	26		T10	46
len_401_600	8719	1			T4	20		T6	12		T10	23
len_201_400	15468	1			T4	10		T6	10		T10	7
len_65_200	70225	1			T4	3		T6	3		T10	3
len_min_for_xof_require_squeeze	956	1			T10	1		T33	10		T157	9
len_keccak_block_sizes[72]	722	1			T33	5		T157	9		T43	9
len_keccak_block_sizes[104]	723	1			T33	5		T157	9		T29	1
len_keccak_block_sizes[136]	725	1			T33	5		T157	9		T43	9
len_keccak_block_sizes[144]	257	1			T33	5		T158	5		T159	2
len_keccak_block_sizes[168]	275	1			T33	5		T29	1		T158	5
len_datapath_width	14146	1			T5	246		T6	1		T33	5
len_2_63	203478	1			T4	32		T6	39		T32	96
len_1	67	1			T93	2		T159	1		T160	1