Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10805353 |
1 |
|
|
T4 |
14147 |
|
T5 |
3936 |
|
T6 |
10915 |
auto[1] |
10805202 |
1 |
|
|
T4 |
14147 |
|
T5 |
3936 |
|
T6 |
10915 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21379370 |
1 |
|
|
T4 |
28184 |
|
T5 |
7872 |
|
T6 |
21750 |
triple_byte_access |
76794 |
1 |
|
|
T4 |
40 |
|
T6 |
32 |
|
T10 |
48 |
halfword_access |
77428 |
1 |
|
|
T4 |
30 |
|
T6 |
20 |
|
T10 |
58 |
byte_access |
76963 |
1 |
|
|
T4 |
40 |
|
T6 |
28 |
|
T10 |
60 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10689760 |
1 |
|
|
T4 |
14092 |
|
T5 |
3936 |
|
T6 |
10875 |
auto[0] |
triple_byte_access |
38397 |
1 |
|
|
T4 |
20 |
|
T6 |
16 |
|
T10 |
24 |
auto[0] |
halfword_access |
38714 |
1 |
|
|
T4 |
15 |
|
T6 |
10 |
|
T10 |
29 |
auto[0] |
byte_access |
38482 |
1 |
|
|
T4 |
20 |
|
T6 |
14 |
|
T10 |
30 |
auto[1] |
word_access |
10689610 |
1 |
|
|
T4 |
14092 |
|
T5 |
3936 |
|
T6 |
10875 |
auto[1] |
triple_byte_access |
38397 |
1 |
|
|
T4 |
20 |
|
T6 |
16 |
|
T10 |
24 |
auto[1] |
halfword_access |
38714 |
1 |
|
|
T4 |
15 |
|
T6 |
10 |
|
T10 |
29 |
auto[1] |
byte_access |
38481 |
1 |
|
|
T4 |
20 |
|
T6 |
14 |
|
T10 |
30 |