Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 290 1 T57 7 T66 4 T115 4
all_values[1] 290 1 T57 7 T66 4 T115 4
all_values[2] 290 1 T57 7 T66 4 T115 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 443 1 T57 10 T66 7 T115 8
auto[1] 427 1 T57 11 T66 5 T115 4


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 323 1 T57 4 T66 8 T115 8
auto[1] 547 1 T57 17 T66 4 T115 4


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 511 1 T57 9 T66 8 T115 9
auto[1] 359 1 T57 12 T66 4 T115 3


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 50 1 T57 1 T66 1 T115 1
all_values[0] auto[0] auto[0] auto[1] 31 1 T57 2 T141 2 T136 1
all_values[0] auto[0] auto[1] auto[0] 50 1 T57 1 T66 1 T115 3
all_values[0] auto[0] auto[1] auto[1] 41 1 T100 1 T141 2 T142 2
all_values[0] auto[1] auto[0] auto[1] 55 1 T57 1 T66 1 T100 1
all_values[0] auto[1] auto[1] auto[1] 63 1 T57 2 T66 1 T100 2
all_values[1] auto[0] auto[0] auto[0] 59 1 T57 2 T66 2 T115 2
all_values[1] auto[0] auto[0] auto[1] 23 1 T57 1 T142 1 T136 1
all_values[1] auto[0] auto[1] auto[0] 53 1 T66 1 T142 1 T143 4
all_values[1] auto[0] auto[1] auto[1] 32 1 T141 2 T142 2 T144 2
all_values[1] auto[1] auto[0] auto[1] 69 1 T57 1 T115 2 T100 3
all_values[1] auto[1] auto[1] auto[1] 54 1 T57 3 T66 1 T100 2
all_values[2] auto[0] auto[0] auto[0] 66 1 T66 2 T115 2 T100 1
all_values[2] auto[0] auto[0] auto[1] 27 1 T141 2 T143 2 T145 2
all_values[2] auto[0] auto[1] auto[0] 45 1 T66 1 T142 1 T144 3
all_values[2] auto[0] auto[1] auto[1] 34 1 T57 2 T115 1 T100 2
all_values[2] auto[1] auto[0] auto[1] 63 1 T57 2 T66 1 T115 1
all_values[2] auto[1] auto[1] auto[1] 55 1 T57 3 T100 3 T142 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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