Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100431237	1			T47	8		T51	5		T53	1
all_values[1]	100431237	1			T47	8		T51	5		T53	1
all_values[2]	100431237	1			T47	8		T51	5		T53	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

625176

1

T47

21

T51

10

T53

3

auto[1]

300668535

1

T47

3

T51

5

T101

11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299748246

1

T47

12

T51

6

T53

3

auto[1]

1545465

1

T47

12

T51

9

T101

9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	206865	1			T47	4		T51	2		T53	1
all_values[0]	auto[0]	auto[1]	2401	1			T47	2		T51	3		T101	2
all_values[0]	auto[1]	auto[0]	99709217	1			T101	4		T102	1		T138	2
all_values[0]	auto[1]	auto[1]	512754	1			T47	2		T101	1		T102	1
all_values[1]	auto[0]	auto[0]	193452	1			T47	4		T53	1		T54	1
all_values[1]	auto[0]	auto[1]	1793	1			T47	3		T101	1		T102	2
all_values[1]	auto[1]	auto[0]	99722630	1			T51	2		T101	2		T139	3
all_values[1]	auto[1]	auto[1]	513362	1			T47	1		T51	3		T101	2
all_values[2]	auto[0]	auto[0]	218805	1			T47	4		T51	2		T53	1
all_values[2]	auto[0]	auto[1]	1860	1			T47	4		T51	3		T101	2
all_values[2]	auto[1]	auto[0]	99697277	1			T101	1		T102	3		T139	1
all_values[2]	auto[1]	auto[1]	513295	1			T101	1		T102	2		T138	2