Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10267	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9225	1			T5	17		T12	2		T23	30
len_5001_7500	14879	1			T5	34		T12	2		T23	30
len_2501_5000	9257	1			T5	6		T23	30		T24	24
len_1025_2500	5458	1			T5	1		T23	16		T24	14
len_769_1024	6721	1			T4	6		T6	16		T12	38
len_513_768	7341	1			T4	9		T5	2		T6	18
len_257_512	21526	1			T4	7		T6	17		T10	2
len_0_256	258637	1			T4	12		T5	10		T6	18
len_keccak_block_sizes[72]	716	1			T23	3		T24	2		T26	2
len_keccak_block_sizes[104]	629	1			T23	3		T24	2		T26	2
len_keccak_block_sizes[136]	522	1			T23	3		T26	2		T32	3
len_keccak_block_sizes[144]	415	1			T23	3		T32	3		T87	3
len_keccak_block_sizes[168]	318	1			T23	3		T32	3		T87	3
len_1	751	1			T23	3		T24	2		T26	2
len_0	1238	1			T5	2		T12	2		T23	3