Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100431237	1			T47	8		T51	5		T53	1
all_pins[1]	100431237	1			T47	8		T51	5		T53	1
all_pins[2]	100431237	1			T47	8		T51	5		T53	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	249539040	1			T47	22		T51	13		T53	3
values[0x1]	51754671	1			T47	2		T51	2		T101	5
transitions[0x0=>0x1]	51294389	1			T47	2		T51	2		T101	4
transitions[0x1=>0x0]	51294408	1			T47	2		T51	2		T101	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99918483	1			T47	6		T51	5		T53	1
all_pins[0]	values[0x1]	512754	1			T47	2		T101	1		T102	1
all_pins[0]	transitions[0x0=>0x1]	215135	1			T47	2		T101	1		T102	1
all_pins[0]	transitions[0x1=>0x0]	50539779	1			T51	2		T101	2		T102	1
all_pins[1]	values[0x0]	49593839	1			T47	8		T51	3		T53	1
all_pins[1]	values[0x1]	50837398	1			T51	2		T101	2		T102	1
all_pins[1]	transitions[0x0=>0x1]	50677288	1			T51	2		T101	1		T102	1
all_pins[1]	transitions[0x1=>0x0]	244409	1			T101	1		T102	2		T138	2
all_pins[2]	values[0x0]	100026718	1			T47	8		T51	5		T53	1
all_pins[2]	values[0x1]	404519	1			T101	2		T102	2		T138	2
all_pins[2]	transitions[0x0=>0x1]	401966	1			T101	2		T102	1		T138	1
all_pins[2]	transitions[0x1=>0x0]	510220	1			T47	2		T101	1		T102	1