Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	771	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	6126	1			T4	3		T5	9		T6	9
len_601_800	13614	1			T4	12		T5	27		T6	23
len_401_600	9070	1			T4	5		T5	19		T6	15
len_201_400	16861	1			T4	4		T5	7		T6	7
len_65_200	73944	1			T4	2		T5	3		T6	1
len_min_for_xof_require_squeeze	1010	1			T5	1		T23	9		T13	1
len_keccak_block_sizes[72]	743	1			T12	2		T23	9		T32	5
len_keccak_block_sizes[104]	740	1			T23	9		T32	5		T87	9
len_keccak_block_sizes[136]	760	1			T12	3		T23	9		T32	5
len_keccak_block_sizes[144]	286	1			T32	5		T153	5		T154	5
len_keccak_block_sizes[168]	284	1			T12	1		T32	5		T14	1
len_datapath_width	14456	1			T5	1		T12	12		T23	9
len_2_63	214551	1			T4	1		T5	4		T6	8
len_1	54	1			T12	1		T15	1		T17	1