Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 293 1 T47 7 T51 4 T101 7
all_values[1] 293 1 T47 7 T51 4 T101 7
all_values[2] 293 1 T47 7 T51 4 T101 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 490 1 T47 19 T51 9 T101 12
auto[1] 389 1 T47 2 T51 3 T101 9


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 352 1 T47 4 T51 5 T101 7
auto[1] 527 1 T47 17 T51 7 T101 14


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 512 1 T47 10 T51 7 T101 12
auto[1] 367 1 T47 11 T51 5 T101 9


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 62 1 T47 2 T51 1 T101 1
all_values[0] auto[0] auto[0] auto[1] 28 1 T47 2 T51 1 T101 2
all_values[0] auto[0] auto[1] auto[0] 49 1 T101 2 T102 1 T139 1
all_values[0] auto[0] auto[1] auto[1] 33 1 T140 1 T141 2 T124 1
all_values[0] auto[1] auto[0] auto[1] 66 1 T47 2 T51 2 T101 2
all_values[0] auto[1] auto[1] auto[1] 55 1 T47 1 T102 1 T138 1
all_values[1] auto[0] auto[0] auto[0] 72 1 T51 1 T101 2 T102 5
all_values[1] auto[0] auto[0] auto[1] 26 1 T47 3 T142 1 T143 1
all_values[1] auto[0] auto[1] auto[0] 49 1 T51 1 T101 1 T138 5
all_values[1] auto[0] auto[1] auto[1] 21 1 T51 1 T101 2 T139 1
all_values[1] auto[1] auto[0] auto[1] 65 1 T47 3 T101 1 T102 1
all_values[1] auto[1] auto[1] auto[1] 60 1 T47 1 T51 1 T101 1
all_values[2] auto[0] auto[0] auto[0] 73 1 T47 2 T51 2 T101 1
all_values[2] auto[0] auto[0] auto[1] 29 1 T47 1 T101 1 T144 1
all_values[2] auto[0] auto[1] auto[0] 47 1 T102 3 T138 3 T144 2
all_values[2] auto[0] auto[1] auto[1] 23 1 T138 1 T141 1 T145 1
all_values[2] auto[1] auto[0] auto[1] 69 1 T47 4 T51 2 T101 2
all_values[2] auto[1] auto[1] auto[1] 52 1 T101 3 T102 2 T138 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%