Unified Coverage Report :: Tests

Tests

dashboard | hierarchy | modlist | groups | tests | asserts

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.16	98.38	93.14	99.93	95.45	96.04	98.89	98.31

Total test records in report: 1264

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T1251	/workspace/coverage/cover_reg_top/6.kmac_intr_test.3650985191			Feb 04 12:40:04 PM PST 24	Feb 04 12:40:15 PM PST 24	80410620 ps
T1252	/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3714639588			Feb 04 12:39:53 PM PST 24	Feb 04 12:39:56 PM PST 24	243458158 ps
T1253	/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3391642446			Feb 04 12:39:56 PM PST 24	Feb 04 12:40:02 PM PST 24	222779926 ps
T1254	/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.4006140056			Feb 04 12:40:12 PM PST 24	Feb 04 12:40:30 PM PST 24	324574205 ps
T1255	/workspace/coverage/cover_reg_top/2.kmac_intr_test.3204646931			Feb 04 12:39:59 PM PST 24	Feb 04 12:40:06 PM PST 24	47438073 ps
T1256	/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2018770305			Feb 04 12:40:16 PM PST 24	Feb 04 12:40:31 PM PST 24	114071014 ps
T1257	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.537844871			Feb 04 12:39:55 PM PST 24	Feb 04 12:39:57 PM PST 24	79254636 ps
T1258	/workspace/coverage/cover_reg_top/14.kmac_tl_errors.2920673607			Feb 04 12:39:58 PM PST 24	Feb 04 12:40:06 PM PST 24	146639683 ps
T1259	/workspace/coverage/cover_reg_top/0.kmac_intr_test.126054053			Feb 04 12:39:47 PM PST 24	Feb 04 12:39:51 PM PST 24	24402946 ps
T1260	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1074045383			Feb 04 12:40:05 PM PST 24	Feb 04 12:40:20 PM PST 24	92753348 ps
T1261	/workspace/coverage/cover_reg_top/3.kmac_mem_walk.862041990			Feb 04 12:39:56 PM PST 24	Feb 04 12:39:58 PM PST 24	11141682 ps
T1262	/workspace/coverage/cover_reg_top/6.kmac_csr_rw.1514564981			Feb 04 12:39:58 PM PST 24	Feb 04 12:40:04 PM PST 24	134558330 ps
T1263	/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.479405630			Feb 04 12:40:17 PM PST 24	Feb 04 12:40:30 PM PST 24	199498374 ps
T1264	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2624780559			Feb 04 12:40:10 PM PST 24	Feb 04 12:40:27 PM PST 24	109267698 ps

Test location	/workspace/coverage/default/5.kmac_stress_all.2390038730
Short name	T12
Test name
Test status
Simulation time	74466617253 ps
CPU time	598.09 seconds
Started	Feb 04 02:45:13 PM PST 24
Finished	Feb 04 02:55:28 PM PST 24
Peak memory	292996 kb
Host	smart-9c35f0bf-bb6d-478f-a7cf-7bf7042be518
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2390038730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.2390038730 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_rw.2263020458
Short name	T1
Test name
Test status
Simulation time	36578071 ps
CPU time	1.03 seconds
Started	Feb 04 12:39:44 PM PST 24
Finished	Feb 04 12:39:49 PM PST 24
Peak memory	216072 kb
Host	smart-f57b8ddf-6ffa-42da-bb16-49bc12eb0058
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263020458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.2263020458 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.2873909605
Short name	T110
Test name
Test status
Simulation time	253892265 ps
CPU time	5.41 seconds
Started	Feb 04 12:40:12 PM PST 24
Finished	Feb 04 12:40:32 PM PST 24
Peak memory	217296 kb
Host	smart-98d9d423-0e73-4b12-9ddb-d56a2fb3c99d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873909605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.2873 909605 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_errors.2956414158
Short name	T53
Test name
Test status
Simulation time	78197700 ps
CPU time	2.27 seconds
Started	Feb 04 12:40:10 PM PST 24
Finished	Feb 04 12:40:27 PM PST 24
Peak memory	217100 kb
Host	smart-bcc32d56-15c2-46cf-9d5f-19e842ad6d29
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956414158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.2956414158 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_errors/latest

Test location	/workspace/coverage/default/0.kmac_sec_cm.2991794779
Short name	T8
Test name
Test status
Simulation time	4550046450 ps
CPU time	61.89 seconds
Started	Feb 04 02:44:55 PM PST 24
Finished	Feb 04 02:46:18 PM PST 24
Peak memory	270448 kb
Host	smart-225e69a2-3b26-42d7-8b26-5b4867daffb3
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991794779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.2991794779 +enable_maski ng=1 +sw_key_masked=0
Directory	/workspace/0.kmac_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2154863622
Short name	T93
Test name
Test status
Simulation time	47591126 ps
CPU time	1.41 seconds
Started	Feb 04 12:40:10 PM PST 24
Finished	Feb 04 12:40:26 PM PST 24
Peak memory	224672 kb
Host	smart-f2414da2-426a-4b93-a3f3-8ab0ac58694d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154863622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_ errors.2154863622 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/default/12.kmac_stress_all_with_rand_reset.788691959
Short name	T79
Test name
Test status
Simulation time	54768181289 ps
CPU time	1955.31 seconds
Started	Feb 04 02:46:14 PM PST 24
Finished	Feb 04 03:18:51 PM PST 24
Peak memory	355360 kb
Host	smart-5084b54a-e6d3-46a6-be09-db2bcc4eea66
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=788691959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all_with_rand_reset.788691959 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.kmac_error.3691315625
Short name	T4
Test name
Test status
Simulation time	7776702101 ps
CPU time	89.92 seconds
Started	Feb 04 02:49:44 PM PST 24
Finished	Feb 04 02:51:17 PM PST 24
Peak memory	243780 kb
Host	smart-4f162a41-f6c2-4589-b6d6-4601bb598262
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3691315625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.3691315625 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_error/latest

Test location	/workspace/coverage/cover_reg_top/42.kmac_intr_test.3522587453
Short name	T101
Test name
Test status
Simulation time	95733827 ps
CPU time	0.84 seconds
Started	Feb 04 12:40:09 PM PST 24
Finished	Feb 04 12:40:25 PM PST 24
Peak memory	217016 kb
Host	smart-b2d11987-eb86-4ab0-b5fa-1205036a94eb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522587453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.3522587453 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2078586156
Short name	T48
Test name
Test status
Simulation time	152450251 ps
CPU time	1.44 seconds
Started	Feb 04 12:40:06 PM PST 24
Finished	Feb 04 12:40:19 PM PST 24
Peak memory	217612 kb
Host	smart-e05864a1-cb5a-48dd-a861-7b8f7a592b64
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078586156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg _errors.2078586156 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_shake_128.3752922095
Short name	T23
Test name
Test status
Simulation time	1874387679350 ps
CPU time	7006.36 seconds
Started	Feb 04 02:45:52 PM PST 24
Finished	Feb 04 04:42:47 PM PST 24
Peak memory	660508 kb
Host	smart-e9213272-c509-4168-9b10-68b399b8e9b8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3752922095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.3752922095 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.1788714974
Short name	T119
Test name
Test status
Simulation time	38088962 ps
CPU time	1.33 seconds
Started	Feb 04 12:39:59 PM PST 24
Finished	Feb 04 12:40:07 PM PST 24
Peak memory	216356 kb
Host	smart-c83beea6-cc3b-4330-a3d5-0c58abcfab44
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788714974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia l_access.1788714974 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_partial_access/latest

Test location	/workspace/coverage/default/32.kmac_key_error.1627278335
Short name	T37
Test name
Test status
Simulation time	752044869 ps
CPU time	4.9 seconds
Started	Feb 04 02:50:45 PM PST 24
Finished	Feb 04 02:50:51 PM PST 24
Peak memory	218512 kb
Host	smart-bc9d3735-2e2c-44c1-839c-c9f42685c1a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1627278335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.1627278335 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_key_error/latest

Test location	/workspace/coverage/default/28.kmac_entropy_refresh.3686154357
Short name	T33
Test name
Test status
Simulation time	13758532817 ps
CPU time	337.7 seconds
Started	Feb 04 02:49:14 PM PST 24
Finished	Feb 04 02:54:52 PM PST 24
Peak memory	251948 kb
Host	smart-3baf2cd9-079c-4ef7-9ce1-167d0304811b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3686154357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.3686154357 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/28.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/33.kmac_error.301234287
Short name	T45
Test name
Test status
Simulation time	15487086391 ps
CPU time	383.84 seconds
Started	Feb 04 02:51:21 PM PST 24
Finished	Feb 04 02:57:46 PM PST 24
Peak memory	264264 kb
Host	smart-26a5a79c-5418-4701-8d1c-5274ceb17935
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=301234287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.301234287 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_error/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.679515772
Short name	T89
Test name
Test status
Simulation time	65723981 ps
CPU time	2.74 seconds
Started	Feb 04 12:40:11 PM PST 24
Finished	Feb 04 12:40:30 PM PST 24
Peak memory	220308 kb
Host	smart-435701cf-fbc5-4365-adba-c93d29968794
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679515772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac _shadow_reg_errors_with_csr_rw.679515772 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/0.kmac_entropy_ready_error.3176350263
Short name	T41
Test name
Test status
Simulation time	23216665582 ps
CPU time	74.42 seconds
Started	Feb 04 02:44:55 PM PST 24
Finished	Feb 04 02:46:31 PM PST 24
Peak memory	222460 kb
Host	smart-ac049317-2fc8-45bc-9215-c1c400895760
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3176350263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.3176350263 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/0.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/10.kmac_edn_timeout_error.2015004192
Short name	T484
Test name
Test status
Simulation time	52215389 ps
CPU time	0.95 seconds
Started	Feb 04 02:45:49 PM PST 24
Finished	Feb 04 02:45:53 PM PST 24
Peak memory	218332 kb
Host	smart-a3dcea04-d82b-42ac-9e34-9d5c8de3a7e8
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2015004192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.2015004192 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_intr_test.4098617196
Short name	T141
Test name
Test status
Simulation time	20205936 ps
CPU time	0.87 seconds
Started	Feb 04 12:40:15 PM PST 24
Finished	Feb 04 12:40:29 PM PST 24
Peak memory	216964 kb
Host	smart-ef979a60-2f4e-4bb3-bc5a-0478834e315e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098617196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.4098617196 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2487580466
Short name	T150
Test name
Test status
Simulation time	100496730 ps
CPU time	4.4 seconds
Started	Feb 04 12:40:00 PM PST 24
Finished	Feb 04 12:40:12 PM PST 24
Peak memory	217200 kb
Host	smart-053b9d4e-6cda-4464-803e-45aeacbc41c6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487580466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.2487 580466 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1922002841
Short name	T68
Test name
Test status
Simulation time	112330562 ps
CPU time	1.05 seconds
Started	Feb 04 12:40:00 PM PST 24
Finished	Feb 04 12:40:07 PM PST 24
Peak memory	217652 kb
Host	smart-4c1baa31-6970-43b2-abcc-69ae0b1c6e01
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922002841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_ errors.1922002841 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_errors.1846379006
Short name	T58
Test name
Test status
Simulation time	368991297 ps
CPU time	2.92 seconds
Started	Feb 04 12:40:10 PM PST 24
Finished	Feb 04 12:40:29 PM PST 24
Peak memory	216364 kb
Host	smart-c1403eb3-9bfa-42c7-8fee-e3ad5e0a7d94
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846379006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.1846379006 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.2804919814
Short name	T1202
Test name
Test status
Simulation time	1269001173 ps
CPU time	5.84 seconds
Started	Feb 04 12:39:54 PM PST 24
Finished	Feb 04 12:40:00 PM PST 24
Peak memory	217156 kb
Host	smart-b55f5121-fb8a-4d9b-8e1b-74cacf960bf6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804919814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.28049 19814 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_intg_err/latest

Test location	/workspace/coverage/default/0.kmac_entropy_mode_error.794944090
Short name	T630
Test name
Test status
Simulation time	46185377 ps
CPU time	1.3 seconds
Started	Feb 04 02:44:38 PM PST 24
Finished	Feb 04 02:44:44 PM PST 24
Peak memory	218676 kb
Host	smart-ebb4f880-02ce-4280-9120-435fee7c2815
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=794944090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.794944090 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/25.kmac_sideload.4192738256
Short name	T245
Test name
Test status
Simulation time	15692109206 ps
CPU time	532.55 seconds
Started	Feb 04 02:48:06 PM PST 24
Finished	Feb 04 02:57:01 PM PST 24
Peak memory	259504 kb
Host	smart-132eaf4e-eb07-42de-9a13-2ef2748c15fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4192738256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.4192738256 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_sideload/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_intr_test.2542778924
Short name	T1184
Test name
Test status
Simulation time	16133727 ps
CPU time	0.79 seconds
Started	Feb 04 12:40:10 PM PST 24
Finished	Feb 04 12:40:27 PM PST 24
Peak memory	216824 kb
Host	smart-8087a097-d1fb-4d36-8770-b65861b5a9ee
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542778924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.2542778924 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.3890632297
Short name	T146
Test name
Test status
Simulation time	150771548 ps
CPU time	3.15 seconds
Started	Feb 04 12:40:04 PM PST 24
Finished	Feb 04 12:40:18 PM PST 24
Peak memory	216052 kb
Host	smart-a7790172-c414-4a7a-bb32-573e14ec422f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890632297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.38906 32297 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.3091096260
Short name	T152
Test name
Test status
Simulation time	1111623206 ps
CPU time	5.46 seconds
Started	Feb 04 12:40:07 PM PST 24
Finished	Feb 04 12:40:25 PM PST 24
Peak memory	217108 kb
Host	smart-aee35940-54cd-4c7e-b003-ab8bc5dd7ce2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091096260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.30910 96260 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_intg_err/latest

Test location	/workspace/coverage/default/10.kmac_stress_all.4097325902
Short name	T1101
Test name
Test status
Simulation time	66961704746 ps
CPU time	1548.65 seconds
Started	Feb 04 02:45:56 PM PST 24
Finished	Feb 04 03:11:51 PM PST 24
Peak memory	412016 kb
Host	smart-c96bf71a-9ae5-42c5-9ccd-b323f4065bde
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4097325902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.4097325902 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_stress_all/latest

Test location	/workspace/coverage/default/12.kmac_alert_test.109569034
Short name	T97
Test name
Test status
Simulation time	120441368 ps
CPU time	0.86 seconds
Started	Feb 04 02:46:14 PM PST 24
Finished	Feb 04 02:46:16 PM PST 24
Peak memory	218284 kb
Host	smart-65c96c7e-ff3f-424a-8253-fa336e3dcdda
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109569034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.109569034 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_alert_test/latest

Test location	/workspace/coverage/default/15.kmac_lc_escalation.2631329409
Short name	T282
Test name
Test status
Simulation time	86157771 ps
CPU time	1.4 seconds
Started	Feb 04 02:46:28 PM PST 24
Finished	Feb 04 02:46:41 PM PST 24
Peak memory	220156 kb
Host	smart-032f054c-ff6f-4efb-8b23-33e20ba63b86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2631329409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.2631329409 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/15.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/0.kmac_app.76845972
Short name	T43
Test name
Test status
Simulation time	10872808115 ps
CPU time	354.1 seconds
Started	Feb 04 02:44:41 PM PST 24
Finished	Feb 04 02:50:42 PM PST 24
Peak memory	252884 kb
Host	smart-0d85fbd2-7d00-40f8-8879-9690ab47a5bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=76845972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.76845972 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_app/latest

Test location	/workspace/coverage/default/1.kmac_error.2354876491
Short name	T262
Test name
Test status
Simulation time	40598400332 ps
CPU time	487.25 seconds
Started	Feb 04 02:44:55 PM PST 24
Finished	Feb 04 02:53:24 PM PST 24
Peak memory	269252 kb
Host	smart-2304df45-1225-4976-a205-83ba42c0df1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2354876491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.2354876491 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_error/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.3182844095
Short name	T50
Test name
Test status
Simulation time	612773965 ps
CPU time	9.15 seconds
Started	Feb 04 12:39:47 PM PST 24
Finished	Feb 04 12:40:00 PM PST 24
Peak memory	216412 kb
Host	smart-c5914bdd-ce07-4c02-b402-b054493be2cd
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182844095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.3182844 095 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2167272713
Short name	T134
Test name
Test status
Simulation time	810486547 ps
CPU time	12.31 seconds
Started	Feb 04 12:39:47 PM PST 24
Finished	Feb 04 12:40:03 PM PST 24
Peak memory	217192 kb
Host	smart-9d46c57d-1f46-4cd7-a669-88f0cb044ead
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167272713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.2167272 713 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1932343080
Short name	T1152
Test name
Test status
Simulation time	22739770 ps
CPU time	1 seconds
Started	Feb 04 12:39:46 PM PST 24
Finished	Feb 04 12:39:49 PM PST 24
Peak memory	216900 kb
Host	smart-0e280968-76b0-4de3-9604-d12dcdeae7a8
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932343080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1932343 080 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.3299821898
Short name	T60
Test name
Test status
Simulation time	32274946 ps
CPU time	2.14 seconds
Started	Feb 04 12:39:53 PM PST 24
Finished	Feb 04 12:39:56 PM PST 24
Peak memory	223552 kb
Host	smart-188311dd-d280-4be5-bc1b-6a7dd00abd65
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299821898 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.3299821898 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_intr_test.126054053
Short name	T1259
Test name
Test status
Simulation time	24402946 ps
CPU time	0.85 seconds
Started	Feb 04 12:39:47 PM PST 24
Finished	Feb 04 12:39:51 PM PST 24
Peak memory	216812 kb
Host	smart-74c8806e-41f0-443f-b0fa-c89360180fc5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126054053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.126054053 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.2814470092
Short name	T118
Test name
Test status
Simulation time	158057319 ps
CPU time	1.59 seconds
Started	Feb 04 12:39:51 PM PST 24
Finished	Feb 04 12:39:55 PM PST 24
Peak memory	217140 kb
Host	smart-f025eb6d-6fa0-4e20-94e8-d8cf35238094
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814470092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia l_access.2814470092 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_walk.174977319
Short name	T1205
Test name
Test status
Simulation time	22031279 ps
CPU time	0.8 seconds
Started	Feb 04 12:39:46 PM PST 24
Finished	Feb 04 12:39:49 PM PST 24
Peak memory	215928 kb
Host	smart-c696c450-fded-4ef2-b683-db8ff1ab411f
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174977319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.174977319 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3714639588
Short name	T1252
Test name
Test status
Simulation time	243458158 ps
CPU time	1.83 seconds
Started	Feb 04 12:39:53 PM PST 24
Finished	Feb 04 12:39:56 PM PST 24
Peak memory	216144 kb
Host	smart-452605d0-92d4-4cdd-acd4-f3b4252c7b7b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714639588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr _outstanding.3714639588 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1244452270
Short name	T1160
Test name
Test status
Simulation time	49456136 ps
CPU time	1.08 seconds
Started	Feb 04 12:39:54 PM PST 24
Finished	Feb 04 12:39:56 PM PST 24
Peak memory	221584 kb
Host	smart-24f58f66-b352-41b3-919e-f15764770067
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244452270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_ errors.1244452270 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2900896548
Short name	T1161
Test name
Test status
Simulation time	567557220 ps
CPU time	3.39 seconds
Started	Feb 04 12:39:47 PM PST 24
Finished	Feb 04 12:39:52 PM PST 24
Peak memory	220660 kb
Host	smart-389ea453-53c4-4c54-9ad6-bdf6ebf69305
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900896548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac _shadow_reg_errors_with_csr_rw.2900896548 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_errors.3344004419
Short name	T1182
Test name
Test status
Simulation time	87462307 ps
CPU time	2.19 seconds
Started	Feb 04 12:39:47 PM PST 24
Finished	Feb 04 12:39:53 PM PST 24
Peak memory	217300 kb
Host	smart-88bb8216-8948-4057-a377-7e8f8d0fbeda
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344004419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.3344004419 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.228176413
Short name	T128
Test name
Test status
Simulation time	160783286 ps
CPU time	9.63 seconds
Started	Feb 04 12:39:43 PM PST 24
Finished	Feb 04 12:39:58 PM PST 24
Peak memory	216436 kb
Host	smart-bb39ff0d-0957-44f0-9f10-ba3c991956b1
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228176413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.22817641 3 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.3527579800
Short name	T114
Test name
Test status
Simulation time	527723854 ps
CPU time	10.99 seconds
Started	Feb 04 12:39:44 PM PST 24
Finished	Feb 04 12:39:59 PM PST 24
Peak memory	216304 kb
Host	smart-df4d832e-76df-4405-ba3a-540bdc504c35
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527579800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.3527579 800 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.15267198
Short name	T113
Test name
Test status
Simulation time	60644667 ps
CPU time	1.02 seconds
Started	Feb 04 12:39:48 PM PST 24
Finished	Feb 04 12:39:52 PM PST 24
Peak memory	216896 kb
Host	smart-0848b2cf-524c-4853-a179-f50cf5150267
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15267198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.15267198 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.2597627276
Short name	T1155
Test name
Test status
Simulation time	20984640 ps
CPU time	1.62 seconds
Started	Feb 04 12:39:49 PM PST 24
Finished	Feb 04 12:39:53 PM PST 24
Peak memory	218644 kb
Host	smart-9f11401c-db8c-4a9e-bf52-dd22f305248f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597627276 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.2597627276 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_rw.3404916810
Short name	T1169
Test name
Test status
Simulation time	21219691 ps
CPU time	1.14 seconds
Started	Feb 04 12:39:55 PM PST 24
Finished	Feb 04 12:39:58 PM PST 24
Peak memory	217368 kb
Host	smart-b944afea-1621-4250-af67-eaff36c77587
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404916810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.3404916810 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_intr_test.759572437
Short name	T144
Test name
Test status
Simulation time	24462962 ps
CPU time	0.84 seconds
Started	Feb 04 12:39:47 PM PST 24
Finished	Feb 04 12:39:51 PM PST 24
Peak memory	215888 kb
Host	smart-549211e0-ab72-4c95-90e9-22acff4349c4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759572437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.759572437 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.2447272720
Short name	T116
Test name
Test status
Simulation time	32316498 ps
CPU time	1.22 seconds
Started	Feb 04 12:39:47 PM PST 24
Finished	Feb 04 12:39:52 PM PST 24
Peak memory	217112 kb
Host	smart-cd88f0a9-b3fb-410c-9469-e49fedac5b3c
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447272720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia l_access.2447272720 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_walk.1697456563
Short name	T1141
Test name
Test status
Simulation time	11616981 ps
CPU time	0.75 seconds
Started	Feb 04 12:39:45 PM PST 24
Finished	Feb 04 12:39:49 PM PST 24
Peak memory	216908 kb
Host	smart-1dcdb5d0-3b47-4f55-afd0-f591a227a6f1
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697456563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.1697456563 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.2728648848
Short name	T52
Test name
Test status
Simulation time	289572291 ps
CPU time	2.66 seconds
Started	Feb 04 12:39:54 PM PST 24
Finished	Feb 04 12:39:58 PM PST 24
Peak memory	216564 kb
Host	smart-5eaa94cf-e713-480d-b52e-6547e25909eb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728648848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr _outstanding.2728648848 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.607910633
Short name	T1159
Test name
Test status
Simulation time	90526959 ps
CPU time	1.05 seconds
Started	Feb 04 12:39:44 PM PST 24
Finished	Feb 04 12:39:49 PM PST 24
Peak memory	224520 kb
Host	smart-4082c351-f212-4fa5-a735-cc7ef854da08
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607910633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_e rrors.607910633 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.1132338397
Short name	T133
Test name
Test status
Simulation time	57601581 ps
CPU time	1.66 seconds
Started	Feb 04 12:39:49 PM PST 24
Finished	Feb 04 12:39:53 PM PST 24
Peak memory	216560 kb
Host	smart-b5e3b692-c59e-4c77-8265-b986ce126a66
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132338397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac _shadow_reg_errors_with_csr_rw.1132338397 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_errors.2897575458
Short name	T1146
Test name
Test status
Simulation time	100171447 ps
CPU time	1.96 seconds
Started	Feb 04 12:39:47 PM PST 24
Finished	Feb 04 12:39:51 PM PST 24
Peak memory	217064 kb
Host	smart-b09ee3d3-64c7-4db0-8db4-d39b8ebfe8bd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897575458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.2897575458 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.1555638697
Short name	T112
Test name
Test status
Simulation time	274663779 ps
CPU time	5.6 seconds
Started	Feb 04 12:39:47 PM PST 24
Finished	Feb 04 12:39:56 PM PST 24
Peak memory	217216 kb
Host	smart-bd087ce6-a35f-4a77-8e9b-a3d0c8b81d89
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555638697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.15556 38697 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.4206809608
Short name	T1241
Test name
Test status
Simulation time	60553300 ps
CPU time	1.87 seconds
Started	Feb 04 12:40:10 PM PST 24
Finished	Feb 04 12:40:26 PM PST 24
Peak memory	222048 kb
Host	smart-e521c7a0-e353-4384-a4e0-cfe42a2008b8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206809608 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.4206809608 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_rw.2417117016
Short name	T1225
Test name
Test status
Simulation time	50081661 ps
CPU time	1.25 seconds
Started	Feb 04 12:40:10 PM PST 24
Finished	Feb 04 12:40:25 PM PST 24
Peak memory	216300 kb
Host	smart-d18a52b9-e8e1-467c-b8ab-65a3c5792ba8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417117016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.2417117016 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1190212943
Short name	T1195
Test name
Test status
Simulation time	54826731 ps
CPU time	1.7 seconds
Started	Feb 04 12:40:06 PM PST 24
Finished	Feb 04 12:40:20 PM PST 24
Peak memory	216404 kb
Host	smart-757ee613-bfaf-4148-8e92-86e6621c5ad2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190212943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs r_outstanding.1190212943 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3373669571
Short name	T1235
Test name
Test status
Simulation time	70852993 ps
CPU time	1.06 seconds
Started	Feb 04 12:40:10 PM PST 24
Finished	Feb 04 12:40:25 PM PST 24
Peak memory	220900 kb
Host	smart-208eca07-8e6b-4a42-a367-94c482a5cfc7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373669571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg _errors.3373669571 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.586827087
Short name	T1145
Test name
Test status
Simulation time	122782860 ps
CPU time	3.09 seconds
Started	Feb 04 12:40:07 PM PST 24
Finished	Feb 04 12:40:22 PM PST 24
Peak memory	217592 kb
Host	smart-2300c352-9684-4d4f-ad41-677dc9eec3d2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586827087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac _shadow_reg_errors_with_csr_rw.586827087 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_errors.1715238226
Short name	T1229
Test name
Test status
Simulation time	67891944 ps
CPU time	2.02 seconds
Started	Feb 04 12:40:06 PM PST 24
Finished	Feb 04 12:40:21 PM PST 24
Peak memory	217332 kb
Host	smart-792ead0d-671d-466b-a2a2-c8c6c608d37c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715238226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.1715238226 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.1897371183
Short name	T1228
Test name
Test status
Simulation time	523319985 ps
CPU time	3.34 seconds
Started	Feb 04 12:40:07 PM PST 24
Finished	Feb 04 12:40:22 PM PST 24
Peak memory	217200 kb
Host	smart-438037a9-0ed9-4ab6-be31-5b1167e6ea93
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897371183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.1897 371183 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1483615515
Short name	T70
Test name
Test status
Simulation time	17919318 ps
CPU time	1.46 seconds
Started	Feb 04 12:39:59 PM PST 24
Finished	Feb 04 12:40:07 PM PST 24
Peak memory	219912 kb
Host	smart-35218681-05eb-431c-acfc-619dae25b122
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483615515 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.1483615515 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_rw.240251788
Short name	T1197
Test name
Test status
Simulation time	15836819 ps
CPU time	1.03 seconds
Started	Feb 04 12:40:05 PM PST 24
Finished	Feb 04 12:40:19 PM PST 24
Peak memory	216788 kb
Host	smart-0cdca2af-6f48-496b-b2c3-644254cdf7bf
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240251788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.240251788 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_intr_test.63455650
Short name	T140
Test name
Test status
Simulation time	23113537 ps
CPU time	0.79 seconds
Started	Feb 04 12:40:06 PM PST 24
Finished	Feb 04 12:40:19 PM PST 24
Peak memory	216452 kb
Host	smart-0b104275-b08a-4cfc-b5f5-f75a52a1b966
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63455650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.63455650 +enable_mas king=1 +sw_key_masked=0
Directory	/workspace/11.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3584533373
Short name	T1249
Test name
Test status
Simulation time	68872847 ps
CPU time	1.81 seconds
Started	Feb 04 12:40:01 PM PST 24
Finished	Feb 04 12:40:11 PM PST 24
Peak memory	217120 kb
Host	smart-926996ca-c98b-46fb-a677-32d4973d2685
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584533373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs r_outstanding.3584533373 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2624780559
Short name	T1264
Test name
Test status
Simulation time	109267698 ps
CPU time	2.52 seconds
Started	Feb 04 12:40:10 PM PST 24
Finished	Feb 04 12:40:27 PM PST 24
Peak memory	224788 kb
Host	smart-e5f3cda8-2bb1-4a4c-8494-263214ae6da3
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624780559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma c_shadow_reg_errors_with_csr_rw.2624780559 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_errors.580589904
Short name	T1214
Test name
Test status
Simulation time	81189584 ps
CPU time	2.97 seconds
Started	Feb 04 12:40:05 PM PST 24
Finished	Feb 04 12:40:21 PM PST 24
Peak memory	217360 kb
Host	smart-ed8e0991-fadb-4948-afa2-76155e9038c5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580589904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.580589904 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.3660368112
Short name	T151
Test name
Test status
Simulation time	520489760 ps
CPU time	5.2 seconds
Started	Feb 04 12:40:02 PM PST 24
Finished	Feb 04 12:40:15 PM PST 24
Peak memory	216620 kb
Host	smart-b013de12-2d02-4fe8-abc7-7d6c398fddbb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660368112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.3660 368112 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.434990640
Short name	T1185
Test name
Test status
Simulation time	19974693 ps
CPU time	1.54 seconds
Started	Feb 04 12:40:07 PM PST 24
Finished	Feb 04 12:40:21 PM PST 24
Peak memory	217072 kb
Host	smart-6beba4ed-46ae-4420-9e9a-9866af4d9bc9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434990640 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.434990640 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_rw.1227638740
Short name	T123
Test name
Test status
Simulation time	68576682 ps
CPU time	1.26 seconds
Started	Feb 04 12:40:04 PM PST 24
Finished	Feb 04 12:40:16 PM PST 24
Peak memory	217124 kb
Host	smart-012a41bd-e07e-45dc-88ee-6fb368cb05a2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227638740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.1227638740 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_intr_test.106491783
Short name	T1248
Test name
Test status
Simulation time	30378684 ps
CPU time	0.85 seconds
Started	Feb 04 12:39:56 PM PST 24
Finished	Feb 04 12:39:58 PM PST 24
Peak memory	216912 kb
Host	smart-f14a5b11-f39c-436f-8cb1-cbcf1981f21c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106491783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.106491783 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3403553417
Short name	T1142
Test name
Test status
Simulation time	53389619 ps
CPU time	1.81 seconds
Started	Feb 04 12:40:04 PM PST 24
Finished	Feb 04 12:40:18 PM PST 24
Peak memory	217228 kb
Host	smart-7ce511a0-d16c-4ddf-8699-a94380fca39f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403553417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs r_outstanding.3403553417 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2933893557
Short name	T63
Test name
Test status
Simulation time	139282523 ps
CPU time	1.27 seconds
Started	Feb 04 12:40:04 PM PST 24
Finished	Feb 04 12:40:17 PM PST 24
Peak memory	224660 kb
Host	smart-55dd931d-8853-43fb-9877-56a1669ef54b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933893557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg _errors.2933893557 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3686652287
Short name	T1223
Test name
Test status
Simulation time	211365204 ps
CPU time	2.56 seconds
Started	Feb 04 12:40:05 PM PST 24
Finished	Feb 04 12:40:20 PM PST 24
Peak memory	220572 kb
Host	smart-f2f1feba-1375-4405-b688-14c3cb084c7a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686652287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma c_shadow_reg_errors_with_csr_rw.3686652287 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_errors.190969222
Short name	T1158
Test name
Test status
Simulation time	447002883 ps
CPU time	3.06 seconds
Started	Feb 04 12:40:02 PM PST 24
Finished	Feb 04 12:40:13 PM PST 24
Peak memory	217324 kb
Host	smart-76115dc3-7e74-4f0a-98ea-b92ccebd2647
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190969222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.190969222 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.444888543
Short name	T1136
Test name
Test status
Simulation time	21401714 ps
CPU time	1.4 seconds
Started	Feb 04 12:40:05 PM PST 24
Finished	Feb 04 12:40:19 PM PST 24
Peak memory	220100 kb
Host	smart-1a24d427-47ff-4c3f-9037-d568e950904c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444888543 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.444888543 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_rw.2666091405
Short name	T1211
Test name
Test status
Simulation time	53007889 ps
CPU time	0.96 seconds
Started	Feb 04 12:39:54 PM PST 24
Finished	Feb 04 12:39:56 PM PST 24
Peak memory	216864 kb
Host	smart-f891ddcb-6060-455b-b0c0-ec0cac2044d6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666091405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.2666091405 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_intr_test.483173553
Short name	T1232
Test name
Test status
Simulation time	16831656 ps
CPU time	0.85 seconds
Started	Feb 04 12:40:04 PM PST 24
Finished	Feb 04 12:40:15 PM PST 24
Peak memory	216828 kb
Host	smart-97a6f85b-a635-44eb-b203-aa29d4381cca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483173553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.483173553 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2653004588
Short name	T1196
Test name
Test status
Simulation time	176943781 ps
CPU time	2.76 seconds
Started	Feb 04 12:40:04 PM PST 24
Finished	Feb 04 12:40:17 PM PST 24
Peak memory	217204 kb
Host	smart-ff5f49ea-4b51-4938-85d7-18fb81b1163d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653004588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs r_outstanding.2653004588 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2552632374
Short name	T2
Test name
Test status
Simulation time	51978465 ps
CPU time	1.28 seconds
Started	Feb 04 12:40:05 PM PST 24
Finished	Feb 04 12:40:19 PM PST 24
Peak memory	217704 kb
Host	smart-ebaeca68-1d82-4de3-b73b-bdd0ba51d4e7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552632374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg _errors.2552632374 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1911449389
Short name	T122
Test name
Test status
Simulation time	1504426756 ps
CPU time	3.19 seconds
Started	Feb 04 12:40:07 PM PST 24
Finished	Feb 04 12:40:22 PM PST 24
Peak memory	224416 kb
Host	smart-ad960615-b824-497c-a914-71a4ee3b08f8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911449389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma c_shadow_reg_errors_with_csr_rw.1911449389 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_errors.4152057476
Short name	T1178
Test name
Test status
Simulation time	54223519 ps
CPU time	1.86 seconds
Started	Feb 04 12:40:00 PM PST 24
Finished	Feb 04 12:40:09 PM PST 24
Peak memory	217248 kb
Host	smart-cb709eb0-1731-4f11-84d6-6db3eb15cb17
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152057476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.4152057476 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.2524961893
Short name	T67
Test name
Test status
Simulation time	367810362 ps
CPU time	4.37 seconds
Started	Feb 04 12:40:04 PM PST 24
Finished	Feb 04 12:40:21 PM PST 24
Peak memory	217240 kb
Host	smart-40f9c789-d593-40cb-96fa-aa1ea53cd333
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524961893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.2524 961893 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1780727278
Short name	T1173
Test name
Test status
Simulation time	66435672 ps
CPU time	1.28 seconds
Started	Feb 04 12:40:09 PM PST 24
Finished	Feb 04 12:40:25 PM PST 24
Peak memory	220388 kb
Host	smart-bbd78c1f-1489-46f6-8471-da3528e5edb2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780727278 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.1780727278 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_rw.3491541107
Short name	T115
Test name
Test status
Simulation time	104880385 ps
CPU time	1.23 seconds
Started	Feb 04 12:40:02 PM PST 24
Finished	Feb 04 12:40:11 PM PST 24
Peak memory	217144 kb
Host	smart-0116dc62-effc-4a9b-ba33-f1cfc4623eef
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491541107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.3491541107 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_intr_test.2359164453
Short name	T1174
Test name
Test status
Simulation time	17147273 ps
CPU time	0.84 seconds
Started	Feb 04 12:40:05 PM PST 24
Finished	Feb 04 12:40:19 PM PST 24
Peak memory	216800 kb
Host	smart-e887a756-b289-403f-ab03-2082fa9acd7c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359164453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.2359164453 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.32828472
Short name	T1240
Test name
Test status
Simulation time	176214097 ps
CPU time	1.67 seconds
Started	Feb 04 12:40:08 PM PST 24
Finished	Feb 04 12:40:22 PM PST 24
Peak memory	216800 kb
Host	smart-c3f3fcdc-10e9-4f99-8ea5-e6dd983ed181
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32828472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_ outstanding.32828472 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3573423880
Short name	T1215
Test name
Test status
Simulation time	35234508 ps
CPU time	1.21 seconds
Started	Feb 04 12:40:08 PM PST 24
Finished	Feb 04 12:40:21 PM PST 24
Peak memory	224728 kb
Host	smart-1e91c902-00b1-43b9-a552-eea785bbbda5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573423880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg _errors.3573423880 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2838930083
Short name	T1171
Test name
Test status
Simulation time	268628493 ps
CPU time	2.95 seconds
Started	Feb 04 12:40:03 PM PST 24
Finished	Feb 04 12:40:13 PM PST 24
Peak memory	220420 kb
Host	smart-74652cf1-2d1a-4abb-ba1c-d5f9ab6b1f00
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838930083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma c_shadow_reg_errors_with_csr_rw.2838930083 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_errors.2920673607
Short name	T1258
Test name
Test status
Simulation time	146639683 ps
CPU time	3.68 seconds
Started	Feb 04 12:39:58 PM PST 24
Finished	Feb 04 12:40:06 PM PST 24
Peak memory	217272 kb
Host	smart-7ef1ca0c-02c5-456a-bb30-29a219bc84f8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920673607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.2920673607 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.4121267517
Short name	T1239
Test name
Test status
Simulation time	109684598 ps
CPU time	3.11 seconds
Started	Feb 04 12:40:06 PM PST 24
Finished	Feb 04 12:40:21 PM PST 24
Peak memory	217140 kb
Host	smart-9cb6e6f8-15e3-444e-aba6-03b2152a2ef8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121267517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.4121 267517 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1633069037
Short name	T1208
Test name
Test status
Simulation time	25516707 ps
CPU time	1.28 seconds
Started	Feb 04 12:40:08 PM PST 24
Finished	Feb 04 12:40:21 PM PST 24
Peak memory	217288 kb
Host	smart-1bc4e34b-f93a-445f-99da-3c0de6ebcb80
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633069037 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.1633069037 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_rw.2725122006
Short name	T1138
Test name
Test status
Simulation time	29531806 ps
CPU time	1.24 seconds
Started	Feb 04 12:40:09 PM PST 24
Finished	Feb 04 12:40:25 PM PST 24
Peak memory	216292 kb
Host	smart-e00a2c64-46ae-439f-8039-04d0ca0dbdd6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725122006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.2725122006 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_intr_test.1480802954
Short name	T143
Test name
Test status
Simulation time	50962563 ps
CPU time	0.82 seconds
Started	Feb 04 12:40:09 PM PST 24
Finished	Feb 04 12:40:24 PM PST 24
Peak memory	216900 kb
Host	smart-05823f24-a098-4ed3-81c1-4c7495b800ea
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480802954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.1480802954 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2647723302
Short name	T1226
Test name
Test status
Simulation time	456538902 ps
CPU time	2.96 seconds
Started	Feb 04 12:40:09 PM PST 24
Finished	Feb 04 12:40:26 PM PST 24
Peak memory	217180 kb
Host	smart-0cf0931d-1551-45ae-b5e0-48682aea68d4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647723302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs r_outstanding.2647723302 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1275638634
Short name	T155
Test name
Test status
Simulation time	19301512 ps
CPU time	0.86 seconds
Started	Feb 04 12:40:09 PM PST 24
Finished	Feb 04 12:40:23 PM PST 24
Peak memory	219208 kb
Host	smart-34fb3869-59c8-4d64-b6f8-cd94f44bf681
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275638634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg _errors.1275638634 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3495406013
Short name	T120
Test name
Test status
Simulation time	184764677 ps
CPU time	1.74 seconds
Started	Feb 04 12:40:01 PM PST 24
Finished	Feb 04 12:40:11 PM PST 24
Peak memory	216220 kb
Host	smart-c7e00657-e9da-4a06-ab99-c68b7d8752f7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495406013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma c_shadow_reg_errors_with_csr_rw.3495406013 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1074045383
Short name	T1260
Test name
Test status
Simulation time	92753348 ps
CPU time	2.82 seconds
Started	Feb 04 12:40:05 PM PST 24
Finished	Feb 04 12:40:20 PM PST 24
Peak memory	217180 kb
Host	smart-7cd90e72-581b-4edb-b9ae-2326769da82b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074045383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.1074 045383 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3733532806
Short name	T1165
Test name
Test status
Simulation time	57805528 ps
CPU time	1.32 seconds
Started	Feb 04 12:40:10 PM PST 24
Finished	Feb 04 12:40:25 PM PST 24
Peak memory	220016 kb
Host	smart-77bb64c1-c7ad-49be-9a38-9dbd3e034e28
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733532806 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.3733532806 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_rw.1540980705
Short name	T158
Test name
Test status
Simulation time	68914946 ps
CPU time	0.98 seconds
Started	Feb 04 12:40:03 PM PST 24
Finished	Feb 04 12:40:11 PM PST 24
Peak memory	217124 kb
Host	smart-6d039ee0-12c5-40d9-b6b1-18840ebfc783
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540980705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.1540980705 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_intr_test.1185545236
Short name	T1192
Test name
Test status
Simulation time	16247664 ps
CPU time	0.78 seconds
Started	Feb 04 12:40:09 PM PST 24
Finished	Feb 04 12:40:24 PM PST 24
Peak memory	216932 kb
Host	smart-5409c8fc-f2cd-41e8-bab5-61e24515c4b4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185545236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.1185545236 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3552422949
Short name	T132
Test name
Test status
Simulation time	116809011 ps
CPU time	2.82 seconds
Started	Feb 04 12:40:02 PM PST 24
Finished	Feb 04 12:40:13 PM PST 24
Peak memory	217224 kb
Host	smart-f76b87c8-f113-43a5-86f0-926a3dcf3419
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552422949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs r_outstanding.3552422949 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.3182333405
Short name	T95
Test name
Test status
Simulation time	278886937 ps
CPU time	1.73 seconds
Started	Feb 04 12:40:10 PM PST 24
Finished	Feb 04 12:40:26 PM PST 24
Peak memory	218640 kb
Host	smart-a76f20db-b759-4221-91e5-41867501344d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182333405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg _errors.3182333405 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1242210262
Short name	T163
Test name
Test status
Simulation time	106643963 ps
CPU time	1.67 seconds
Started	Feb 04 12:40:10 PM PST 24
Finished	Feb 04 12:40:26 PM PST 24
Peak memory	216380 kb
Host	smart-0d6981f0-4bd5-4203-9967-fbaff5697442
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242210262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma c_shadow_reg_errors_with_csr_rw.1242210262 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.4072945262
Short name	T49
Test name
Test status
Simulation time	429377346 ps
CPU time	3.12 seconds
Started	Feb 04 12:40:06 PM PST 24
Finished	Feb 04 12:40:21 PM PST 24
Peak memory	217036 kb
Host	smart-a8aebd7d-65ad-4d55-bd65-e3b00e11ce97
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072945262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.4072 945262 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2692217395
Short name	T1212
Test name
Test status
Simulation time	39380778 ps
CPU time	1.8 seconds
Started	Feb 04 12:40:15 PM PST 24
Finished	Feb 04 12:40:30 PM PST 24
Peak memory	223096 kb
Host	smart-6faad466-a507-4068-a7b1-c9204655ccdc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692217395 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.2692217395 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_rw.651449461
Short name	T1157
Test name
Test status
Simulation time	105342108 ps
CPU time	1.2 seconds
Started	Feb 04 12:40:08 PM PST 24
Finished	Feb 04 12:40:21 PM PST 24
Peak memory	217136 kb
Host	smart-4ad7a05d-e428-4728-b037-078996cb37b9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651449461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.651449461 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_intr_test.2634058894
Short name	T102
Test name
Test status
Simulation time	14632399 ps
CPU time	0.83 seconds
Started	Feb 04 12:40:20 PM PST 24
Finished	Feb 04 12:40:34 PM PST 24
Peak memory	216932 kb
Host	smart-dbda9bd7-77a3-478b-9d57-b0c88a1e2159
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634058894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.2634058894 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.479405630
Short name	T1263
Test name
Test status
Simulation time	199498374 ps
CPU time	1.63 seconds
Started	Feb 04 12:40:17 PM PST 24
Finished	Feb 04 12:40:30 PM PST 24
Peak memory	217188 kb
Host	smart-28663f8f-66e5-453c-aad1-089db2f44148
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479405630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr _outstanding.479405630 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.1162033057
Short name	T1179
Test name
Test status
Simulation time	56335775 ps
CPU time	1.18 seconds
Started	Feb 04 12:40:16 PM PST 24
Finished	Feb 04 12:40:29 PM PST 24
Peak memory	224736 kb
Host	smart-d45480b1-d9b2-4a94-9966-2fbd6d0173a0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162033057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg _errors.1162033057 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1212655512
Short name	T1206
Test name
Test status
Simulation time	121678717 ps
CPU time	3.02 seconds
Started	Feb 04 12:40:08 PM PST 24
Finished	Feb 04 12:40:23 PM PST 24
Peak memory	220380 kb
Host	smart-399d5e7b-e6cb-40ca-b6ce-5f9057c291ed
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212655512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma c_shadow_reg_errors_with_csr_rw.1212655512 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_errors.2467966699
Short name	T55
Test name
Test status
Simulation time	26668311 ps
CPU time	1.54 seconds
Started	Feb 04 12:40:11 PM PST 24
Finished	Feb 04 12:40:28 PM PST 24
Peak memory	217472 kb
Host	smart-d173b5e3-a777-447d-88c9-0af502780592
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467966699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.2467966699 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1109938278
Short name	T157
Test name
Test status
Simulation time	17876195 ps
CPU time	1.33 seconds
Started	Feb 04 12:40:12 PM PST 24
Finished	Feb 04 12:40:29 PM PST 24
Peak memory	219608 kb
Host	smart-04be102f-6eca-4358-bdd2-8997fb414241
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109938278 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.1109938278 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_rw.3870360011
Short name	T1150
Test name
Test status
Simulation time	39630150 ps
CPU time	1.24 seconds
Started	Feb 04 12:40:13 PM PST 24
Finished	Feb 04 12:40:28 PM PST 24
Peak memory	217068 kb
Host	smart-c5e499f0-10f7-49cf-b92a-95bd363b13f1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870360011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.3870360011 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2018770305
Short name	T1256
Test name
Test status
Simulation time	114071014 ps
CPU time	2.64 seconds
Started	Feb 04 12:40:16 PM PST 24
Finished	Feb 04 12:40:31 PM PST 24
Peak memory	216644 kb
Host	smart-3269d855-7d4f-465d-8f14-dae2d8cdbbb8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018770305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs r_outstanding.2018770305 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.3513782275
Short name	T65
Test name
Test status
Simulation time	25384605 ps
CPU time	1.09 seconds
Started	Feb 04 12:40:11 PM PST 24
Finished	Feb 04 12:40:28 PM PST 24
Peak memory	217216 kb
Host	smart-5cafb6a3-f7cf-457f-a5c2-91a0bff721cd
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513782275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg _errors.3513782275 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1526623509
Short name	T1181
Test name
Test status
Simulation time	52015925 ps
CPU time	2.56 seconds
Started	Feb 04 12:40:10 PM PST 24
Finished	Feb 04 12:40:27 PM PST 24
Peak memory	224704 kb
Host	smart-6e56c279-e19d-416b-8c18-ed5c6eff9656
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526623509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma c_shadow_reg_errors_with_csr_rw.1526623509 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_errors.1133204411
Short name	T1170
Test name
Test status
Simulation time	94828643 ps
CPU time	1.84 seconds
Started	Feb 04 12:40:08 PM PST 24
Finished	Feb 04 12:40:23 PM PST 24
Peak memory	217260 kb
Host	smart-0f354c62-63f5-4345-b1d3-dd102af9fede
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133204411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.1133204411 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3398144201
Short name	T149
Test name
Test status
Simulation time	113861286 ps
CPU time	2.89 seconds
Started	Feb 04 12:40:08 PM PST 24
Finished	Feb 04 12:40:24 PM PST 24
Peak memory	216380 kb
Host	smart-4036380d-93c2-4532-ba3f-806491342ca6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398144201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3398 144201 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3563370247
Short name	T162
Test name
Test status
Simulation time	21262729 ps
CPU time	1.32 seconds
Started	Feb 04 12:40:08 PM PST 24
Finished	Feb 04 12:40:22 PM PST 24
Peak memory	218600 kb
Host	smart-2ffc0568-b7df-43b8-b38b-88de9c4065f2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563370247 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.3563370247 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_rw.4225672037
Short name	T1143
Test name
Test status
Simulation time	21274562 ps
CPU time	1.02 seconds
Started	Feb 04 12:40:10 PM PST 24
Finished	Feb 04 12:40:27 PM PST 24
Peak memory	216048 kb
Host	smart-b2d47cd2-9ea7-4f5b-bc88-b55c25b8be43
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225672037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.4225672037 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_intr_test.2936520007
Short name	T1238
Test name
Test status
Simulation time	41161025 ps
CPU time	0.8 seconds
Started	Feb 04 12:40:16 PM PST 24
Finished	Feb 04 12:40:29 PM PST 24
Peak memory	216312 kb
Host	smart-779b2164-ef3b-494e-adac-8f72933019f4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936520007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.2936520007 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.4006140056
Short name	T1254
Test name
Test status
Simulation time	324574205 ps
CPU time	2.84 seconds
Started	Feb 04 12:40:12 PM PST 24
Finished	Feb 04 12:40:30 PM PST 24
Peak memory	217084 kb
Host	smart-2d099897-5658-4029-9e79-64d55e41888c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006140056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs r_outstanding.4006140056 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3275460283
Short name	T92
Test name
Test status
Simulation time	32548821 ps
CPU time	1.11 seconds
Started	Feb 04 12:40:16 PM PST 24
Finished	Feb 04 12:40:29 PM PST 24
Peak memory	218180 kb
Host	smart-77c32ff3-2f56-42ec-93c2-a4467aad0501
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275460283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg _errors.3275460283 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_errors.119646539
Short name	T59
Test name
Test status
Simulation time	119571872 ps
CPU time	2.06 seconds
Started	Feb 04 12:40:13 PM PST 24
Finished	Feb 04 12:40:29 PM PST 24
Peak memory	217336 kb
Host	smart-8131b3a6-4612-40b2-ab74-aa5cb9b5cc39
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119646539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.119646539 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.462252106
Short name	T1188
Test name
Test status
Simulation time	454651026 ps
CPU time	3.29 seconds
Started	Feb 04 12:40:10 PM PST 24
Finished	Feb 04 12:40:28 PM PST 24
Peak memory	217108 kb
Host	smart-b2a23f05-d268-4d6e-ae2c-66094eda7018
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462252106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.46225 2106 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.3874597830
Short name	T131
Test name
Test status
Simulation time	2457497239 ps
CPU time	9.97 seconds
Started	Feb 04 12:39:57 PM PST 24
Finished	Feb 04 12:40:11 PM PST 24
Peak memory	217248 kb
Host	smart-7c1c75f9-57d3-4d31-bf61-756da374326e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874597830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.3874597 830 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.1540524610
Short name	T1137
Test name
Test status
Simulation time	802314701 ps
CPU time	12.11 seconds
Started	Feb 04 12:40:04 PM PST 24
Finished	Feb 04 12:40:29 PM PST 24
Peak memory	217192 kb
Host	smart-bca78734-495a-477d-9eda-1ed60f63a64d
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540524610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1540524 610 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.709510135
Short name	T1221
Test name
Test status
Simulation time	59384031 ps
CPU time	1.06 seconds
Started	Feb 04 12:39:59 PM PST 24
Finished	Feb 04 12:40:07 PM PST 24
Peak memory	216868 kb
Host	smart-4235efc0-7c99-436e-9402-d781397fc3f7
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709510135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.70951013 5 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2532610289
Short name	T69
Test name
Test status
Simulation time	22493849 ps
CPU time	1.5 seconds
Started	Feb 04 12:40:04 PM PST 24
Finished	Feb 04 12:40:18 PM PST 24
Peak memory	220280 kb
Host	smart-e514be24-1c72-4296-9d9c-b4ced78f5c84
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532610289 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.2532610289 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_rw.3750492066
Short name	T1247
Test name
Test status
Simulation time	32510048 ps
CPU time	1.15 seconds
Started	Feb 04 12:39:59 PM PST 24
Finished	Feb 04 12:40:06 PM PST 24
Peak memory	216224 kb
Host	smart-f872761a-0625-40cc-aac0-2fc750e5f5b2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750492066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.3750492066 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_intr_test.3204646931
Short name	T1255
Test name
Test status
Simulation time	47438073 ps
CPU time	0.84 seconds
Started	Feb 04 12:39:59 PM PST 24
Finished	Feb 04 12:40:06 PM PST 24
Peak memory	216888 kb
Host	smart-4e569fb0-bfb5-4028-869d-bfda3cfda15e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204646931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.3204646931 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.3091439133
Short name	T126
Test name
Test status
Simulation time	135060857 ps
CPU time	1.61 seconds
Started	Feb 04 12:39:53 PM PST 24
Finished	Feb 04 12:39:55 PM PST 24
Peak memory	216964 kb
Host	smart-08051f9b-f803-486e-9586-a88756399126
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091439133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia l_access.3091439133 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_walk.639635346
Short name	T159
Test name
Test status
Simulation time	23069455 ps
CPU time	0.76 seconds
Started	Feb 04 12:39:57 PM PST 24
Finished	Feb 04 12:40:02 PM PST 24
Peak memory	216108 kb
Host	smart-4ff7f8c6-d77c-4884-a95c-680d92e6efac
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639635346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.639635346 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.530699479
Short name	T1177
Test name
Test status
Simulation time	186533297 ps
CPU time	2.58 seconds
Started	Feb 04 12:39:59 PM PST 24
Finished	Feb 04 12:40:07 PM PST 24
Peak memory	216188 kb
Host	smart-05c0132f-f507-49c9-b665-2271d1fa33eb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530699479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_ outstanding.530699479 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.959359070
Short name	T1135
Test name
Test status
Simulation time	16672106 ps
CPU time	1 seconds
Started	Feb 04 12:39:59 PM PST 24
Finished	Feb 04 12:40:05 PM PST 24
Peak memory	217300 kb
Host	smart-e1d87d9e-1de2-49e2-928b-91c86aca6027
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959359070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_e rrors.959359070 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3317117269
Short name	T90
Test name
Test status
Simulation time	98695763 ps
CPU time	2.45 seconds
Started	Feb 04 12:39:59 PM PST 24
Finished	Feb 04 12:40:07 PM PST 24
Peak memory	220688 kb
Host	smart-52a81bf3-2197-41bc-90ae-c647fbfc9ae0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317117269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac _shadow_reg_errors_with_csr_rw.3317117269 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_errors.1001137273
Short name	T1233
Test name
Test status
Simulation time	118425746 ps
CPU time	1.9 seconds
Started	Feb 04 12:39:59 PM PST 24
Finished	Feb 04 12:40:08 PM PST 24
Peak memory	217272 kb
Host	smart-9e9d9d0f-20b9-4fe9-9cef-7e3fdcdef352
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001137273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.1001137273 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.4033003782
Short name	T1176
Test name
Test status
Simulation time	339538719 ps
CPU time	5.97 seconds
Started	Feb 04 12:40:04 PM PST 24
Finished	Feb 04 12:40:21 PM PST 24
Peak memory	217132 kb
Host	smart-fb813bba-4769-4acf-a3fc-9de80032f287
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033003782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.40330 03782 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.kmac_intr_test.1400106125
Short name	T1234
Test name
Test status
Simulation time	26336484 ps
CPU time	0.87 seconds
Started	Feb 04 12:40:11 PM PST 24
Finished	Feb 04 12:40:28 PM PST 24
Peak memory	216860 kb
Host	smart-813730be-9f6b-4493-8f44-2013e8a23b4f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400106125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.1400106125 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.kmac_intr_test.2835494112
Short name	T47
Test name
Test status
Simulation time	40249193 ps
CPU time	0.8 seconds
Started	Feb 04 12:40:09 PM PST 24
Finished	Feb 04 12:40:25 PM PST 24
Peak memory	217028 kb
Host	smart-e11b6988-eaa9-4424-8832-0486f23a09a5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835494112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.2835494112 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.kmac_intr_test.4156954962
Short name	T1204
Test name
Test status
Simulation time	15056897 ps
CPU time	0.83 seconds
Started	Feb 04 12:40:10 PM PST 24
Finished	Feb 04 12:40:25 PM PST 24
Peak memory	216812 kb
Host	smart-18c30008-1e19-47bb-b540-caf5d05a7e59
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156954962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.4156954962 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.kmac_intr_test.3100635235
Short name	T1216
Test name
Test status
Simulation time	26879705 ps
CPU time	0.79 seconds
Started	Feb 04 12:40:17 PM PST 24
Finished	Feb 04 12:40:29 PM PST 24
Peak memory	216860 kb
Host	smart-9966dd63-4af1-43bb-84d7-b206ff90825b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100635235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.3100635235 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.kmac_intr_test.1299739729
Short name	T51
Test name
Test status
Simulation time	18101408 ps
CPU time	0.78 seconds
Started	Feb 04 12:40:16 PM PST 24
Finished	Feb 04 12:40:29 PM PST 24
Peak memory	216932 kb
Host	smart-d569ae67-e62b-4994-afef-abfb982dfe56
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299739729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.1299739729 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.kmac_intr_test.861658981
Short name	T1199
Test name
Test status
Simulation time	15222957 ps
CPU time	0.78 seconds
Started	Feb 04 12:40:10 PM PST 24
Finished	Feb 04 12:40:27 PM PST 24
Peak memory	217016 kb
Host	smart-07d0fed0-4164-4c14-999d-f0bc675eb494
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861658981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.861658981 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.kmac_intr_test.3316728578
Short name	T1162
Test name
Test status
Simulation time	130270086 ps
CPU time	0.83 seconds
Started	Feb 04 12:40:13 PM PST 24
Finished	Feb 04 12:40:28 PM PST 24
Peak memory	216856 kb
Host	smart-924591dd-3374-4d3e-bf8a-59b217c3bf29
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316728578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.3316728578 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.kmac_intr_test.2357916417
Short name	T1193
Test name
Test status
Simulation time	42486856 ps
CPU time	0.82 seconds
Started	Feb 04 12:40:12 PM PST 24
Finished	Feb 04 12:40:28 PM PST 24
Peak memory	216992 kb
Host	smart-5a13bd7d-33f6-4ed3-acc6-d34a7eeb0642
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357916417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.2357916417 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.kmac_intr_test.1057149625
Short name	T1203
Test name
Test status
Simulation time	15442673 ps
CPU time	0.81 seconds
Started	Feb 04 12:40:08 PM PST 24
Finished	Feb 04 12:40:22 PM PST 24
Peak memory	216868 kb
Host	smart-a8956c47-3558-4254-ba4a-f67f7d1d9244
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057149625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.1057149625 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.kmac_intr_test.3255449952
Short name	T139
Test name
Test status
Simulation time	19253590 ps
CPU time	0.77 seconds
Started	Feb 04 12:40:08 PM PST 24
Finished	Feb 04 12:40:21 PM PST 24
Peak memory	216888 kb
Host	smart-ef2edbc7-ce5d-4af5-a04c-41dfcc8220be
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255449952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.3255449952 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.2388111248
Short name	T127
Test name
Test status
Simulation time	162785739 ps
CPU time	9.63 seconds
Started	Feb 04 12:40:07 PM PST 24
Finished	Feb 04 12:40:28 PM PST 24
Peak memory	217188 kb
Host	smart-6597466d-447f-48e6-8898-b1e76560d44e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388111248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.2388111 248 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.3437239183
Short name	T156
Test name
Test status
Simulation time	737491349 ps
CPU time	9.03 seconds
Started	Feb 04 12:39:55 PM PST 24
Finished	Feb 04 12:40:06 PM PST 24
Peak memory	217212 kb
Host	smart-46cdff27-7963-43b4-a9e4-3cf9333a2f3a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437239183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.3437239 183 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.1239581717
Short name	T1140
Test name
Test status
Simulation time	162182201 ps
CPU time	1.17 seconds
Started	Feb 04 12:40:03 PM PST 24
Finished	Feb 04 12:40:11 PM PST 24
Peak memory	217156 kb
Host	smart-a2f7ddb3-74ac-4086-90da-2a83d7ab8c83
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239581717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.1239581 717 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1524530055
Short name	T1231
Test name
Test status
Simulation time	22049197 ps
CPU time	1.27 seconds
Started	Feb 04 12:40:07 PM PST 24
Finished	Feb 04 12:40:20 PM PST 24
Peak memory	219284 kb
Host	smart-e8569a78-b340-447d-ad2a-0abe1b061e16
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524530055 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.1524530055 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_rw.846611257
Short name	T129
Test name
Test status
Simulation time	47766114 ps
CPU time	1.17 seconds
Started	Feb 04 12:40:05 PM PST 24
Finished	Feb 04 12:40:19 PM PST 24
Peak memory	217376 kb
Host	smart-e1549ded-219c-4ffd-8494-8a4aeb454c69
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846611257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.846611257 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_intr_test.4177316761
Short name	T1217
Test name
Test status
Simulation time	21035614 ps
CPU time	0.77 seconds
Started	Feb 04 12:39:57 PM PST 24
Finished	Feb 04 12:40:03 PM PST 24
Peak memory	216876 kb
Host	smart-42d2b8e1-1226-407b-8b3d-1bf8ae859b1a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177316761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.4177316761 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_walk.862041990
Short name	T1261
Test name
Test status
Simulation time	11141682 ps
CPU time	0.78 seconds
Started	Feb 04 12:39:56 PM PST 24
Finished	Feb 04 12:39:58 PM PST 24
Peak memory	216936 kb
Host	smart-6f1973d6-bd00-4394-9960-55fc9081d7c8
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862041990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.862041990 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1526379436
Short name	T1167
Test name
Test status
Simulation time	38362677 ps
CPU time	2.32 seconds
Started	Feb 04 12:39:55 PM PST 24
Finished	Feb 04 12:39:59 PM PST 24
Peak memory	216324 kb
Host	smart-178416a6-2367-4843-95da-21f3a0445907
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526379436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr _outstanding.1526379436 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.537844871
Short name	T1257
Test name
Test status
Simulation time	79254636 ps
CPU time	1.44 seconds
Started	Feb 04 12:39:55 PM PST 24
Finished	Feb 04 12:39:57 PM PST 24
Peak memory	218736 kb
Host	smart-677a1ac4-19f0-4427-a60b-304594174285
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537844871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_e rrors.537844871 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3241459851
Short name	T64
Test name
Test status
Simulation time	1044047721 ps
CPU time	2.24 seconds
Started	Feb 04 12:39:58 PM PST 24
Finished	Feb 04 12:40:06 PM PST 24
Peak memory	221148 kb
Host	smart-00548988-14d0-41ac-985f-a3a471b57f9c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241459851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac _shadow_reg_errors_with_csr_rw.3241459851 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_errors.732700315
Short name	T1191
Test name
Test status
Simulation time	132274369 ps
CPU time	1.69 seconds
Started	Feb 04 12:39:56 PM PST 24
Finished	Feb 04 12:39:59 PM PST 24
Peak memory	217440 kb
Host	smart-2ca8e59d-ef6a-4492-88d4-67ccf249c7d1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732700315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.732700315 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.818595641
Short name	T1243
Test name
Test status
Simulation time	424947011 ps
CPU time	3.09 seconds
Started	Feb 04 12:40:02 PM PST 24
Finished	Feb 04 12:40:13 PM PST 24
Peak memory	217136 kb
Host	smart-4a71579f-94ca-418e-bf69-2a57ad7ef63e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818595641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.818595 641 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.kmac_intr_test.1575237
Short name	T1154
Test name
Test status
Simulation time	14003755 ps
CPU time	0.81 seconds
Started	Feb 04 12:40:15 PM PST 24
Finished	Feb 04 12:40:29 PM PST 24
Peak memory	216336 kb
Host	smart-1ed16f1f-abcf-4326-9105-35d63f64f678
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.1575237 +enable_maski ng=1 +sw_key_masked=0
Directory	/workspace/30.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.kmac_intr_test.1283487999
Short name	T1242
Test name
Test status
Simulation time	50239339 ps
CPU time	0.82 seconds
Started	Feb 04 12:40:16 PM PST 24
Finished	Feb 04 12:40:29 PM PST 24
Peak memory	216172 kb
Host	smart-41dc65d0-dee7-4e5f-9530-8eb99d542d31
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283487999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.1283487999 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.kmac_intr_test.3160900234
Short name	T1198
Test name
Test status
Simulation time	49891874 ps
CPU time	0.84 seconds
Started	Feb 04 12:40:15 PM PST 24
Finished	Feb 04 12:40:29 PM PST 24
Peak memory	215572 kb
Host	smart-5eaf6d34-d9ab-47ac-8d2a-bb5cb31b891c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160900234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.3160900234 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.kmac_intr_test.2368570422
Short name	T124
Test name
Test status
Simulation time	14614096 ps
CPU time	0.85 seconds
Started	Feb 04 12:40:08 PM PST 24
Finished	Feb 04 12:40:22 PM PST 24
Peak memory	216924 kb
Host	smart-0e9d4e82-55af-49bf-b012-fa976da4ab2e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368570422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.2368570422 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.kmac_intr_test.3724759266
Short name	T145
Test name
Test status
Simulation time	14765459 ps
CPU time	0.81 seconds
Started	Feb 04 12:40:05 PM PST 24
Finished	Feb 04 12:40:19 PM PST 24
Peak memory	216856 kb
Host	smart-a25cc44a-e931-472d-9c58-667c182a1038
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724759266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.3724759266 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.kmac_intr_test.2943514662
Short name	T138
Test name
Test status
Simulation time	19516122 ps
CPU time	0.82 seconds
Started	Feb 04 12:40:17 PM PST 24
Finished	Feb 04 12:40:29 PM PST 24
Peak memory	216860 kb
Host	smart-0bb130cd-eb84-4982-88e9-8722b8c47506
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943514662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.2943514662 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.kmac_intr_test.1468595137
Short name	T1230
Test name
Test status
Simulation time	25308553 ps
CPU time	0.84 seconds
Started	Feb 04 12:40:12 PM PST 24
Finished	Feb 04 12:40:28 PM PST 24
Peak memory	216996 kb
Host	smart-de67822c-71b0-41b8-9f0b-42b918ec5af2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468595137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.1468595137 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.kmac_intr_test.2610905537
Short name	T1153
Test name
Test status
Simulation time	24314906 ps
CPU time	0.81 seconds
Started	Feb 04 12:40:19 PM PST 24
Finished	Feb 04 12:40:34 PM PST 24
Peak memory	215872 kb
Host	smart-1c3fc2e1-6ec8-49a5-b316-64d9e485728f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610905537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.2610905537 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.kmac_intr_test.800582237
Short name	T1148
Test name
Test status
Simulation time	38330254 ps
CPU time	0.79 seconds
Started	Feb 04 12:40:18 PM PST 24
Finished	Feb 04 12:40:30 PM PST 24
Peak memory	216936 kb
Host	smart-5953b2e3-9042-465a-956f-82862e1e76d3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800582237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.800582237 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.kmac_intr_test.3369071033
Short name	T1213
Test name
Test status
Simulation time	12534316 ps
CPU time	0.8 seconds
Started	Feb 04 12:40:10 PM PST 24
Finished	Feb 04 12:40:27 PM PST 24
Peak memory	216868 kb
Host	smart-13f832a2-d172-4f3e-8215-006f10424305
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369071033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.3369071033 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.2569567332
Short name	T1156
Test name
Test status
Simulation time	582548566 ps
CPU time	11.64 seconds
Started	Feb 04 12:40:05 PM PST 24
Finished	Feb 04 12:40:29 PM PST 24
Peak memory	217116 kb
Host	smart-be2075d9-7fe7-46a1-9d2e-ff4dd2e2e7c8
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569567332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.2569567 332 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.10108609
Short name	T1227
Test name
Test status
Simulation time	3763391460 ps
CPU time	23.85 seconds
Started	Feb 04 12:40:05 PM PST 24
Finished	Feb 04 12:40:42 PM PST 24
Peak memory	217144 kb
Host	smart-bdbb6f7e-c54b-4382-8823-36a2ebe6288a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10108609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.10108609 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.688533436
Short name	T66
Test name
Test status
Simulation time	68076088 ps
CPU time	1.14 seconds
Started	Feb 04 12:40:04 PM PST 24
Finished	Feb 04 12:40:18 PM PST 24
Peak memory	216408 kb
Host	smart-402987e2-1f55-4aac-9ecd-c7f7959eebde
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688533436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.68853343 6 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3309983283
Short name	T61
Test name
Test status
Simulation time	155510186 ps
CPU time	1.97 seconds
Started	Feb 04 12:40:03 PM PST 24
Finished	Feb 04 12:40:12 PM PST 24
Peak memory	221944 kb
Host	smart-df7b9f53-13d8-4482-900a-68d4e8987131
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309983283 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.3309983283 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_rw.2216674885
Short name	T160
Test name
Test status
Simulation time	88447439 ps
CPU time	1.17 seconds
Started	Feb 04 12:39:57 PM PST 24
Finished	Feb 04 12:40:02 PM PST 24
Peak memory	217220 kb
Host	smart-1a45494f-5447-4b78-95c0-acf984f4c7fe
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216674885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.2216674885 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_intr_test.504812576
Short name	T1222
Test name
Test status
Simulation time	64337214 ps
CPU time	0.87 seconds
Started	Feb 04 12:40:02 PM PST 24
Finished	Feb 04 12:40:10 PM PST 24
Peak memory	216928 kb
Host	smart-03446034-90fb-4753-9dcf-c38a39845bdc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504812576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.504812576 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.1071567865
Short name	T125
Test name
Test status
Simulation time	75967580 ps
CPU time	1.59 seconds
Started	Feb 04 12:39:56 PM PST 24
Finished	Feb 04 12:40:00 PM PST 24
Peak memory	217136 kb
Host	smart-e4d33350-ccc4-4c28-9506-1ba9dbd96cbf
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071567865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia l_access.1071567865 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_walk.1215879101
Short name	T1237
Test name
Test status
Simulation time	18670713 ps
CPU time	0.77 seconds
Started	Feb 04 12:39:57 PM PST 24
Finished	Feb 04 12:40:02 PM PST 24
Peak memory	216888 kb
Host	smart-0cfb441a-0db2-4e3b-929e-dd56d37ad52b
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215879101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.1215879101 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.658579240
Short name	T1190
Test name
Test status
Simulation time	255471778 ps
CPU time	2.49 seconds
Started	Feb 04 12:39:59 PM PST 24
Finished	Feb 04 12:40:08 PM PST 24
Peak memory	217188 kb
Host	smart-a137de00-c67a-48ac-ab9b-2e90ca83ac2b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658579240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_ outstanding.658579240 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.2162817688
Short name	T161
Test name
Test status
Simulation time	84214621 ps
CPU time	1.02 seconds
Started	Feb 04 12:40:02 PM PST 24
Finished	Feb 04 12:40:11 PM PST 24
Peak memory	217372 kb
Host	smart-4b51afa0-4231-44ae-b98b-73e923c2d4b5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162817688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_ errors.2162817688 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.3515706924
Short name	T1201
Test name
Test status
Simulation time	81446011 ps
CPU time	2.64 seconds
Started	Feb 04 12:39:57 PM PST 24
Finished	Feb 04 12:40:04 PM PST 24
Peak memory	217220 kb
Host	smart-fbf63830-b0ba-4551-8e0e-3eeed8a7aa60
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515706924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac _shadow_reg_errors_with_csr_rw.3515706924 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_errors.2888788450
Short name	T54
Test name
Test status
Simulation time	61296153 ps
CPU time	1.35 seconds
Started	Feb 04 12:40:02 PM PST 24
Finished	Feb 04 12:40:10 PM PST 24
Peak memory	217456 kb
Host	smart-2f355fbc-d85f-4766-969f-3c24530e148f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888788450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.2888788450 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/40.kmac_intr_test.3625689637
Short name	T1172
Test name
Test status
Simulation time	21889244 ps
CPU time	0.87 seconds
Started	Feb 04 12:40:15 PM PST 24
Finished	Feb 04 12:40:28 PM PST 24
Peak memory	216764 kb
Host	smart-7fdd18bf-85ed-4db4-9a61-71247a204568
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625689637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.3625689637 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.kmac_intr_test.1904506375
Short name	T1218
Test name
Test status
Simulation time	46111005 ps
CPU time	0.83 seconds
Started	Feb 04 12:40:11 PM PST 24
Finished	Feb 04 12:40:28 PM PST 24
Peak memory	216824 kb
Host	smart-8b417c3a-6483-4cab-9f9f-e5d283eb63fa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904506375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.1904506375 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.kmac_intr_test.363238617
Short name	T1180
Test name
Test status
Simulation time	15979083 ps
CPU time	0.77 seconds
Started	Feb 04 12:40:17 PM PST 24
Finished	Feb 04 12:40:29 PM PST 24
Peak memory	216932 kb
Host	smart-269fd630-994a-4ee4-8421-7a575010f06f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363238617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.363238617 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.kmac_intr_test.3608826661
Short name	T1194
Test name
Test status
Simulation time	11906675 ps
CPU time	0.78 seconds
Started	Feb 04 12:40:16 PM PST 24
Finished	Feb 04 12:40:29 PM PST 24
Peak memory	216176 kb
Host	smart-f33edb27-98e1-497d-b7df-4b7e0d251a3a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608826661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.3608826661 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.kmac_intr_test.1279786911
Short name	T1210
Test name
Test status
Simulation time	14393102 ps
CPU time	0.81 seconds
Started	Feb 04 12:40:17 PM PST 24
Finished	Feb 04 12:40:30 PM PST 24
Peak memory	216856 kb
Host	smart-49838341-7d8a-4cab-8c5e-53d11714cebc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279786911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.1279786911 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.kmac_intr_test.1715054277
Short name	T1189
Test name
Test status
Simulation time	13442216 ps
CPU time	0.78 seconds
Started	Feb 04 12:40:17 PM PST 24
Finished	Feb 04 12:40:30 PM PST 24
Peak memory	216860 kb
Host	smart-dfec05fa-22ef-4ada-b2bf-f5e807baef5b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715054277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.1715054277 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.kmac_intr_test.3042090392
Short name	T1246
Test name
Test status
Simulation time	58452672 ps
CPU time	0.76 seconds
Started	Feb 04 12:40:20 PM PST 24
Finished	Feb 04 12:40:34 PM PST 24
Peak memory	216028 kb
Host	smart-edf7817f-a8a8-4cfd-a282-f198569244a3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042090392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.3042090392 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.kmac_intr_test.16933716
Short name	T1147
Test name
Test status
Simulation time	15161472 ps
CPU time	0.85 seconds
Started	Feb 04 12:40:13 PM PST 24
Finished	Feb 04 12:40:28 PM PST 24
Peak memory	216860 kb
Host	smart-cb760346-9e5e-4262-aba8-e621a7ae6684
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16933716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.16933716 +enable_mas king=1 +sw_key_masked=0
Directory	/workspace/48.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.kmac_intr_test.2320345919
Short name	T142
Test name
Test status
Simulation time	21531663 ps
CPU time	0.8 seconds
Started	Feb 04 12:40:07 PM PST 24
Finished	Feb 04 12:40:20 PM PST 24
Peak memory	216936 kb
Host	smart-9dded419-7536-42ba-897a-6d8b33856c6a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320345919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.2320345919 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1616986321
Short name	T117
Test name
Test status
Simulation time	78835653 ps
CPU time	1.71 seconds
Started	Feb 04 12:40:06 PM PST 24
Finished	Feb 04 12:40:20 PM PST 24
Peak memory	218184 kb
Host	smart-c07f710b-7d0f-4680-a90d-a6009a54c152
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616986321 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.1616986321 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_rw.1884111283
Short name	T1245
Test name
Test status
Simulation time	35297857 ps
CPU time	1.28 seconds
Started	Feb 04 12:40:04 PM PST 24
Finished	Feb 04 12:40:17 PM PST 24
Peak memory	217252 kb
Host	smart-80d7780c-5077-40e6-bd92-3bbe1146ebe5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884111283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.1884111283 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_intr_test.1647499905
Short name	T1175
Test name
Test status
Simulation time	13380155 ps
CPU time	0.79 seconds
Started	Feb 04 12:40:03 PM PST 24
Finished	Feb 04 12:40:11 PM PST 24
Peak memory	216928 kb
Host	smart-2860889c-f53e-4bd1-a0b3-2962433a9230
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647499905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.1647499905 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1055483917
Short name	T1219
Test name
Test status
Simulation time	973418441 ps
CPU time	2.96 seconds
Started	Feb 04 12:40:02 PM PST 24
Finished	Feb 04 12:40:12 PM PST 24
Peak memory	216272 kb
Host	smart-30537962-2ae0-46fa-83e2-e6716463512b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055483917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr _outstanding.1055483917 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3253090330
Short name	T91
Test name
Test status
Simulation time	77830065 ps
CPU time	1.02 seconds
Started	Feb 04 12:39:57 PM PST 24
Finished	Feb 04 12:40:01 PM PST 24
Peak memory	217460 kb
Host	smart-cf8b1e42-426f-4905-b202-fd91cbce8061
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253090330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_ errors.3253090330 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.499820861
Short name	T3
Test name
Test status
Simulation time	567232737 ps
CPU time	3.14 seconds
Started	Feb 04 12:39:56 PM PST 24
Finished	Feb 04 12:40:01 PM PST 24
Peak memory	220828 kb
Host	smart-f02c0ce5-8409-4d28-b3da-155b7ec63f94
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499820861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_ shadow_reg_errors_with_csr_rw.499820861 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_errors.4006727639
Short name	T1168
Test name
Test status
Simulation time	80728884 ps
CPU time	2.55 seconds
Started	Feb 04 12:39:57 PM PST 24
Finished	Feb 04 12:40:04 PM PST 24
Peak memory	217296 kb
Host	smart-08ea5598-beaf-484b-809c-2699cb2003f9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006727639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.4006727639 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2290304602
Short name	T111
Test name
Test status
Simulation time	233225431 ps
CPU time	2.59 seconds
Started	Feb 04 12:39:56 PM PST 24
Finished	Feb 04 12:40:00 PM PST 24
Peak memory	217132 kb
Host	smart-4ebf9ece-ca32-4f60-affb-26cfaa16494c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290304602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.22903 04602 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2361429015
Short name	T62
Test name
Test status
Simulation time	21162420 ps
CPU time	1.64 seconds
Started	Feb 04 12:40:02 PM PST 24
Finished	Feb 04 12:40:11 PM PST 24
Peak memory	218308 kb
Host	smart-e77cfbd6-7194-4df4-bd31-de7a1840dd61
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361429015 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.2361429015 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_rw.1514564981
Short name	T1262
Test name
Test status
Simulation time	134558330 ps
CPU time	1.01 seconds
Started	Feb 04 12:39:58 PM PST 24
Finished	Feb 04 12:40:04 PM PST 24
Peak memory	216960 kb
Host	smart-b9bb47ef-7579-449d-a4cd-0393255ec3b2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514564981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.1514564981 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_intr_test.3650985191
Short name	T1251
Test name
Test status
Simulation time	80410620 ps
CPU time	0.86 seconds
Started	Feb 04 12:40:04 PM PST 24
Finished	Feb 04 12:40:15 PM PST 24
Peak memory	216860 kb
Host	smart-d91666ce-a051-49d4-978b-b0b416b1203e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650985191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.3650985191 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3391642446
Short name	T1253
Test name
Test status
Simulation time	222779926 ps
CPU time	2.75 seconds
Started	Feb 04 12:39:56 PM PST 24
Finished	Feb 04 12:40:02 PM PST 24
Peak memory	216356 kb
Host	smart-c22d87c8-0fc9-455b-95a0-93d04cfc8e78
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391642446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr _outstanding.3391642446 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.613668030
Short name	T1151
Test name
Test status
Simulation time	271052289 ps
CPU time	2.06 seconds
Started	Feb 04 12:39:58 PM PST 24
Finished	Feb 04 12:40:05 PM PST 24
Peak memory	221192 kb
Host	smart-9270653c-e46d-495d-9b34-55d8bfd26dc9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613668030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_ shadow_reg_errors_with_csr_rw.613668030 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_errors.2167145016
Short name	T1163
Test name
Test status
Simulation time	562301918 ps
CPU time	1.83 seconds
Started	Feb 04 12:39:58 PM PST 24
Finished	Feb 04 12:40:05 PM PST 24
Peak memory	217244 kb
Host	smart-a6dde8f6-00c2-4978-929b-e2ad1d4af5e2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167145016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.2167145016 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3680207429
Short name	T148
Test name
Test status
Simulation time	5002077287 ps
CPU time	6.77 seconds
Started	Feb 04 12:40:03 PM PST 24
Finished	Feb 04 12:40:21 PM PST 24
Peak memory	217132 kb
Host	smart-827a0d2f-eb67-43fe-9cb3-6c59b947fcde
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680207429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.36802 07429 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3846697239
Short name	T56
Test name
Test status
Simulation time	115561004 ps
CPU time	2.29 seconds
Started	Feb 04 12:40:03 PM PST 24
Finished	Feb 04 12:40:12 PM PST 24
Peak memory	224396 kb
Host	smart-0dc80d33-cce3-48d4-9295-450e324eb473
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846697239 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.3846697239 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_rw.3948011666
Short name	T1183
Test name
Test status
Simulation time	77724187 ps
CPU time	1.02 seconds
Started	Feb 04 12:40:08 PM PST 24
Finished	Feb 04 12:40:22 PM PST 24
Peak memory	216120 kb
Host	smart-f781e2cc-6378-45c4-9737-844aedd55aaa
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948011666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.3948011666 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_intr_test.2372822486
Short name	T1166
Test name
Test status
Simulation time	35898982 ps
CPU time	0.8 seconds
Started	Feb 04 12:40:08 PM PST 24
Finished	Feb 04 12:40:21 PM PST 24
Peak memory	216592 kb
Host	smart-e2c178d7-5290-4d02-9c95-9dcacb93b36a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372822486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.2372822486 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.419625453
Short name	T121
Test name
Test status
Simulation time	104010213 ps
CPU time	1.77 seconds
Started	Feb 04 12:40:05 PM PST 24
Finished	Feb 04 12:40:19 PM PST 24
Peak memory	216160 kb
Host	smart-1ea2bfec-fe8c-4ec2-a97c-27bb9bfb27bb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419625453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_ outstanding.419625453 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1842430171
Short name	T1200
Test name
Test status
Simulation time	234710213 ps
CPU time	1.3 seconds
Started	Feb 04 12:40:03 PM PST 24
Finished	Feb 04 12:40:11 PM PST 24
Peak memory	218636 kb
Host	smart-b878b756-1adb-4791-82b0-e18e990bfb0f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842430171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_ errors.1842430171 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3689558880
Short name	T1186
Test name
Test status
Simulation time	66136928 ps
CPU time	1.99 seconds
Started	Feb 04 12:40:01 PM PST 24
Finished	Feb 04 12:40:11 PM PST 24
Peak memory	221112 kb
Host	smart-137770cf-a98a-4fa6-8aa7-8813c6038e17
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689558880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac _shadow_reg_errors_with_csr_rw.3689558880 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_errors.1910447739
Short name	T1149
Test name
Test status
Simulation time	172923525 ps
CPU time	3.07 seconds
Started	Feb 04 12:40:01 PM PST 24
Finished	Feb 04 12:40:12 PM PST 24
Peak memory	217620 kb
Host	smart-d8d47203-f7a1-45a2-8cca-6753a5c2bb9b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910447739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.1910447739 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3963943121
Short name	T1250
Test name
Test status
Simulation time	20096172 ps
CPU time	1.61 seconds
Started	Feb 04 12:40:08 PM PST 24
Finished	Feb 04 12:40:22 PM PST 24
Peak memory	222564 kb
Host	smart-06219b4c-d989-4f35-9ec4-05a4ee8b93dc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963943121 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.3963943121 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_rw.1180473007
Short name	T130
Test name
Test status
Simulation time	59897559 ps
CPU time	1.12 seconds
Started	Feb 04 12:40:09 PM PST 24
Finished	Feb 04 12:40:23 PM PST 24
Peak memory	217208 kb
Host	smart-58905f9f-18c4-42c8-8e2d-ebec4fd01725
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180473007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.1180473007 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_intr_test.1403905267
Short name	T1236
Test name
Test status
Simulation time	15253765 ps
CPU time	0.87 seconds
Started	Feb 04 12:40:08 PM PST 24
Finished	Feb 04 12:40:21 PM PST 24
Peak memory	216868 kb
Host	smart-3f096d32-a363-4a8c-8d89-76218705e3cf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403905267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.1403905267 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3949528337
Short name	T1220
Test name
Test status
Simulation time	130356573 ps
CPU time	1.66 seconds
Started	Feb 04 12:40:02 PM PST 24
Finished	Feb 04 12:40:12 PM PST 24
Peak memory	217216 kb
Host	smart-d3df5142-7b4d-4340-b713-46d85e6f3686
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949528337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr _outstanding.3949528337 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.4189574593
Short name	T1224
Test name
Test status
Simulation time	132741449 ps
CPU time	1.31 seconds
Started	Feb 04 12:39:58 PM PST 24
Finished	Feb 04 12:40:05 PM PST 24
Peak memory	217564 kb
Host	smart-5e724985-9079-4dff-b68b-e31628f93985
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189574593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_ errors.4189574593 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.517492523
Short name	T94
Test name
Test status
Simulation time	198386239 ps
CPU time	2.53 seconds
Started	Feb 04 12:40:04 PM PST 24
Finished	Feb 04 12:40:17 PM PST 24
Peak memory	221508 kb
Host	smart-3b5f4786-4127-4742-b652-35de23333f19
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517492523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_ shadow_reg_errors_with_csr_rw.517492523 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_errors.2654934101
Short name	T1139
Test name
Test status
Simulation time	362165741 ps
CPU time	2.82 seconds
Started	Feb 04 12:40:03 PM PST 24
Finished	Feb 04 12:40:17 PM PST 24
Peak memory	217368 kb
Host	smart-4a0fb738-f836-4805-b2f8-18fd3266e1db
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654934101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.2654934101 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.2118940146
Short name	T1244
Test name
Test status
Simulation time	520142157 ps
CPU time	5.61 seconds
Started	Feb 04 12:40:05 PM PST 24
Finished	Feb 04 12:40:24 PM PST 24
Peak memory	217088 kb
Host	smart-cb861f73-d733-4b2a-949b-19ea7881bc85
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118940146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.21189 40146 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2935865668
Short name	T1187
Test name
Test status
Simulation time	27661759 ps
CPU time	2.11 seconds
Started	Feb 04 12:40:10 PM PST 24
Finished	Feb 04 12:40:29 PM PST 24
Peak memory	222144 kb
Host	smart-6903b7bb-c66d-400a-b5cd-3dd2483a72cb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935865668 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.2935865668 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_rw.1693533249
Short name	T1209
Test name
Test status
Simulation time	97859800 ps
CPU time	1.12 seconds
Started	Feb 04 12:40:06 PM PST 24
Finished	Feb 04 12:40:19 PM PST 24
Peak memory	216252 kb
Host	smart-f2d16355-034d-4348-a20f-0b6462533249
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693533249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.1693533249 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_intr_test.1991107109
Short name	T1144
Test name
Test status
Simulation time	15645063 ps
CPU time	0.83 seconds
Started	Feb 04 12:40:06 PM PST 24
Finished	Feb 04 12:40:19 PM PST 24
Peak memory	216452 kb
Host	smart-4cc97768-7b46-4536-92af-34dcfb8af95b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991107109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.1991107109 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.4138277180
Short name	T1207
Test name
Test status
Simulation time	69384015 ps
CPU time	1.93 seconds
Started	Feb 04 12:40:10 PM PST 24
Finished	Feb 04 12:40:28 PM PST 24
Peak memory	216156 kb
Host	smart-438637f0-6037-479e-95fd-cd65fa5c7238
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138277180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr _outstanding.4138277180 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.68146717
Short name	T1164
Test name
Test status
Simulation time	48079624 ps
CPU time	1.66 seconds
Started	Feb 04 12:40:08 PM PST 24
Finished	Feb 04 12:40:22 PM PST 24
Peak memory	217388 kb
Host	smart-a106ad3b-18dc-4d29-9861-c56c5619ec35
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68146717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_s hadow_reg_errors_with_csr_rw.68146717 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_errors.1694096181
Short name	T57
Test name
Test status
Simulation time	32597793 ps
CPU time	2.13 seconds
Started	Feb 04 12:40:09 PM PST 24
Finished	Feb 04 12:40:25 PM PST 24
Peak memory	216200 kb
Host	smart-d201340f-619c-468b-9811-390b7e2a5fec
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694096181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.1694096181 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.1389283928
Short name	T147
Test name
Test status
Simulation time	530755614 ps
CPU time	5.4 seconds
Started	Feb 04 12:40:09 PM PST 24
Finished	Feb 04 12:40:29 PM PST 24
Peak memory	216952 kb
Host	smart-9998e0e5-8124-4469-9a56-11a62abc6396
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389283928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.13892 83928 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_intg_err/latest

Test location	/workspace/coverage/default/0.kmac_alert_test.4267308256
Short name	T857
Test name
Test status
Simulation time	13725575 ps
CPU time	0.92 seconds
Started	Feb 04 02:44:48 PM PST 24
Finished	Feb 04 02:45:05 PM PST 24
Peak memory	219472 kb
Host	smart-15a2ec5a-1aeb-4e9f-9803-c3918d953d34
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267308256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.4267308256 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_alert_test/latest

Test location	/workspace/coverage/default/0.kmac_app_with_partial_data.1275736629
Short name	T556
Test name
Test status
Simulation time	1731974472 ps
CPU time	39.33 seconds
Started	Feb 04 02:44:51 PM PST 24
Finished	Feb 04 02:45:54 PM PST 24
Peak memory	228236 kb
Host	smart-d34fc67a-69b7-4957-b0db-60202ddc243a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1275736629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.1275736629 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/0.kmac_burst_write.2814576773
Short name	T414
Test name
Test status
Simulation time	122002560133 ps
CPU time	642.32 seconds
Started	Feb 04 02:44:46 PM PST 24
Finished	Feb 04 02:55:43 PM PST 24
Peak memory	243412 kb
Host	smart-c1c636e4-6bb6-42e0-8b9f-ba9ae21424cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2814576773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.2814576773 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_burst_write/latest

Test location	/workspace/coverage/default/0.kmac_edn_timeout_error.1185161561
Short name	T644
Test name
Test status
Simulation time	23395277 ps
CPU time	1.07 seconds
Started	Feb 04 02:44:52 PM PST 24
Finished	Feb 04 02:45:16 PM PST 24
Peak memory	218484 kb
Host	smart-68dfad41-92d5-4f0f-b152-4f7f884d179b
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1185161561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.1185161561 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/0.kmac_entropy_refresh.2997327822
Short name	T389
Test name
Test status
Simulation time	11306688087 ps
CPU time	78.72 seconds
Started	Feb 04 02:44:55 PM PST 24
Finished	Feb 04 02:46:35 PM PST 24
Peak memory	232440 kb
Host	smart-93d71cd7-88b5-47d0-8cde-22e367de0805
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2997327822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.2997327822 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/0.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/0.kmac_error.577596044
Short name	T240
Test name
Test status
Simulation time	73749495741 ps
CPU time	346.73 seconds
Started	Feb 04 02:44:54 PM PST 24
Finished	Feb 04 02:51:02 PM PST 24
Peak memory	259796 kb
Host	smart-90f0029e-a7f8-44f6-87fb-5cc603a58d01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=577596044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.577596044 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_error/latest

Test location	/workspace/coverage/default/0.kmac_key_error.325564491
Short name	T696
Test name
Test status
Simulation time	759606171 ps
CPU time	4.75 seconds
Started	Feb 04 02:44:55 PM PST 24
Finished	Feb 04 02:45:21 PM PST 24
Peak memory	218600 kb
Host	smart-2d838f53-b34c-4008-a434-74942c914ac7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=325564491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.325564491 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_key_error/latest

Test location	/workspace/coverage/default/0.kmac_lc_escalation.3928588225
Short name	T770
Test name
Test status
Simulation time	74479633 ps
CPU time	1.53 seconds
Started	Feb 04 02:44:48 PM PST 24
Finished	Feb 04 02:45:06 PM PST 24
Peak memory	219728 kb
Host	smart-ed2417e9-92ad-4fda-a664-502c75afcf07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3928588225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.3928588225 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/0.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/0.kmac_long_msg_and_output.4179424483
Short name	T748
Test name
Test status
Simulation time	22892196475 ps
CPU time	639.5 seconds
Started	Feb 04 02:44:47 PM PST 24
Finished	Feb 04 02:55:43 PM PST 24
Peak memory	269896 kb
Host	smart-c23dde72-fa3e-4041-bd38-5bd1f4cb0e98
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179424483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an d_output.4179424483 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/0.kmac_sideload.984294562
Short name	T960
Test name
Test status
Simulation time	2266035951 ps
CPU time	162.36 seconds
Started	Feb 04 02:44:55 PM PST 24
Finished	Feb 04 02:47:59 PM PST 24
Peak memory	243492 kb
Host	smart-69a6e437-7ee1-48a4-993c-ef35673fc22e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=984294562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.984294562 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_sideload/latest

Test location	/workspace/coverage/default/0.kmac_smoke.578894718
Short name	T614
Test name
Test status
Simulation time	1936639690 ps
CPU time	42.53 seconds
Started	Feb 04 02:44:47 PM PST 24
Finished	Feb 04 02:45:46 PM PST 24
Peak memory	227044 kb
Host	smart-12c55a8a-abea-4b9f-b5f8-a7517c1e5d55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=578894718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.578894718 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_smoke/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_kmac.3659392604
Short name	T25
Test name
Test status
Simulation time	219799113 ps
CPU time	5.39 seconds
Started	Feb 04 02:44:54 PM PST 24
Finished	Feb 04 02:45:21 PM PST 24
Peak memory	218900 kb
Host	smart-2365272b-b877-4c19-a849-ea738e5b0ba4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659392604 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.kmac_test_vectors_kmac.3659392604 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_kmac_xof.2386313767
Short name	T768
Test name
Test status
Simulation time	542370234 ps
CPU time	6.36 seconds
Started	Feb 04 02:44:47 PM PST 24
Finished	Feb 04 02:45:08 PM PST 24
Peak memory	219956 kb
Host	smart-7d243557-94cd-4e3f-b066-2232cfc19e0f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386313767 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.2386313767 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_224.2654836794
Short name	T1054
Test name
Test status
Simulation time	73160053479 ps
CPU time	2308.35 seconds
Started	Feb 04 02:44:59 PM PST 24
Finished	Feb 04 03:23:51 PM PST 24
Peak memory	403624 kb
Host	smart-58521a88-b315-452a-9330-14b3371e3ea2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2654836794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.2654836794 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_256.4040326019
Short name	T1001
Test name
Test status
Simulation time	270949669890 ps
CPU time	2514.38 seconds
Started	Feb 04 02:44:56 PM PST 24
Finished	Feb 04 03:27:12 PM PST 24
Peak memory	390216 kb
Host	smart-4e7f5c3e-576e-44bd-9273-18a342d5c473
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4040326019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.4040326019 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_384.3720861457
Short name	T743
Test name
Test status
Simulation time	15921223386 ps
CPU time	1674.86 seconds
Started	Feb 04 02:44:49 PM PST 24
Finished	Feb 04 03:13:03 PM PST 24
Peak memory	344412 kb
Host	smart-371c66fd-1210-4d95-9da4-14c730c57903
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3720861457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.3720861457 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_512.1998808990
Short name	T411
Test name
Test status
Simulation time	46741884031 ps
CPU time	1301.61 seconds
Started	Feb 04 02:44:41 PM PST 24
Finished	Feb 04 03:06:30 PM PST 24
Peak memory	307300 kb
Host	smart-b1ad08c9-61e6-4e67-ab7d-13c646e0a06d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1998808990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.1998808990 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_shake_128.799529369
Short name	T253
Test name
Test status
Simulation time	61794000940 ps
CPU time	5405.75 seconds
Started	Feb 04 02:44:38 PM PST 24
Finished	Feb 04 04:14:49 PM PST 24
Peak memory	651748 kb
Host	smart-2abed3f6-0223-4d1b-b3dd-2b9506c45746
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=799529369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.799529369 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_shake_256.4117904257
Short name	T184
Test name
Test status
Simulation time	108561493875 ps
CPU time	4397.56 seconds
Started	Feb 04 02:44:50 PM PST 24
Finished	Feb 04 03:58:33 PM PST 24
Peak memory	582672 kb
Host	smart-0bc04c85-baa6-41c9-9564-fcc9d1ebfdc9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4117904257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.4117904257 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/1.kmac_alert_test.77789449
Short name	T364
Test name
Test status
Simulation time	24632301 ps
CPU time	0.83 seconds
Started	Feb 04 02:44:59 PM PST 24
Finished	Feb 04 02:45:23 PM PST 24
Peak memory	218064 kb
Host	smart-4ded4831-e3a7-44fb-96f1-9b22ce81e336
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77789449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.77789449 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/1.kmac_alert_test/latest

Test location	/workspace/coverage/default/1.kmac_app.2391573338
Short name	T642
Test name
Test status
Simulation time	2292893128 ps
CPU time	74.52 seconds
Started	Feb 04 02:44:55 PM PST 24
Finished	Feb 04 02:46:31 PM PST 24
Peak memory	231628 kb
Host	smart-2c2baae3-2ddb-4ca7-8b2b-1471220e9766
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2391573338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.2391573338 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_app/latest

Test location	/workspace/coverage/default/1.kmac_app_with_partial_data.1622398090
Short name	T320
Test name
Test status
Simulation time	12119763557 ps
CPU time	347.54 seconds
Started	Feb 04 02:44:56 PM PST 24
Finished	Feb 04 02:51:04 PM PST 24
Peak memory	252660 kb
Host	smart-a35c2e58-a1e7-43d5-82fa-204f3da68d99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1622398090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.1622398090 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/1.kmac_burst_write.3207677191
Short name	T991
Test name
Test status
Simulation time	38086918905 ps
CPU time	1510.44 seconds
Started	Feb 04 02:44:46 PM PST 24
Finished	Feb 04 03:10:08 PM PST 24
Peak memory	241540 kb
Host	smart-a0f34a9f-c7b5-4a8e-8509-33e2f8482ad1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3207677191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.3207677191 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_burst_write/latest

Test location	/workspace/coverage/default/1.kmac_edn_timeout_error.514402870
Short name	T198
Test name
Test status
Simulation time	6231713722 ps
CPU time	41.78 seconds
Started	Feb 04 02:44:52 PM PST 24
Finished	Feb 04 02:45:57 PM PST 24
Peak memory	237636 kb
Host	smart-ed36d339-64f8-4df1-88a3-503b30a5c155
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=514402870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.514402870 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/1.kmac_entropy_mode_error.3468958623
Short name	T1015
Test name
Test status
Simulation time	13062977 ps
CPU time	0.85 seconds
Started	Feb 04 02:44:55 PM PST 24
Finished	Feb 04 02:45:18 PM PST 24
Peak memory	218460 kb
Host	smart-12a35084-43c8-4b17-83a3-41a799a7b1b6
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3468958623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.3468958623 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/1.kmac_entropy_ready_error.3681367087
Short name	T499
Test name
Test status
Simulation time	14015989400 ps
CPU time	35.38 seconds
Started	Feb 04 02:44:54 PM PST 24
Finished	Feb 04 02:45:51 PM PST 24
Peak memory	227068 kb
Host	smart-5b28aa86-eb8b-432e-a9db-746a7428d668
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3681367087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.3681367087 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/1.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/1.kmac_entropy_refresh.2482013304
Short name	T851
Test name
Test status
Simulation time	37515575587 ps
CPU time	279.3 seconds
Started	Feb 04 02:44:54 PM PST 24
Finished	Feb 04 02:49:55 PM PST 24
Peak memory	247752 kb
Host	smart-f3515606-749d-494b-b355-701b8e6fad4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2482013304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.2482013304 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/1.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/1.kmac_key_error.2436046284
Short name	T522
Test name
Test status
Simulation time	652454315 ps
CPU time	4.32 seconds
Started	Feb 04 02:44:53 PM PST 24
Finished	Feb 04 02:45:19 PM PST 24
Peak memory	218532 kb
Host	smart-c9c4b9ab-4aaa-48ea-8d33-a05fef7c7354
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2436046284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.2436046284 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_key_error/latest

Test location	/workspace/coverage/default/1.kmac_lc_escalation.2998421129
Short name	T333
Test name
Test status
Simulation time	46943119 ps
CPU time	1.55 seconds
Started	Feb 04 02:44:55 PM PST 24
Finished	Feb 04 02:45:18 PM PST 24
Peak memory	219836 kb
Host	smart-8c919abf-b50e-4290-bf24-a1cb97b29154
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2998421129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.2998421129 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/1.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/1.kmac_long_msg_and_output.1220277852
Short name	T929
Test name
Test status
Simulation time	262478455921 ps
CPU time	2212.11 seconds
Started	Feb 04 02:44:41 PM PST 24
Finished	Feb 04 03:21:40 PM PST 24
Peak memory	403216 kb
Host	smart-dc959dc3-37be-4729-8ed9-c76e75475292
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220277852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an d_output.1220277852 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/1.kmac_mubi.2007963211
Short name	T451
Test name
Test status
Simulation time	10871484524 ps
CPU time	355.28 seconds
Started	Feb 04 02:44:55 PM PST 24
Finished	Feb 04 02:51:12 PM PST 24
Peak memory	254456 kb
Host	smart-d4bbf000-c288-4094-ae33-94738a713691
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2007963211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.2007963211 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_mubi/latest

Test location	/workspace/coverage/default/1.kmac_sec_cm.1966964274
Short name	T96
Test name
Test status
Simulation time	30382964184 ps
CPU time	112.69 seconds
Started	Feb 04 02:44:54 PM PST 24
Finished	Feb 04 02:47:08 PM PST 24
Peak memory	302704 kb
Host	smart-e7a6758a-48ac-4494-bd52-ff2322a46c5e
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966964274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.1966964274 +enable_maski ng=1 +sw_key_masked=0
Directory	/workspace/1.kmac_sec_cm/latest

Test location	/workspace/coverage/default/1.kmac_sideload.2628630216
Short name	T1075
Test name
Test status
Simulation time	8353884866 ps
CPU time	174.06 seconds
Started	Feb 04 02:44:52 PM PST 24
Finished	Feb 04 02:48:09 PM PST 24
Peak memory	237884 kb
Host	smart-e17e431c-44d5-4234-98eb-45dbcf06ae3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2628630216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.2628630216 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_sideload/latest

Test location	/workspace/coverage/default/1.kmac_smoke.2138467313
Short name	T566
Test name
Test status
Simulation time	41825548 ps
CPU time	1.21 seconds
Started	Feb 04 02:44:46 PM PST 24
Finished	Feb 04 02:44:58 PM PST 24
Peak memory	218576 kb
Host	smart-96571882-a806-400e-9e76-e46fe9411756
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2138467313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.2138467313 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_smoke/latest

Test location	/workspace/coverage/default/1.kmac_stress_all.735524043
Short name	T401
Test name
Test status
Simulation time	185159830024 ps
CPU time	2740.37 seconds
Started	Feb 04 02:44:53 PM PST 24
Finished	Feb 04 03:30:56 PM PST 24
Peak memory	449800 kb
Host	smart-122cc5b2-81f1-45a9-9f54-30550d22a054
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=735524043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.735524043 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_stress_all/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_kmac.588146898
Short name	T873
Test name
Test status
Simulation time	371555162 ps
CPU time	6.52 seconds
Started	Feb 04 02:44:49 PM PST 24
Finished	Feb 04 02:45:14 PM PST 24
Peak memory	218896 kb
Host	smart-a5879ce4-132b-4d22-89d9-f353d709c976
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588146898 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.kmac_test_vectors_kmac.588146898 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_kmac_xof.1639119971
Short name	T1115
Test name
Test status
Simulation time	190063563 ps
CPU time	5.61 seconds
Started	Feb 04 02:44:54 PM PST 24
Finished	Feb 04 02:45:21 PM PST 24
Peak memory	220284 kb
Host	smart-900a0c59-e298-4b52-b231-41b0e6898469
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639119971 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.1639119971 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_224.2061446513
Short name	T804
Test name
Test status
Simulation time	67455188748 ps
CPU time	2274.16 seconds
Started	Feb 04 02:44:41 PM PST 24
Finished	Feb 04 03:22:42 PM PST 24
Peak memory	395724 kb
Host	smart-8496179c-6fac-4d8f-9587-2b17ee48fab1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2061446513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.2061446513 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_256.4039929835
Short name	T438
Test name
Test status
Simulation time	19567366988 ps
CPU time	2015.3 seconds
Started	Feb 04 02:44:53 PM PST 24
Finished	Feb 04 03:18:50 PM PST 24
Peak memory	387984 kb
Host	smart-9876f570-343f-4eb5-98c2-6a655bc0f081
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4039929835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.4039929835 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_384.3082479367
Short name	T436
Test name
Test status
Simulation time	190407268270 ps
CPU time	1740.54 seconds
Started	Feb 04 02:44:57 PM PST 24
Finished	Feb 04 03:14:19 PM PST 24
Peak memory	342656 kb
Host	smart-f2a12ce2-9fbd-42f3-b861-5c5bc7e60194
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3082479367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.3082479367 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_512.613597351
Short name	T541
Test name
Test status
Simulation time	16271000015 ps
CPU time	1268.38 seconds
Started	Feb 04 02:44:48 PM PST 24
Finished	Feb 04 03:06:14 PM PST 24
Peak memory	307472 kb
Host	smart-54bc96fc-6b0b-4469-a88a-8787ba5b09a6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=613597351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.613597351 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_shake_128.2260120089
Short name	T550
Test name
Test status
Simulation time	1024008997860 ps
CPU time	6555.04 seconds
Started	Feb 04 02:44:55 PM PST 24
Finished	Feb 04 04:34:32 PM PST 24
Peak memory	659108 kb
Host	smart-978cd253-579a-4cc8-a0aa-7115700a9211
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2260120089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.2260120089 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_shake_256.2380475104
Short name	T699
Test name
Test status
Simulation time	214046446242 ps
CPU time	5159.57 seconds
Started	Feb 04 02:44:55 PM PST 24
Finished	Feb 04 04:11:17 PM PST 24
Peak memory	587544 kb
Host	smart-59c4f905-260f-4614-83b0-641fbbeac654
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2380475104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.2380475104 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/10.kmac_alert_test.1612030552
Short name	T635
Test name
Test status
Simulation time	17321936 ps
CPU time	0.9 seconds
Started	Feb 04 02:45:51 PM PST 24
Finished	Feb 04 02:45:54 PM PST 24
Peak memory	218360 kb
Host	smart-b28a4c29-abee-4a7a-b864-04ffaf384c97
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612030552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.1612030552 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_alert_test/latest

Test location	/workspace/coverage/default/10.kmac_app.696330961
Short name	T307
Test name
Test status
Simulation time	24414095481 ps
CPU time	231.69 seconds
Started	Feb 04 02:45:45 PM PST 24
Finished	Feb 04 02:49:42 PM PST 24
Peak memory	245528 kb
Host	smart-a4502988-b1de-4ef1-a5de-ad9f485cb2e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=696330961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.696330961 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_app/latest

Test location	/workspace/coverage/default/10.kmac_burst_write.1995173146
Short name	T361
Test name
Test status
Simulation time	7146194035 ps
CPU time	378.82 seconds
Started	Feb 04 02:45:45 PM PST 24
Finished	Feb 04 02:52:09 PM PST 24
Peak memory	232508 kb
Host	smart-5d650c5e-762c-4e57-ab2d-5d5d8491fa27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1995173146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.1995173146 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_burst_write/latest

Test location	/workspace/coverage/default/10.kmac_entropy_mode_error.1122895544
Short name	T863
Test name
Test status
Simulation time	35440175 ps
CPU time	0.92 seconds
Started	Feb 04 02:45:42 PM PST 24
Finished	Feb 04 02:45:49 PM PST 24
Peak memory	218008 kb
Host	smart-5246e32b-22a6-4e02-baa3-6c309ea51abb
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1122895544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.1122895544 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/10.kmac_entropy_refresh.4131307134
Short name	T425
Test name
Test status
Simulation time	7717192342 ps
CPU time	203.61 seconds
Started	Feb 04 02:45:41 PM PST 24
Finished	Feb 04 02:49:12 PM PST 24
Peak memory	240796 kb
Host	smart-aab2be09-e8a4-4a9c-9ff5-d83bab30a307
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4131307134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.4131307134 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/10.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/10.kmac_error.2148732246
Short name	T466
Test name
Test status
Simulation time	9222124457 ps
CPU time	41.83 seconds
Started	Feb 04 02:45:41 PM PST 24
Finished	Feb 04 02:46:30 PM PST 24
Peak memory	243476 kb
Host	smart-dd9c6ce1-ffa2-427e-998d-5082b950108a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2148732246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.2148732246 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_error/latest

Test location	/workspace/coverage/default/10.kmac_key_error.1239757065
Short name	T848
Test name
Test status
Simulation time	535607521 ps
CPU time	3.93 seconds
Started	Feb 04 02:45:50 PM PST 24
Finished	Feb 04 02:45:57 PM PST 24
Peak memory	218620 kb
Host	smart-a4822e6f-f215-4558-9b3d-87aac0286774
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1239757065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.1239757065 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_key_error/latest

Test location	/workspace/coverage/default/10.kmac_lc_escalation.3320804882
Short name	T11
Test name
Test status
Simulation time	109402983 ps
CPU time	1.4 seconds
Started	Feb 04 02:45:53 PM PST 24
Finished	Feb 04 02:46:02 PM PST 24
Peak memory	219764 kb
Host	smart-9c2fec41-e1b3-4f1a-8a85-3f230f9d1502
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3320804882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.3320804882 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/10.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/10.kmac_long_msg_and_output.3972567471
Short name	T810
Test name
Test status
Simulation time	20353741480 ps
CPU time	508.2 seconds
Started	Feb 04 02:45:41 PM PST 24
Finished	Feb 04 02:54:17 PM PST 24
Peak memory	264208 kb
Host	smart-e085b031-2a37-4ac7-936f-84bcf05bfcbd
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972567471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a nd_output.3972567471 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/10.kmac_sideload.1806802500
Short name	T1002
Test name
Test status
Simulation time	1621677281 ps
CPU time	47.8 seconds
Started	Feb 04 02:45:42 PM PST 24
Finished	Feb 04 02:46:36 PM PST 24
Peak memory	227344 kb
Host	smart-7e9ac241-4060-41d7-9038-f9409ec04773
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1806802500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.1806802500 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_sideload/latest

Test location	/workspace/coverage/default/10.kmac_smoke.383411858
Short name	T1117
Test name
Test status
Simulation time	1181778453 ps
CPU time	2.96 seconds
Started	Feb 04 02:45:42 PM PST 24
Finished	Feb 04 02:45:51 PM PST 24
Peak memory	218624 kb
Host	smart-59323da0-84e3-4999-a2d2-bc706482b7c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=383411858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.383411858 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_smoke/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_kmac.2815003619
Short name	T693
Test name
Test status
Simulation time	381805751 ps
CPU time	6.22 seconds
Started	Feb 04 02:45:42 PM PST 24
Finished	Feb 04 02:45:54 PM PST 24
Peak memory	219956 kb
Host	smart-05fdcd13-8a08-4081-ab80-70b03e47c431
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815003619 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.kmac_test_vectors_kmac.2815003619 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_kmac_xof.3881210783
Short name	T999
Test name
Test status
Simulation time	497912442 ps
CPU time	6.66 seconds
Started	Feb 04 02:45:49 PM PST 24
Finished	Feb 04 02:45:59 PM PST 24
Peak memory	220172 kb
Host	smart-52fe52e4-84f5-4781-9a58-aa134ab20b74
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881210783 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_kmac_xof.3881210783 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_224.2610728125
Short name	T909
Test name
Test status
Simulation time	23277046176 ps
CPU time	2117.56 seconds
Started	Feb 04 02:45:45 PM PST 24
Finished	Feb 04 03:21:08 PM PST 24
Peak memory	401248 kb
Host	smart-8ea66925-9346-4602-a612-09cde6938b7b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2610728125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.2610728125 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_256.3749571936
Short name	T638
Test name
Test status
Simulation time	250712078050 ps
CPU time	2319.08 seconds
Started	Feb 04 02:45:50 PM PST 24
Finished	Feb 04 03:24:32 PM PST 24
Peak memory	392416 kb
Host	smart-ef896223-f1cc-4b73-b18c-57fc19bd5afb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3749571936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.3749571936 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_384.3561010711
Short name	T1084
Test name
Test status
Simulation time	94714950226 ps
CPU time	1642.58 seconds
Started	Feb 04 02:45:50 PM PST 24
Finished	Feb 04 03:13:16 PM PST 24
Peak memory	335820 kb
Host	smart-3125779a-1d98-4618-8a63-e6cf54c36ec1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3561010711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.3561010711 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_512.4094423866
Short name	T1069
Test name
Test status
Simulation time	42388731844 ps
CPU time	1235.28 seconds
Started	Feb 04 02:45:46 PM PST 24
Finished	Feb 04 03:06:26 PM PST 24
Peak memory	303172 kb
Host	smart-dbcefbe5-fbbb-4559-810c-28f980cf0546
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4094423866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.4094423866 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_shake_128.2370959826
Short name	T796
Test name
Test status
Simulation time	724677254705 ps
CPU time	5858.77 seconds
Started	Feb 04 02:45:50 PM PST 24
Finished	Feb 04 04:23:33 PM PST 24
Peak memory	673500 kb
Host	smart-0d84a4c9-e3bc-4b0e-9fb7-b0ca6cbbb57a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2370959826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.2370959826 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_shake_256.2093903861
Short name	T897
Test name
Test status
Simulation time	198926404964 ps
CPU time	5115.5 seconds
Started	Feb 04 02:45:50 PM PST 24
Finished	Feb 04 04:11:09 PM PST 24
Peak memory	566876 kb
Host	smart-0198124d-4bf0-4743-ab8b-5cb753e5262f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2093903861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.2093903861 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/11.kmac_alert_test.1355056717
Short name	T272
Test name
Test status
Simulation time	57408097 ps
CPU time	0.87 seconds
Started	Feb 04 02:46:06 PM PST 24
Finished	Feb 04 02:46:10 PM PST 24
Peak memory	219424 kb
Host	smart-73b89097-e4c3-4f68-a930-8cd92c986102
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355056717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.1355056717 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_alert_test/latest

Test location	/workspace/coverage/default/11.kmac_app.4056301842
Short name	T626
Test name
Test status
Simulation time	3112118444 ps
CPU time	183.08 seconds
Started	Feb 04 02:45:54 PM PST 24
Finished	Feb 04 02:49:05 PM PST 24
Peak memory	243428 kb
Host	smart-72e5b89c-c855-4054-9bd4-f53cc4836e76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4056301842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.4056301842 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_app/latest

Test location	/workspace/coverage/default/11.kmac_burst_write.2626639193
Short name	T867
Test name
Test status
Simulation time	75234991112 ps
CPU time	704.69 seconds
Started	Feb 04 02:45:56 PM PST 24
Finished	Feb 04 02:57:47 PM PST 24
Peak memory	236020 kb
Host	smart-ac494ff6-c3a0-49f8-b378-51dfcc31126e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2626639193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.2626639193 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_burst_write/latest

Test location	/workspace/coverage/default/11.kmac_edn_timeout_error.2194926656
Short name	T88
Test name
Test status
Simulation time	111647723 ps
CPU time	3.9 seconds
Started	Feb 04 02:46:05 PM PST 24
Finished	Feb 04 02:46:12 PM PST 24
Peak memory	225680 kb
Host	smart-95a90f83-da59-4108-9f36-e1f79f4f3ee5
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2194926656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.2194926656 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/11.kmac_entropy_mode_error.2147592605
Short name	T568
Test name
Test status
Simulation time	43088506 ps
CPU time	1.19 seconds
Started	Feb 04 02:46:03 PM PST 24
Finished	Feb 04 02:46:07 PM PST 24
Peak memory	218600 kb
Host	smart-767ebdbd-f938-4649-a65b-aba72f76181d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2147592605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.2147592605 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/11.kmac_entropy_refresh.3843900722
Short name	T249
Test name
Test status
Simulation time	43530662918 ps
CPU time	291.78 seconds
Started	Feb 04 02:45:52 PM PST 24
Finished	Feb 04 02:50:45 PM PST 24
Peak memory	248400 kb
Host	smart-0d81ca69-ea5d-4484-9225-9575dfd976cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3843900722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.3843900722 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/11.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/11.kmac_error.1395115006
Short name	T1114
Test name
Test status
Simulation time	12399004772 ps
CPU time	414.18 seconds
Started	Feb 04 02:45:58 PM PST 24
Finished	Feb 04 02:52:56 PM PST 24
Peak memory	259888 kb
Host	smart-6b31cc92-070a-4d31-b1c9-a7b13a29b0d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1395115006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.1395115006 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_error/latest

Test location	/workspace/coverage/default/11.kmac_key_error.3447293989
Short name	T22
Test name
Test status
Simulation time	1324137775 ps
CPU time	4.43 seconds
Started	Feb 04 02:46:02 PM PST 24
Finished	Feb 04 02:46:09 PM PST 24
Peak memory	218656 kb
Host	smart-ba28d0ff-ae9e-418d-a14e-d35afdbf65bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3447293989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.3447293989 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_key_error/latest

Test location	/workspace/coverage/default/11.kmac_lc_escalation.1324365075
Short name	T870
Test name
Test status
Simulation time	118391507 ps
CPU time	1.33 seconds
Started	Feb 04 02:46:08 PM PST 24
Finished	Feb 04 02:46:12 PM PST 24
Peak memory	219812 kb
Host	smart-60f620d0-bf1a-4425-a2e3-fbc4239d556d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1324365075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.1324365075 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/11.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/11.kmac_long_msg_and_output.4141773800
Short name	T892
Test name
Test status
Simulation time	200998835702 ps
CPU time	506.06 seconds
Started	Feb 04 02:45:53 PM PST 24
Finished	Feb 04 02:54:27 PM PST 24
Peak memory	255612 kb
Host	smart-33e1c737-a70e-4b36-89d4-99cd1ccfa7e3
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141773800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a nd_output.4141773800 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/11.kmac_sideload.80557399
Short name	T1018
Test name
Test status
Simulation time	11645410619 ps
CPU time	377.31 seconds
Started	Feb 04 02:45:50 PM PST 24
Finished	Feb 04 02:52:10 PM PST 24
Peak memory	252552 kb
Host	smart-40230cd8-086a-4a86-9969-652e8e003855
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=80557399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.80557399 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_sideload/latest

Test location	/workspace/coverage/default/11.kmac_smoke.1257281800
Short name	T746
Test name
Test status
Simulation time	4911700915 ps
CPU time	70.55 seconds
Started	Feb 04 02:46:00 PM PST 24
Finished	Feb 04 02:47:13 PM PST 24
Peak memory	226972 kb
Host	smart-54ce4fed-7d6c-46ec-b5f8-a6b9a4587034
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1257281800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.1257281800 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_smoke/latest

Test location	/workspace/coverage/default/11.kmac_stress_all.3336708954
Short name	T82
Test name
Test status
Simulation time	302240497975 ps
CPU time	2145 seconds
Started	Feb 04 02:46:04 PM PST 24
Finished	Feb 04 03:21:53 PM PST 24
Peak memory	406468 kb
Host	smart-43377eeb-1b50-4444-ac1e-e8c72926cd91
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3336708954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.3336708954 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_stress_all/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_kmac.1434348293
Short name	T667
Test name
Test status
Simulation time	353739797 ps
CPU time	5.62 seconds
Started	Feb 04 02:46:04 PM PST 24
Finished	Feb 04 02:46:13 PM PST 24
Peak memory	220276 kb
Host	smart-809379af-36cf-497c-b7e4-c8ce769b8c11
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434348293 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.kmac_test_vectors_kmac.1434348293 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_kmac_xof.3727013465
Short name	T205
Test name
Test status
Simulation time	957341578 ps
CPU time	6.36 seconds
Started	Feb 04 02:46:00 PM PST 24
Finished	Feb 04 02:46:09 PM PST 24
Peak memory	218892 kb
Host	smart-e4b24a41-3b12-4a5b-afc4-88c30473604c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727013465 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_kmac_xof.3727013465 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_224.3757553061
Short name	T842
Test name
Test status
Simulation time	99142851919 ps
CPU time	2458.44 seconds
Started	Feb 04 02:46:03 PM PST 24
Finished	Feb 04 03:27:05 PM PST 24
Peak memory	406864 kb
Host	smart-bbb8784b-d397-4c8c-82cc-46adbe85cf40
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3757553061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.3757553061 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_256.577987929
Short name	T108
Test name
Test status
Simulation time	147949114647 ps
CPU time	2176.58 seconds
Started	Feb 04 02:46:03 PM PST 24
Finished	Feb 04 03:22:23 PM PST 24
Peak memory	398428 kb
Host	smart-5c883fdb-9bd9-4c6d-ba7d-66aebc40aeb2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=577987929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.577987929 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_384.3978532768
Short name	T177
Test name
Test status
Simulation time	30057290069 ps
CPU time	1371.4 seconds
Started	Feb 04 02:45:52 PM PST 24
Finished	Feb 04 03:08:49 PM PST 24
Peak memory	337764 kb
Host	smart-0dd25ffd-9c43-4f88-927c-e75e2265768b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3978532768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.3978532768 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_512.2681766118
Short name	T1004
Test name
Test status
Simulation time	49432377917 ps
CPU time	1291.6 seconds
Started	Feb 04 02:45:53 PM PST 24
Finished	Feb 04 03:07:33 PM PST 24
Peak memory	303372 kb
Host	smart-65ced9c6-5fe2-4058-ae7b-96d03141fdd8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2681766118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.2681766118 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_shake_256.3590155608
Short name	T1116
Test name
Test status
Simulation time	878783808391 ps
CPU time	5924.45 seconds
Started	Feb 04 02:45:54 PM PST 24
Finished	Feb 04 04:24:47 PM PST 24
Peak memory	577932 kb
Host	smart-77d086a9-e713-4e64-aad0-72ac2ad666cd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3590155608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.3590155608 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/12.kmac_app.3577113677
Short name	T955
Test name
Test status
Simulation time	158376695217 ps
CPU time	365.14 seconds
Started	Feb 04 02:46:05 PM PST 24
Finished	Feb 04 02:52:14 PM PST 24
Peak memory	252104 kb
Host	smart-e8688d59-1276-44e8-b473-128081dd210d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3577113677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.3577113677 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_app/latest

Test location	/workspace/coverage/default/12.kmac_burst_write.3539109901
Short name	T1009
Test name
Test status
Simulation time	34134986581 ps
CPU time	1173.51 seconds
Started	Feb 04 02:46:06 PM PST 24
Finished	Feb 04 03:05:43 PM PST 24
Peak memory	243500 kb
Host	smart-efb976df-6234-4bb3-89a6-b9a157296bc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3539109901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.3539109901 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_burst_write/latest

Test location	/workspace/coverage/default/12.kmac_edn_timeout_error.2381897385
Short name	T792
Test name
Test status
Simulation time	40513611 ps
CPU time	2.76 seconds
Started	Feb 04 02:46:05 PM PST 24
Finished	Feb 04 02:46:11 PM PST 24
Peak memory	224972 kb
Host	smart-8161b034-d849-4d93-b133-66827cd45f1a
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2381897385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.2381897385 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/12.kmac_entropy_mode_error.3104904408
Short name	T615
Test name
Test status
Simulation time	111240174 ps
CPU time	1.24 seconds
Started	Feb 04 02:46:14 PM PST 24
Finished	Feb 04 02:46:17 PM PST 24
Peak memory	218640 kb
Host	smart-e35cb77f-a3bf-4c40-a5d4-99f4cb79a13f
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3104904408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.3104904408 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/12.kmac_entropy_refresh.2660719011
Short name	T981
Test name
Test status
Simulation time	12805779437 ps
CPU time	311.66 seconds
Started	Feb 04 02:46:05 PM PST 24
Finished	Feb 04 02:51:21 PM PST 24
Peak memory	248676 kb
Host	smart-aa5ab0a7-c127-4c89-aa1f-3d1dc8d7289a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2660719011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.2660719011 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/12.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/12.kmac_error.2142103713
Short name	T469
Test name
Test status
Simulation time	3669778028 ps
CPU time	151.58 seconds
Started	Feb 04 02:46:07 PM PST 24
Finished	Feb 04 02:48:42 PM PST 24
Peak memory	251576 kb
Host	smart-1679e9b8-8f32-46a2-8a57-630eedba574d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2142103713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.2142103713 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_error/latest

Test location	/workspace/coverage/default/12.kmac_key_error.2548515076
Short name	T1123
Test name
Test status
Simulation time	248270921 ps
CPU time	1.12 seconds
Started	Feb 04 02:46:07 PM PST 24
Finished	Feb 04 02:46:11 PM PST 24
Peak memory	218516 kb
Host	smart-2f59a3c9-36f9-4a82-8129-d2f12c729099
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2548515076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.2548515076 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_key_error/latest

Test location	/workspace/coverage/default/12.kmac_lc_escalation.1674528833
Short name	T882
Test name
Test status
Simulation time	57578336 ps
CPU time	1.57 seconds
Started	Feb 04 02:46:22 PM PST 24
Finished	Feb 04 02:46:28 PM PST 24
Peak memory	219760 kb
Host	smart-556155e6-cde8-4f52-9f67-0466f49228c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1674528833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.1674528833 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/12.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/12.kmac_long_msg_and_output.3542291407
Short name	T525
Test name
Test status
Simulation time	48854840630 ps
CPU time	2633.32 seconds
Started	Feb 04 02:46:04 PM PST 24
Finished	Feb 04 03:30:00 PM PST 24
Peak memory	446928 kb
Host	smart-fd23b816-6a9e-409e-84fc-adc2ece337d2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542291407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a nd_output.3542291407 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/12.kmac_sideload.3530476819
Short name	T908
Test name
Test status
Simulation time	14743890660 ps
CPU time	377.49 seconds
Started	Feb 04 02:46:07 PM PST 24
Finished	Feb 04 02:52:28 PM PST 24
Peak memory	249344 kb
Host	smart-96d7025e-dc23-439e-bd94-24b3bc3e2348
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3530476819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.3530476819 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_sideload/latest

Test location	/workspace/coverage/default/12.kmac_smoke.2491993940
Short name	T820
Test name
Test status
Simulation time	287318910 ps
CPU time	2.65 seconds
Started	Feb 04 02:46:07 PM PST 24
Finished	Feb 04 02:46:13 PM PST 24
Peak memory	226764 kb
Host	smart-5ae8e0d3-62fc-423b-8747-76aa128f3c00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2491993940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.2491993940 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_smoke/latest

Test location	/workspace/coverage/default/12.kmac_stress_all.3296510643
Short name	T367
Test name
Test status
Simulation time	21743519394 ps
CPU time	442.69 seconds
Started	Feb 04 02:46:14 PM PST 24
Finished	Feb 04 02:53:38 PM PST 24
Peak memory	276552 kb
Host	smart-b99ca00f-46a7-4dde-911b-78bf70bf1954
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3296510643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.3296510643 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_stress_all/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_kmac.3475513185
Short name	T1008
Test name
Test status
Simulation time	179509835 ps
CPU time	5.38 seconds
Started	Feb 04 02:46:04 PM PST 24
Finished	Feb 04 02:46:11 PM PST 24
Peak memory	218820 kb
Host	smart-33164cf9-f06e-4006-b385-4eae09bd7063
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475513185 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 12.kmac_test_vectors_kmac.3475513185 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_kmac_xof.736003838
Short name	T408
Test name
Test status
Simulation time	227730673 ps
CPU time	5.9 seconds
Started	Feb 04 02:46:04 PM PST 24
Finished	Feb 04 02:46:13 PM PST 24
Peak memory	220128 kb
Host	smart-172ccfad-f5fc-42c9-801a-e19a940e73e6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736003838 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 12.kmac_test_vectors_kmac_xof.736003838 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_224.2447607542
Short name	T839
Test name
Test status
Simulation time	96290706754 ps
CPU time	2422.48 seconds
Started	Feb 04 02:46:07 PM PST 24
Finished	Feb 04 03:26:33 PM PST 24
Peak memory	391412 kb
Host	smart-3d90d294-b1b3-4b59-b323-8a4b91afe990
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2447607542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.2447607542 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_256.517333942
Short name	T731
Test name
Test status
Simulation time	61916735234 ps
CPU time	2181.25 seconds
Started	Feb 04 02:46:03 PM PST 24
Finished	Feb 04 03:22:27 PM PST 24
Peak memory	377308 kb
Host	smart-8cf2a67c-cb7b-4d86-97fe-8b3f531836f8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=517333942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.517333942 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_384.3842887612
Short name	T688
Test name
Test status
Simulation time	263744909630 ps
CPU time	1682.54 seconds
Started	Feb 04 02:46:03 PM PST 24
Finished	Feb 04 03:14:09 PM PST 24
Peak memory	341504 kb
Host	smart-01007acc-9168-4989-86c6-e9d04fea7d95
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3842887612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.3842887612 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_512.571900714
Short name	T505
Test name
Test status
Simulation time	105476220316 ps
CPU time	1144.44 seconds
Started	Feb 04 02:46:04 PM PST 24
Finished	Feb 04 03:05:12 PM PST 24
Peak memory	299436 kb
Host	smart-1920a56a-633a-4226-a770-dc2b36ecbc48
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=571900714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.571900714 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_shake_128.762016087
Short name	T591
Test name
Test status
Simulation time	235579492255 ps
CPU time	5365.32 seconds
Started	Feb 04 02:46:07 PM PST 24
Finished	Feb 04 04:15:36 PM PST 24
Peak memory	654228 kb
Host	smart-38b47163-e882-4a81-8bf4-3d6cad4edd53
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=762016087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.762016087 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_shake_256.2397784099
Short name	T485
Test name
Test status
Simulation time	622136090840 ps
CPU time	5480.28 seconds
Started	Feb 04 02:46:03 PM PST 24
Finished	Feb 04 04:17:26 PM PST 24
Peak memory	561312 kb
Host	smart-ec260a46-0a63-40a9-8fc7-0991e5586466
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2397784099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.2397784099 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/13.kmac_alert_test.525492035
Short name	T1046
Test name
Test status
Simulation time	17538904 ps
CPU time	0.87 seconds
Started	Feb 04 02:46:17 PM PST 24
Finished	Feb 04 02:46:21 PM PST 24
Peak memory	218264 kb
Host	smart-2b5b013c-190f-4e91-8d12-aaa4fcce15b6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525492035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.525492035 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_alert_test/latest

Test location	/workspace/coverage/default/13.kmac_app.2341761125
Short name	T815
Test name
Test status
Simulation time	1700687420 ps
CPU time	38.03 seconds
Started	Feb 04 02:46:17 PM PST 24
Finished	Feb 04 02:46:57 PM PST 24
Peak memory	227100 kb
Host	smart-c716b702-ecca-41a8-b129-a9dd1dabed5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2341761125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.2341761125 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_app/latest

Test location	/workspace/coverage/default/13.kmac_burst_write.3426407230
Short name	T380
Test name
Test status
Simulation time	11013605041 ps
CPU time	1376.93 seconds
Started	Feb 04 02:46:20 PM PST 24
Finished	Feb 04 03:09:21 PM PST 24
Peak memory	243156 kb
Host	smart-10cb3c19-12b7-4afd-81c7-c12b2b675c4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3426407230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.3426407230 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_burst_write/latest

Test location	/workspace/coverage/default/13.kmac_edn_timeout_error.2228619044
Short name	T80
Test name
Test status
Simulation time	28591037 ps
CPU time	1.09 seconds
Started	Feb 04 02:46:15 PM PST 24
Finished	Feb 04 02:46:18 PM PST 24
Peak memory	218488 kb
Host	smart-63c4d085-e358-4a58-a223-b6fbe079e8fc
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2228619044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.2228619044 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/13.kmac_entropy_mode_error.924292242
Short name	T174
Test name
Test status
Simulation time	263407279 ps
CPU time	7.11 seconds
Started	Feb 04 02:46:16 PM PST 24
Finished	Feb 04 02:46:24 PM PST 24
Peak memory	224076 kb
Host	smart-e0a8c4c8-b62f-44e0-8a9e-82698bc58cda
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=924292242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.924292242 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/13.kmac_entropy_refresh.249895880
Short name	T35
Test name
Test status
Simulation time	2395166511 ps
CPU time	62.32 seconds
Started	Feb 04 02:46:17 PM PST 24
Finished	Feb 04 02:47:23 PM PST 24
Peak memory	231060 kb
Host	smart-9fe9d148-b3e7-44d5-8a90-05fb89c33d4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=249895880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.249895880 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/13.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/13.kmac_error.4023645758
Short name	T1132
Test name
Test status
Simulation time	51327517993 ps
CPU time	455.93 seconds
Started	Feb 04 02:46:18 PM PST 24
Finished	Feb 04 02:53:57 PM PST 24
Peak memory	265824 kb
Host	smart-5fd6e887-3378-43a6-b49a-e8465eeaca70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4023645758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.4023645758 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_error/latest

Test location	/workspace/coverage/default/13.kmac_key_error.2476413405
Short name	T778
Test name
Test status
Simulation time	2002464468 ps
CPU time	4.93 seconds
Started	Feb 04 02:46:13 PM PST 24
Finished	Feb 04 02:46:19 PM PST 24
Peak memory	218620 kb
Host	smart-3ae7c990-4d1b-4102-8be4-b9243b88b4e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2476413405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.2476413405 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_key_error/latest

Test location	/workspace/coverage/default/13.kmac_lc_escalation.714394304
Short name	T277
Test name
Test status
Simulation time	56218941 ps
CPU time	1.35 seconds
Started	Feb 04 02:46:18 PM PST 24
Finished	Feb 04 02:46:22 PM PST 24
Peak memory	220824 kb
Host	smart-3f2c8cae-a519-4303-84a3-94fcb55ab1cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=714394304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.714394304 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/13.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/13.kmac_long_msg_and_output.4148451991
Short name	T182
Test name
Test status
Simulation time	38041910918 ps
CPU time	754.35 seconds
Started	Feb 04 02:46:13 PM PST 24
Finished	Feb 04 02:58:49 PM PST 24
Peak memory	276908 kb
Host	smart-0c987cf0-9602-4f33-92c6-90cd6cc639ae
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148451991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a nd_output.4148451991 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/13.kmac_sideload.820145862
Short name	T783
Test name
Test status
Simulation time	5060065787 ps
CPU time	481 seconds
Started	Feb 04 02:46:13 PM PST 24
Finished	Feb 04 02:54:15 PM PST 24
Peak memory	255156 kb
Host	smart-a86c9e92-bd1f-4db8-95b6-4e831c367413
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=820145862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.820145862 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_sideload/latest

Test location	/workspace/coverage/default/13.kmac_smoke.3898968215
Short name	T493
Test name
Test status
Simulation time	12404235165 ps
CPU time	73.11 seconds
Started	Feb 04 02:46:18 PM PST 24
Finished	Feb 04 02:47:34 PM PST 24
Peak memory	226940 kb
Host	smart-2a623180-4fa9-4d23-adba-afd4e9942a99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3898968215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.3898968215 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_smoke/latest

Test location	/workspace/coverage/default/13.kmac_stress_all.212383513
Short name	T1131
Test name
Test status
Simulation time	18333932291 ps
CPU time	121.42 seconds
Started	Feb 04 02:46:20 PM PST 24
Finished	Feb 04 02:48:25 PM PST 24
Peak memory	243448 kb
Host	smart-0ee16c31-fecb-4077-a225-234644e66498
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=212383513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.212383513 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_stress_all/latest

Test location	/workspace/coverage/default/13.kmac_stress_all_with_rand_reset.2037679302
Short name	T761
Test name
Test status
Simulation time	49773680049 ps
CPU time	1214.22 seconds
Started	Feb 04 02:46:17 PM PST 24
Finished	Feb 04 03:06:35 PM PST 24
Peak memory	325368 kb
Host	smart-b50361bb-4adf-4ffe-866f-90f4dec976a6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2037679302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all_with_rand_reset.2037679302 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_kmac.1388493172
Short name	T677
Test name
Test status
Simulation time	471726853 ps
CPU time	6.37 seconds
Started	Feb 04 02:46:15 PM PST 24
Finished	Feb 04 02:46:23 PM PST 24
Peak memory	218776 kb
Host	smart-bf6c8ed9-fa34-4333-a23d-3728e7bc442b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388493172 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 13.kmac_test_vectors_kmac.1388493172 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_kmac_xof.1735199764
Short name	T821
Test name
Test status
Simulation time	247167648 ps
CPU time	6.23 seconds
Started	Feb 04 02:46:16 PM PST 24
Finished	Feb 04 02:46:23 PM PST 24
Peak memory	220300 kb
Host	smart-0eb2139e-36b8-49f3-8a35-557567e3088f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735199764 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_kmac_xof.1735199764 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_224.4131286554
Short name	T1090
Test name
Test status
Simulation time	21224936257 ps
CPU time	2134.62 seconds
Started	Feb 04 02:46:16 PM PST 24
Finished	Feb 04 03:21:52 PM PST 24
Peak memory	399568 kb
Host	smart-bc54e56c-2f69-4914-8a98-4e208a6fa258
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4131286554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.4131286554 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_256.972517163
Short name	T254
Test name
Test status
Simulation time	20252389819 ps
CPU time	2082.92 seconds
Started	Feb 04 02:46:13 PM PST 24
Finished	Feb 04 03:20:57 PM PST 24
Peak memory	396324 kb
Host	smart-76cc9eac-b487-4e16-95e3-27b1f8d74294
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=972517163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.972517163 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_384.4141477234
Short name	T27
Test name
Test status
Simulation time	306173229980 ps
CPU time	1542.09 seconds
Started	Feb 04 02:46:13 PM PST 24
Finished	Feb 04 03:11:56 PM PST 24
Peak memory	332572 kb
Host	smart-48704366-d3e6-4e4d-be51-8048ad6e81bc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4141477234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.4141477234 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_512.2004719082
Short name	T256
Test name
Test status
Simulation time	41531905337 ps
CPU time	1038.78 seconds
Started	Feb 04 02:46:15 PM PST 24
Finished	Feb 04 03:03:35 PM PST 24
Peak memory	297764 kb
Host	smart-2156a21d-6a57-49a3-a74d-70380d16d789
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2004719082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.2004719082 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_shake_128.2650382541
Short name	T752
Test name
Test status
Simulation time	260952007801 ps
CPU time	6473.19 seconds
Started	Feb 04 02:46:18 PM PST 24
Finished	Feb 04 04:34:15 PM PST 24
Peak memory	648260 kb
Host	smart-5a09f2b3-c2dd-4a77-9025-d8b09d2753e0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2650382541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.2650382541 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_shake_256.3952049373
Short name	T478
Test name
Test status
Simulation time	629096331490 ps
CPU time	5582.57 seconds
Started	Feb 04 02:46:17 PM PST 24
Finished	Feb 04 04:19:24 PM PST 24
Peak memory	575268 kb
Host	smart-629007b0-cc28-4e3b-a225-418fb666f89e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3952049373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.3952049373 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/14.kmac_alert_test.872346612
Short name	T365
Test name
Test status
Simulation time	60915047 ps
CPU time	0.86 seconds
Started	Feb 04 02:46:14 PM PST 24
Finished	Feb 04 02:46:16 PM PST 24
Peak memory	218416 kb
Host	smart-4575ff44-8cb2-4ebb-966a-676d7e0ba1b2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872346612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.872346612 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_alert_test/latest

Test location	/workspace/coverage/default/14.kmac_app.3858953419
Short name	T1043
Test name
Test status
Simulation time	4292383063 ps
CPU time	253.53 seconds
Started	Feb 04 02:46:18 PM PST 24
Finished	Feb 04 02:50:35 PM PST 24
Peak memory	248016 kb
Host	smart-f941e635-b37c-4df0-8e0d-09e486c18b7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3858953419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.3858953419 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_app/latest

Test location	/workspace/coverage/default/14.kmac_burst_write.382723985
Short name	T384
Test name
Test status
Simulation time	490937763 ps
CPU time	44.65 seconds
Started	Feb 04 02:46:17 PM PST 24
Finished	Feb 04 02:47:03 PM PST 24
Peak memory	228296 kb
Host	smart-bdb30b7d-fe41-4609-bfa7-83818d05ac1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=382723985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.382723985 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_burst_write/latest

Test location	/workspace/coverage/default/14.kmac_edn_timeout_error.3212253934
Short name	T678
Test name
Test status
Simulation time	19125585 ps
CPU time	1 seconds
Started	Feb 04 02:46:13 PM PST 24
Finished	Feb 04 02:46:15 PM PST 24
Peak memory	218436 kb
Host	smart-959732c6-a383-45d1-8c23-408e4ccab2fb
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3212253934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.3212253934 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/14.kmac_entropy_mode_error.2453882361
Short name	T524
Test name
Test status
Simulation time	32412027 ps
CPU time	1.17 seconds
Started	Feb 04 02:46:17 PM PST 24
Finished	Feb 04 02:46:20 PM PST 24
Peak memory	218552 kb
Host	smart-35845c9d-a081-42c1-a41b-183fa8ca702f
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2453882361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.2453882361 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/14.kmac_entropy_refresh.2789136807
Short name	T1039
Test name
Test status
Simulation time	10435824629 ps
CPU time	205.49 seconds
Started	Feb 04 02:46:17 PM PST 24
Finished	Feb 04 02:49:45 PM PST 24
Peak memory	241348 kb
Host	smart-69f31652-b21c-4a7a-9c43-bf0136c990b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789136807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.2789136807 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/14.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/14.kmac_error.2179824826
Short name	T590
Test name
Test status
Simulation time	4252508790 ps
CPU time	182.46 seconds
Started	Feb 04 02:46:16 PM PST 24
Finished	Feb 04 02:49:21 PM PST 24
Peak memory	252528 kb
Host	smart-4d6e7293-b229-4cdd-94fa-4b6197f4118a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2179824826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.2179824826 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_error/latest

Test location	/workspace/coverage/default/14.kmac_key_error.2988955541
Short name	T533
Test name
Test status
Simulation time	1992614421 ps
CPU time	3.52 seconds
Started	Feb 04 02:46:17 PM PST 24
Finished	Feb 04 02:46:22 PM PST 24
Peak memory	218648 kb
Host	smart-08385c4d-8681-4322-9eec-847f99955da6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2988955541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.2988955541 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_key_error/latest

Test location	/workspace/coverage/default/14.kmac_lc_escalation.1031257697
Short name	T319
Test name
Test status
Simulation time	597294983 ps
CPU time	1.44 seconds
Started	Feb 04 02:46:16 PM PST 24
Finished	Feb 04 02:46:20 PM PST 24
Peak memory	219720 kb
Host	smart-54961ab6-2f9c-4a49-947e-fa388f90dc00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1031257697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.1031257697 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/14.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/14.kmac_long_msg_and_output.531767548
Short name	T1005
Test name
Test status
Simulation time	5715543712 ps
CPU time	216.78 seconds
Started	Feb 04 02:46:13 PM PST 24
Finished	Feb 04 02:49:51 PM PST 24
Peak memory	243572 kb
Host	smart-4d7a6670-635b-423a-91ac-cdab51e6ffef
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531767548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_an d_output.531767548 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/14.kmac_sideload.2683708924
Short name	T889
Test name
Test status
Simulation time	14050042025 ps
CPU time	482.21 seconds
Started	Feb 04 02:46:13 PM PST 24
Finished	Feb 04 02:54:16 PM PST 24
Peak memory	256928 kb
Host	smart-bcb1d560-248d-48b1-9456-50ef2bff0e28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2683708924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.2683708924 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_sideload/latest

Test location	/workspace/coverage/default/14.kmac_smoke.1410815345
Short name	T255
Test name
Test status
Simulation time	2704734816 ps
CPU time	53.03 seconds
Started	Feb 04 02:46:15 PM PST 24
Finished	Feb 04 02:47:10 PM PST 24
Peak memory	219884 kb
Host	smart-a1b2de91-77b0-43e9-b9df-87f9b08b0388
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1410815345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.1410815345 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_smoke/latest

Test location	/workspace/coverage/default/14.kmac_stress_all.1536610513
Short name	T812
Test name
Test status
Simulation time	56625464576 ps
CPU time	1477.79 seconds
Started	Feb 04 02:46:13 PM PST 24
Finished	Feb 04 03:10:52 PM PST 24
Peak memory	387304 kb
Host	smart-a44d2743-9aff-40be-bad2-e5852dba4431
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1536610513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.1536610513 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_stress_all/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_kmac.2952472406
Short name	T599
Test name
Test status
Simulation time	478238311 ps
CPU time	7.15 seconds
Started	Feb 04 02:46:16 PM PST 24
Finished	Feb 04 02:46:25 PM PST 24
Peak memory	220276 kb
Host	smart-82e40360-5ead-43b0-8920-fec9dd7560f8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952472406 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.kmac_test_vectors_kmac.2952472406 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_kmac_xof.4086051025
Short name	T353
Test name
Test status
Simulation time	247475310 ps
CPU time	6.43 seconds
Started	Feb 04 02:46:20 PM PST 24
Finished	Feb 04 02:46:30 PM PST 24
Peak memory	218880 kb
Host	smart-e934bc9f-45ea-4948-a3bb-4cd14be7b6bc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086051025 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_kmac_xof.4086051025 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_224.444119931
Short name	T179
Test name
Test status
Simulation time	68611005764 ps
CPU time	2255.41 seconds
Started	Feb 04 02:46:22 PM PST 24
Finished	Feb 04 03:24:02 PM PST 24
Peak memory	401908 kb
Host	smart-a0d70492-b2c6-4ea9-b395-7ba261ec8905
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=444119931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.444119931 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_256.132333268
Short name	T26
Test name
Test status
Simulation time	23399966145 ps
CPU time	2028.74 seconds
Started	Feb 04 02:46:12 PM PST 24
Finished	Feb 04 03:20:02 PM PST 24
Peak memory	386292 kb
Host	smart-cb3b88a7-10f5-41bc-808b-e3e9d4b4786a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=132333268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.132333268 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_384.728453903
Short name	T759
Test name
Test status
Simulation time	147134626024 ps
CPU time	1972.25 seconds
Started	Feb 04 02:46:20 PM PST 24
Finished	Feb 04 03:19:16 PM PST 24
Peak memory	341588 kb
Host	smart-27b44875-4d8b-4088-bbd4-edd27d79f0ce
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=728453903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.728453903 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_512.1117805442
Short name	T371
Test name
Test status
Simulation time	88567214112 ps
CPU time	1327.34 seconds
Started	Feb 04 02:46:14 PM PST 24
Finished	Feb 04 03:08:23 PM PST 24
Peak memory	305128 kb
Host	smart-6e25390f-6e70-4e28-b1cf-d7c792ad51bf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1117805442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.1117805442 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_shake_128.319700789
Short name	T859
Test name
Test status
Simulation time	234083217989 ps
CPU time	5621.5 seconds
Started	Feb 04 02:46:18 PM PST 24
Finished	Feb 04 04:20:03 PM PST 24
Peak memory	658432 kb
Host	smart-933d63e5-5e49-4ea4-a568-98fc36c437d5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=319700789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.319700789 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_shake_256.2051445592
Short name	T1105
Test name
Test status
Simulation time	237367636582 ps
CPU time	4568.5 seconds
Started	Feb 04 02:46:16 PM PST 24
Finished	Feb 04 04:02:26 PM PST 24
Peak memory	567936 kb
Host	smart-c7cec655-693b-4f06-8073-742be65acd5a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2051445592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.2051445592 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/15.kmac_alert_test.1601426698
Short name	T805
Test name
Test status
Simulation time	18409952 ps
CPU time	0.84 seconds
Started	Feb 04 02:46:27 PM PST 24
Finished	Feb 04 02:46:40 PM PST 24
Peak memory	218308 kb
Host	smart-e0523934-fa2f-4d3c-bd1f-c35d7d766182
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601426698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.1601426698 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_alert_test/latest

Test location	/workspace/coverage/default/15.kmac_app.1357568363
Short name	T802
Test name
Test status
Simulation time	8321564068 ps
CPU time	170.71 seconds
Started	Feb 04 02:46:26 PM PST 24
Finished	Feb 04 02:49:23 PM PST 24
Peak memory	238764 kb
Host	smart-fbdd6a55-4d62-4878-90a5-210ecde1d4ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1357568363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.1357568363 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_app/latest

Test location	/workspace/coverage/default/15.kmac_burst_write.816183013
Short name	T1074
Test name
Test status
Simulation time	23316162353 ps
CPU time	482.61 seconds
Started	Feb 04 02:46:25 PM PST 24
Finished	Feb 04 02:54:29 PM PST 24
Peak memory	232368 kb
Host	smart-f5fb9563-3af1-4d3b-89c4-da15c33b733e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=816183013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.816183013 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_burst_write/latest

Test location	/workspace/coverage/default/15.kmac_edn_timeout_error.1991201218
Short name	T30
Test name
Test status
Simulation time	3399591424 ps
CPU time	33.58 seconds
Started	Feb 04 02:46:31 PM PST 24
Finished	Feb 04 02:47:13 PM PST 24
Peak memory	236180 kb
Host	smart-97c29519-9260-4d05-b757-42e29880422b
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1991201218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.1991201218 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/15.kmac_entropy_mode_error.863932569
Short name	T295
Test name
Test status
Simulation time	3475050634 ps
CPU time	26.8 seconds
Started	Feb 04 02:46:29 PM PST 24
Finished	Feb 04 02:47:06 PM PST 24
Peak memory	235204 kb
Host	smart-c7145a39-f4ad-4084-9f92-1feceaac30b1
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=863932569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.863932569 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/15.kmac_entropy_refresh.2057886137
Short name	T405
Test name
Test status
Simulation time	870405918 ps
CPU time	9.86 seconds
Started	Feb 04 02:46:29 PM PST 24
Finished	Feb 04 02:46:50 PM PST 24
Peak memory	227236 kb
Host	smart-04811c52-9f44-4606-a328-807126bd1f3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2057886137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.2057886137 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/15.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/15.kmac_error.720857363
Short name	T513
Test name
Test status
Simulation time	4030952581 ps
CPU time	346.13 seconds
Started	Feb 04 02:46:28 PM PST 24
Finished	Feb 04 02:52:26 PM PST 24
Peak memory	253324 kb
Host	smart-0e9133c8-4be1-4cbb-b12f-18ae931aeff9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=720857363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.720857363 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_error/latest

Test location	/workspace/coverage/default/15.kmac_key_error.3194551092
Short name	T612
Test name
Test status
Simulation time	556610298 ps
CPU time	3.88 seconds
Started	Feb 04 02:46:28 PM PST 24
Finished	Feb 04 02:46:44 PM PST 24
Peak memory	218664 kb
Host	smart-b89fe67e-2208-47a5-a44f-8602b8465db6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3194551092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.3194551092 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_key_error/latest

Test location	/workspace/coverage/default/15.kmac_long_msg_and_output.777426925
Short name	T417
Test name
Test status
Simulation time	112346090171 ps
CPU time	1011.79 seconds
Started	Feb 04 02:46:25 PM PST 24
Finished	Feb 04 03:03:19 PM PST 24
Peak memory	301916 kb
Host	smart-6dc165b9-64ea-4b14-a95a-90bc6de3b3aa
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777426925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_an d_output.777426925 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/15.kmac_sideload.2630220318
Short name	T653
Test name
Test status
Simulation time	12595746679 ps
CPU time	127.25 seconds
Started	Feb 04 02:46:29 PM PST 24
Finished	Feb 04 02:48:47 PM PST 24
Peak memory	233728 kb
Host	smart-7a80d6f3-5c03-4c4c-8d5e-e6c2c384642e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2630220318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.2630220318 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_sideload/latest

Test location	/workspace/coverage/default/15.kmac_smoke.72013104
Short name	T858
Test name
Test status
Simulation time	1428039349 ps
CPU time	51.35 seconds
Started	Feb 04 02:46:30 PM PST 24
Finished	Feb 04 02:47:31 PM PST 24
Peak memory	227016 kb
Host	smart-d9f83c31-41de-433a-8fa7-33e8922ff891
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=72013104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.72013104 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_smoke/latest

Test location	/workspace/coverage/default/15.kmac_stress_all.3114954024
Short name	T248
Test name
Test status
Simulation time	69944182945 ps
CPU time	1515.01 seconds
Started	Feb 04 02:46:27 PM PST 24
Finished	Feb 04 03:11:55 PM PST 24
Peak memory	357888 kb
Host	smart-ca2234f9-ce9e-4a4e-b37f-4198efb7d6aa
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3114954024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.3114954024 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_stress_all/latest

Test location	/workspace/coverage/default/15.kmac_stress_all_with_rand_reset.11823967
Short name	T490
Test name
Test status
Simulation time	247097682613 ps
CPU time	1477.97 seconds
Started	Feb 04 02:46:28 PM PST 24
Finished	Feb 04 03:11:18 PM PST 24
Peak memory	319832 kb
Host	smart-5fa59c0f-c226-482c-8bb9-97f350257270
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=11823967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all_with_rand_reset.11823967 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_kmac.3280885969
Short name	T554
Test name
Test status
Simulation time	187319818 ps
CPU time	5.74 seconds
Started	Feb 04 02:46:29 PM PST 24
Finished	Feb 04 02:46:45 PM PST 24
Peak memory	220312 kb
Host	smart-08fcbd40-d9dd-4808-8d57-600843e5db25
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280885969 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.kmac_test_vectors_kmac.3280885969 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_kmac_xof.2396997787
Short name	T511
Test name
Test status
Simulation time	856129642 ps
CPU time	5.2 seconds
Started	Feb 04 02:46:25 PM PST 24
Finished	Feb 04 02:46:32 PM PST 24
Peak memory	218920 kb
Host	smart-847dd728-5ae9-4843-9c92-9d9cef10ac8d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396997787 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_kmac_xof.2396997787 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_224.1935150072
Short name	T502
Test name
Test status
Simulation time	104409398316 ps
CPU time	2596.85 seconds
Started	Feb 04 02:46:30 PM PST 24
Finished	Feb 04 03:29:57 PM PST 24
Peak memory	406204 kb
Host	smart-f6a8558e-d194-441b-8919-dee426c5f2ed
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1935150072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.1935150072 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_256.3150879893
Short name	T844
Test name
Test status
Simulation time	187670284971 ps
CPU time	2234.1 seconds
Started	Feb 04 02:46:27 PM PST 24
Finished	Feb 04 03:23:54 PM PST 24
Peak memory	387972 kb
Host	smart-69b21b02-aa43-45ea-9240-36f7cda11f8d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3150879893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.3150879893 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_384.1099100099
Short name	T284
Test name
Test status
Simulation time	21835581962 ps
CPU time	1851.53 seconds
Started	Feb 04 02:46:31 PM PST 24
Finished	Feb 04 03:17:32 PM PST 24
Peak memory	343304 kb
Host	smart-8128728d-067f-43ff-9c33-6333ebb9f22e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1099100099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.1099100099 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_512.784029515
Short name	T771
Test name
Test status
Simulation time	11692527533 ps
CPU time	1284.02 seconds
Started	Feb 04 02:46:30 PM PST 24
Finished	Feb 04 03:08:04 PM PST 24
Peak memory	302464 kb
Host	smart-d3d8d3a2-4495-4347-840f-a06063c0aa8b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=784029515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.784029515 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_shake_128.1195456539
Short name	T1000
Test name
Test status
Simulation time	225945589526 ps
CPU time	5941.03 seconds
Started	Feb 04 02:46:27 PM PST 24
Finished	Feb 04 04:25:41 PM PST 24
Peak memory	657880 kb
Host	smart-27d51a2c-c682-4750-ab96-96ef55a65757
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1195456539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.1195456539 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_shake_256.2198570
Short name	T153
Test name
Test status
Simulation time	2410293891263 ps
CPU time	6190.88 seconds
Started	Feb 04 02:46:26 PM PST 24
Finished	Feb 04 04:29:43 PM PST 24
Peak memory	568332 kb
Host	smart-744ebc9e-9858-4f0d-bdc7-a3e1e7534823
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2198570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.2198570 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/16.kmac_alert_test.3376635376
Short name	T637
Test name
Test status
Simulation time	34729117 ps
CPU time	0.78 seconds
Started	Feb 04 02:46:42 PM PST 24
Finished	Feb 04 02:46:44 PM PST 24
Peak memory	219316 kb
Host	smart-151687a0-f68c-4ad2-a60c-4cae07c4b0d8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376635376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.3376635376 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_alert_test/latest

Test location	/workspace/coverage/default/16.kmac_app.610755474
Short name	T208
Test name
Test status
Simulation time	880406579 ps
CPU time	16.12 seconds
Started	Feb 04 02:46:35 PM PST 24
Finished	Feb 04 02:46:57 PM PST 24
Peak memory	227020 kb
Host	smart-6e5c767a-4df7-4e7c-9993-bc252827c251
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=610755474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.610755474 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_app/latest

Test location	/workspace/coverage/default/16.kmac_burst_write.276397804
Short name	T990
Test name
Test status
Simulation time	9669850546 ps
CPU time	444.58 seconds
Started	Feb 04 02:46:43 PM PST 24
Finished	Feb 04 02:54:08 PM PST 24
Peak memory	243316 kb
Host	smart-504a8461-dd52-4c8a-9bf7-e73b32c12eb8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=276397804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.276397804 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_burst_write/latest

Test location	/workspace/coverage/default/16.kmac_edn_timeout_error.1230267424
Short name	T77
Test name
Test status
Simulation time	79626292 ps
CPU time	1.07 seconds
Started	Feb 04 02:46:34 PM PST 24
Finished	Feb 04 02:46:42 PM PST 24
Peak memory	218560 kb
Host	smart-2bbd4d68-04f3-4674-9137-688bd18df10d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1230267424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.1230267424 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/16.kmac_entropy_mode_error.1356481070
Short name	T716
Test name
Test status
Simulation time	23001097 ps
CPU time	1.15 seconds
Started	Feb 04 02:46:39 PM PST 24
Finished	Feb 04 02:46:43 PM PST 24
Peak memory	218656 kb
Host	smart-33ffad13-827f-40b1-a741-cabdbd1d1827
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1356481070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.1356481070 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/16.kmac_entropy_refresh.3216786784
Short name	T758
Test name
Test status
Simulation time	32136800362 ps
CPU time	313.28 seconds
Started	Feb 04 02:46:37 PM PST 24
Finished	Feb 04 02:51:55 PM PST 24
Peak memory	250068 kb
Host	smart-47f7068c-6cb1-41d9-8d61-801c47750cd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3216786784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.3216786784 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/16.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/16.kmac_error.2526048028
Short name	T261
Test name
Test status
Simulation time	9443024061 ps
CPU time	58.97 seconds
Started	Feb 04 02:46:39 PM PST 24
Finished	Feb 04 02:47:41 PM PST 24
Peak memory	238216 kb
Host	smart-abfabeba-12a4-4aa1-8fe5-b157832d90df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2526048028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.2526048028 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_error/latest

Test location	/workspace/coverage/default/16.kmac_key_error.2407244643
Short name	T973
Test name
Test status
Simulation time	668243978 ps
CPU time	3.91 seconds
Started	Feb 04 02:46:32 PM PST 24
Finished	Feb 04 02:46:44 PM PST 24
Peak memory	218788 kb
Host	smart-7e39ecb5-294f-44cc-971d-1cae7db90481
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2407244643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.2407244643 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_key_error/latest

Test location	/workspace/coverage/default/16.kmac_lc_escalation.2174270700
Short name	T440
Test name
Test status
Simulation time	61469380 ps
CPU time	1.22 seconds
Started	Feb 04 02:46:36 PM PST 24
Finished	Feb 04 02:46:42 PM PST 24
Peak memory	219704 kb
Host	smart-821ac311-1ca3-46fb-b545-66730feda51e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2174270700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.2174270700 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/16.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/16.kmac_long_msg_and_output.910257544
Short name	T708
Test name
Test status
Simulation time	97949498197 ps
CPU time	1095.54 seconds
Started	Feb 04 02:46:31 PM PST 24
Finished	Feb 04 03:04:55 PM PST 24
Peak memory	314960 kb
Host	smart-807a2732-da43-4f90-a158-189a149ceb28
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910257544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_an d_output.910257544 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/16.kmac_sideload.3683908675
Short name	T835
Test name
Test status
Simulation time	30505447292 ps
CPU time	117.77 seconds
Started	Feb 04 02:46:26 PM PST 24
Finished	Feb 04 02:48:30 PM PST 24
Peak memory	234136 kb
Host	smart-c4dd187d-0503-4518-ab84-b74641e37216
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3683908675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.3683908675 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_sideload/latest

Test location	/workspace/coverage/default/16.kmac_smoke.835903676
Short name	T207
Test name
Test status
Simulation time	1865447090 ps
CPU time	53.05 seconds
Started	Feb 04 02:46:31 PM PST 24
Finished	Feb 04 02:47:33 PM PST 24
Peak memory	226924 kb
Host	smart-1f9ae092-9587-4767-a2af-f5534161e16c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=835903676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.835903676 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_smoke/latest

Test location	/workspace/coverage/default/16.kmac_stress_all.2453497344
Short name	T395
Test name
Test status
Simulation time	65432587683 ps
CPU time	1970.6 seconds
Started	Feb 04 02:46:33 PM PST 24
Finished	Feb 04 03:19:32 PM PST 24
Peak memory	410880 kb
Host	smart-55691692-e847-434e-9796-df16aa565697
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2453497344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.2453497344 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_stress_all/latest

Test location	/workspace/coverage/default/16.kmac_stress_all_with_rand_reset.1365581650
Short name	T782
Test name
Test status
Simulation time	18623694973 ps
CPU time	880.31 seconds
Started	Feb 04 02:46:34 PM PST 24
Finished	Feb 04 03:01:21 PM PST 24
Peak memory	293080 kb
Host	smart-a76cc966-3a4c-45a7-b388-f94fceff6c7e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1365581650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all_with_rand_reset.1365581650 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_kmac.2164461714
Short name	T498
Test name
Test status
Simulation time	1062563318 ps
CPU time	6.05 seconds
Started	Feb 04 02:46:37 PM PST 24
Finished	Feb 04 02:46:48 PM PST 24
Peak memory	218796 kb
Host	smart-3e1d9532-e1c7-4806-9f93-c1d7b9d9ccae
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164461714 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.kmac_test_vectors_kmac.2164461714 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_kmac_xof.3283312946
Short name	T925
Test name
Test status
Simulation time	1331512061 ps
CPU time	6.25 seconds
Started	Feb 04 02:46:35 PM PST 24
Finished	Feb 04 02:46:47 PM PST 24
Peak memory	218784 kb
Host	smart-9c43b533-c03e-4534-94db-25f7eb3224ae
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283312946 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_kmac_xof.3283312946 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_224.285344364
Short name	T606
Test name
Test status
Simulation time	270791928836 ps
CPU time	2314.91 seconds
Started	Feb 04 02:46:33 PM PST 24
Finished	Feb 04 03:25:16 PM PST 24
Peak memory	396832 kb
Host	smart-f45595d5-f77f-40de-911a-a0b03836a8e6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=285344364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.285344364 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_256.2944347449
Short name	T453
Test name
Test status
Simulation time	283591128019 ps
CPU time	2265.08 seconds
Started	Feb 04 02:46:36 PM PST 24
Finished	Feb 04 03:24:26 PM PST 24
Peak memory	391748 kb
Host	smart-f7e397d4-10cb-4d57-8c28-1ac6feec0a75
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2944347449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.2944347449 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_384.4009221566
Short name	T242
Test name
Test status
Simulation time	531551210806 ps
CPU time	1959.84 seconds
Started	Feb 04 02:46:37 PM PST 24
Finished	Feb 04 03:19:21 PM PST 24
Peak memory	343384 kb
Host	smart-a3c3e315-7d06-4067-bd0f-25ffc81c853f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4009221566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.4009221566 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_512.1314669655
Short name	T647
Test name
Test status
Simulation time	214818639386 ps
CPU time	1547.76 seconds
Started	Feb 04 02:46:33 PM PST 24
Finished	Feb 04 03:12:29 PM PST 24
Peak memory	303812 kb
Host	smart-487b657c-ba47-407c-bc2d-eb1122a66023
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1314669655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.1314669655 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_shake_128.4227194908
Short name	T1040
Test name
Test status
Simulation time	724269999005 ps
CPU time	6189.57 seconds
Started	Feb 04 02:46:32 PM PST 24
Finished	Feb 04 04:29:51 PM PST 24
Peak memory	637920 kb
Host	smart-1ebb8bb6-ed9a-4abb-a5e1-c428e1604664
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4227194908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.4227194908 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_shake_256.2018750149
Short name	T893
Test name
Test status
Simulation time	682545109312 ps
CPU time	5215.92 seconds
Started	Feb 04 02:46:37 PM PST 24
Finished	Feb 04 04:13:38 PM PST 24
Peak memory	564696 kb
Host	smart-15c237c0-5609-40be-bec5-aa856190f7c0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2018750149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.2018750149 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/17.kmac_alert_test.891032400
Short name	T1007
Test name
Test status
Simulation time	31916511 ps
CPU time	0.85 seconds
Started	Feb 04 02:46:48 PM PST 24
Finished	Feb 04 02:46:50 PM PST 24
Peak memory	219496 kb
Host	smart-9f9887ca-a416-4d64-8723-2eb88c20e0bb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891032400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.891032400 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_alert_test/latest

Test location	/workspace/coverage/default/17.kmac_app.1128807543
Short name	T400
Test name
Test status
Simulation time	14618987771 ps
CPU time	422.2 seconds
Started	Feb 04 02:46:36 PM PST 24
Finished	Feb 04 02:53:43 PM PST 24
Peak memory	253980 kb
Host	smart-4891129b-9f9d-4d8e-a99c-3bdb9bbbfb23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1128807543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.1128807543 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_app/latest

Test location	/workspace/coverage/default/17.kmac_burst_write.441585041
Short name	T362
Test name
Test status
Simulation time	4492214959 ps
CPU time	534.43 seconds
Started	Feb 04 02:46:33 PM PST 24
Finished	Feb 04 02:55:36 PM PST 24
Peak memory	232812 kb
Host	smart-97cf040a-3fd6-420a-9ed3-cf2f0df075f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=441585041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.441585041 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_burst_write/latest

Test location	/workspace/coverage/default/17.kmac_edn_timeout_error.2322606866
Short name	T683
Test name
Test status
Simulation time	63881873 ps
CPU time	1.29 seconds
Started	Feb 04 02:46:34 PM PST 24
Finished	Feb 04 02:46:42 PM PST 24
Peak memory	218784 kb
Host	smart-3eb288ec-d241-4162-b4fd-f446236f2afa
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2322606866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.2322606866 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/17.kmac_entropy_mode_error.3778966222
Short name	T902
Test name
Test status
Simulation time	78352405 ps
CPU time	0.97 seconds
Started	Feb 04 02:46:34 PM PST 24
Finished	Feb 04 02:46:42 PM PST 24
Peak memory	218380 kb
Host	smart-1c7628a6-4c26-4177-aee8-93ffb5e9b1eb
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3778966222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.3778966222 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/17.kmac_entropy_refresh.2274019593
Short name	T940
Test name
Test status
Simulation time	19371717274 ps
CPU time	32.8 seconds
Started	Feb 04 02:46:38 PM PST 24
Finished	Feb 04 02:47:15 PM PST 24
Peak memory	235348 kb
Host	smart-a4bc8584-0bec-46ad-8448-653559df2469
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2274019593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.2274019593 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/17.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/17.kmac_error.1064800215
Short name	T357
Test name
Test status
Simulation time	1641857217 ps
CPU time	44.94 seconds
Started	Feb 04 02:46:42 PM PST 24
Finished	Feb 04 02:47:28 PM PST 24
Peak memory	243132 kb
Host	smart-285ebf1d-e69f-4cd8-b880-e4ee23fe0b5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1064800215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.1064800215 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_error/latest

Test location	/workspace/coverage/default/17.kmac_key_error.355962954
Short name	T399
Test name
Test status
Simulation time	225027885 ps
CPU time	2.12 seconds
Started	Feb 04 02:46:36 PM PST 24
Finished	Feb 04 02:46:43 PM PST 24
Peak memory	218672 kb
Host	smart-ccfad417-9b7b-4bcb-9667-9c2dace4b2f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=355962954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.355962954 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_key_error/latest

Test location	/workspace/coverage/default/17.kmac_lc_escalation.1752837198
Short name	T1076
Test name
Test status
Simulation time	219055571 ps
CPU time	1.34 seconds
Started	Feb 04 02:46:43 PM PST 24
Finished	Feb 04 02:46:45 PM PST 24
Peak memory	220352 kb
Host	smart-eeeef957-4eab-4f9a-8ac9-4cbb354efc33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1752837198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.1752837198 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/17.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/17.kmac_long_msg_and_output.4023843384
Short name	T818
Test name
Test status
Simulation time	516080054467 ps
CPU time	3067.07 seconds
Started	Feb 04 02:46:37 PM PST 24
Finished	Feb 04 03:37:49 PM PST 24
Peak memory	451312 kb
Host	smart-1e65d9f6-f94d-49a4-a177-f992bfa09bcf
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023843384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a nd_output.4023843384 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/17.kmac_sideload.1948349773
Short name	T507
Test name
Test status
Simulation time	18958475426 ps
CPU time	160.36 seconds
Started	Feb 04 02:46:34 PM PST 24
Finished	Feb 04 02:49:21 PM PST 24
Peak memory	236588 kb
Host	smart-28d09730-1b4b-450d-a853-61d3a2a51967
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1948349773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.1948349773 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_sideload/latest

Test location	/workspace/coverage/default/17.kmac_smoke.501742838
Short name	T283
Test name
Test status
Simulation time	4106731605 ps
CPU time	10.8 seconds
Started	Feb 04 02:46:38 PM PST 24
Finished	Feb 04 02:46:53 PM PST 24
Peak memory	227124 kb
Host	smart-acf93c72-ab2e-4101-ae1e-c6d794a3f330
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=501742838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.501742838 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_smoke/latest

Test location	/workspace/coverage/default/17.kmac_stress_all.266418491
Short name	T766
Test name
Test status
Simulation time	418805017801 ps
CPU time	2897.6 seconds
Started	Feb 04 02:46:34 PM PST 24
Finished	Feb 04 03:34:59 PM PST 24
Peak memory	440432 kb
Host	smart-e93f57b9-6015-477b-a816-620e73b2eccb
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=266418491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.266418491 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_stress_all/latest

Test location	/workspace/coverage/default/17.kmac_stress_all_with_rand_reset.217238652
Short name	T475
Test name
Test status
Simulation time	1419050251728 ps
CPU time	4595.32 seconds
Started	Feb 04 02:46:37 PM PST 24
Finished	Feb 04 04:03:17 PM PST 24
Peak memory	452360 kb
Host	smart-8b127e2d-35cd-4f56-a914-d6f73e207bcb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=217238652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all_with_rand_reset.217238652 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_kmac.1745660169
Short name	T523
Test name
Test status
Simulation time	121958744 ps
CPU time	6.82 seconds
Started	Feb 04 02:46:38 PM PST 24
Finished	Feb 04 02:46:49 PM PST 24
Peak memory	218708 kb
Host	smart-7b9e3e89-a46e-435c-aed4-4df83332da6d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745660169 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.kmac_test_vectors_kmac.1745660169 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_kmac_xof.353810565
Short name	T1092
Test name
Test status
Simulation time	155636559 ps
CPU time	6.14 seconds
Started	Feb 04 02:46:37 PM PST 24
Finished	Feb 04 02:46:48 PM PST 24
Peak memory	218824 kb
Host	smart-d12ea568-d6ef-40a7-a872-c26c5c380e7f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353810565 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 17.kmac_test_vectors_kmac_xof.353810565 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_224.849993930
Short name	T846
Test name
Test status
Simulation time	41599502429 ps
CPU time	1843.31 seconds
Started	Feb 04 02:46:36 PM PST 24
Finished	Feb 04 03:17:25 PM PST 24
Peak memory	388376 kb
Host	smart-92e783a9-eafd-40b3-8cf8-daaf0b2ec0c4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=849993930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.849993930 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_256.816517120
Short name	T442
Test name
Test status
Simulation time	19786470766 ps
CPU time	2134.6 seconds
Started	Feb 04 02:46:36 PM PST 24
Finished	Feb 04 03:22:16 PM PST 24
Peak memory	388380 kb
Host	smart-aeb81022-29b6-4801-8005-d75f2305510e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=816517120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.816517120 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_384.595273962
Short name	T528
Test name
Test status
Simulation time	18339079256 ps
CPU time	1459.98 seconds
Started	Feb 04 02:46:42 PM PST 24
Finished	Feb 04 03:11:04 PM PST 24
Peak memory	346088 kb
Host	smart-bac78b4d-b15d-46b7-8a36-f49814358dd5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=595273962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.595273962 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_512.356728388
Short name	T529
Test name
Test status
Simulation time	478310896437 ps
CPU time	1297.18 seconds
Started	Feb 04 02:46:33 PM PST 24
Finished	Feb 04 03:08:18 PM PST 24
Peak memory	303680 kb
Host	smart-733ac4c8-6c1c-4356-9a0a-a1597e40e9b2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=356728388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.356728388 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_shake_128.2655537290
Short name	T927
Test name
Test status
Simulation time	1117006006742 ps
CPU time	6755.69 seconds
Started	Feb 04 02:46:37 PM PST 24
Finished	Feb 04 04:39:18 PM PST 24
Peak memory	648644 kb
Host	smart-db37e38c-642f-4e89-b0f0-3112ad006f37
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2655537290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.2655537290 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_shake_256.3862337849
Short name	T879
Test name
Test status
Simulation time	110412819415 ps
CPU time	4765.19 seconds
Started	Feb 04 02:46:38 PM PST 24
Finished	Feb 04 04:06:07 PM PST 24
Peak memory	569228 kb
Host	smart-c0c8dd75-1ff1-4bec-9f36-d3d620b064c7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3862337849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.3862337849 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/18.kmac_alert_test.1746139621
Short name	T1003
Test name
Test status
Simulation time	33685923 ps
CPU time	0.86 seconds
Started	Feb 04 02:47:21 PM PST 24
Finished	Feb 04 02:47:26 PM PST 24
Peak memory	218284 kb
Host	smart-7bb0fff6-bd6b-4ba3-bb09-2c09d56374e7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746139621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.1746139621 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_alert_test/latest

Test location	/workspace/coverage/default/18.kmac_app.1001580872
Short name	T883
Test name
Test status
Simulation time	3931120482 ps
CPU time	35.94 seconds
Started	Feb 04 02:46:46 PM PST 24
Finished	Feb 04 02:47:23 PM PST 24
Peak memory	227584 kb
Host	smart-a10e1d42-c213-4b54-9549-6e512f80dcae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1001580872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.1001580872 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_app/latest

Test location	/workspace/coverage/default/18.kmac_burst_write.880757127
Short name	T1077
Test name
Test status
Simulation time	47316743617 ps
CPU time	459.92 seconds
Started	Feb 04 02:46:49 PM PST 24
Finished	Feb 04 02:54:30 PM PST 24
Peak memory	235604 kb
Host	smart-b56b9e79-943d-4ed4-95ff-1ad5dd9fe071
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=880757127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.880757127 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_burst_write/latest

Test location	/workspace/coverage/default/18.kmac_edn_timeout_error.993454423
Short name	T339
Test name
Test status
Simulation time	7775600152 ps
CPU time	50.83 seconds
Started	Feb 04 02:47:19 PM PST 24
Finished	Feb 04 02:48:12 PM PST 24
Peak memory	238692 kb
Host	smart-942b8d41-f980-4588-9137-60744ea75f5f
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=993454423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.993454423 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/18.kmac_entropy_mode_error.2413360040
Short name	T1044
Test name
Test status
Simulation time	1094376023 ps
CPU time	40.64 seconds
Started	Feb 04 02:47:28 PM PST 24
Finished	Feb 04 02:48:10 PM PST 24
Peak memory	243204 kb
Host	smart-73f6fa88-4873-4a91-badb-9f4dbdc48f04
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2413360040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.2413360040 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/18.kmac_entropy_refresh.3281123257
Short name	T1038
Test name
Test status
Simulation time	6122394938 ps
CPU time	230.23 seconds
Started	Feb 04 02:46:46 PM PST 24
Finished	Feb 04 02:50:37 PM PST 24
Peak memory	245132 kb
Host	smart-a5763172-8a09-4401-9d0f-069b07d945f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3281123257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.3281123257 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/18.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/18.kmac_error.2895938420
Short name	T750
Test name
Test status
Simulation time	3813866842 ps
CPU time	334.97 seconds
Started	Feb 04 02:46:45 PM PST 24
Finished	Feb 04 02:52:21 PM PST 24
Peak memory	259968 kb
Host	smart-41dc437f-9df5-44fd-828c-f62d81e53ac9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2895938420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.2895938420 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_error/latest

Test location	/workspace/coverage/default/18.kmac_key_error.114664119
Short name	T1066
Test name
Test status
Simulation time	1091356154 ps
CPU time	3.17 seconds
Started	Feb 04 02:46:49 PM PST 24
Finished	Feb 04 02:46:54 PM PST 24
Peak memory	218620 kb
Host	smart-a86d474e-f616-4ef7-88ee-938a73db63e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=114664119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.114664119 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_key_error/latest

Test location	/workspace/coverage/default/18.kmac_lc_escalation.4188456190
Short name	T934
Test name
Test status
Simulation time	119338310 ps
CPU time	1.47 seconds
Started	Feb 04 02:47:24 PM PST 24
Finished	Feb 04 02:47:27 PM PST 24
Peak memory	219728 kb
Host	smart-d7b2427b-5586-4700-b5f2-0d09a862caa8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4188456190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.4188456190 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/18.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/18.kmac_long_msg_and_output.2735419892
Short name	T983
Test name
Test status
Simulation time	39758749987 ps
CPU time	559.96 seconds
Started	Feb 04 02:46:49 PM PST 24
Finished	Feb 04 02:56:10 PM PST 24
Peak memory	275252 kb
Host	smart-b2de7a0f-3880-4290-95c4-1d7edf9d21ab
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735419892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a nd_output.2735419892 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/18.kmac_sideload.3031268480
Short name	T228
Test name
Test status
Simulation time	3426175621 ps
CPU time	106.98 seconds
Started	Feb 04 02:46:51 PM PST 24
Finished	Feb 04 02:48:38 PM PST 24
Peak memory	243336 kb
Host	smart-a267ea78-070f-4c84-8574-e6ac8c38cb7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3031268480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.3031268480 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_sideload/latest

Test location	/workspace/coverage/default/18.kmac_smoke.3646513159
Short name	T1091
Test name
Test status
Simulation time	7760572334 ps
CPU time	79.07 seconds
Started	Feb 04 02:46:47 PM PST 24
Finished	Feb 04 02:48:07 PM PST 24
Peak memory	224548 kb
Host	smart-5494483f-ea35-4722-a4d4-784623052c1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3646513159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.3646513159 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_smoke/latest

Test location	/workspace/coverage/default/18.kmac_stress_all.2956010819
Short name	T627
Test name
Test status
Simulation time	222430547357 ps
CPU time	1265.59 seconds
Started	Feb 04 02:47:11 PM PST 24
Finished	Feb 04 03:08:18 PM PST 24
Peak memory	358016 kb
Host	smart-0588a812-4ad3-409e-bdc2-fd25919b1476
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2956010819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.2956010819 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_stress_all/latest

Test location	/workspace/coverage/default/18.kmac_stress_all_with_rand_reset.4248343568
Short name	T310
Test name
Test status
Simulation time	63001169640 ps
CPU time	259.78 seconds
Started	Feb 04 02:47:18 PM PST 24
Finished	Feb 04 02:51:40 PM PST 24
Peak memory	258872 kb
Host	smart-8e9dbd29-fae0-43e2-9346-3fca1614d1f0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4248343568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all_with_rand_reset.4248343568 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_kmac.924368700
Short name	T1006
Test name
Test status
Simulation time	274597026 ps
CPU time	6.96 seconds
Started	Feb 04 02:46:48 PM PST 24
Finished	Feb 04 02:46:56 PM PST 24
Peak memory	218724 kb
Host	smart-65eb0da8-7326-4697-b128-e0120190776f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924368700 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 18.kmac_test_vectors_kmac.924368700 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_kmac_xof.1256129030
Short name	T855
Test name
Test status
Simulation time	361439293 ps
CPU time	6.39 seconds
Started	Feb 04 02:46:49 PM PST 24
Finished	Feb 04 02:46:56 PM PST 24
Peak memory	218720 kb
Host	smart-3c3a45f6-2d48-48e1-9f9d-db1a5fc39144
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256129030 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_kmac_xof.1256129030 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_224.2730777396
Short name	T166
Test name
Test status
Simulation time	131796357782 ps
CPU time	2272.4 seconds
Started	Feb 04 02:46:46 PM PST 24
Finished	Feb 04 03:24:39 PM PST 24
Peak memory	391616 kb
Host	smart-eb3edce3-6f15-49f0-b1dd-b395b15c2624
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2730777396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.2730777396 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_256.3836900911
Short name	T479
Test name
Test status
Simulation time	61500893495 ps
CPU time	2253.51 seconds
Started	Feb 04 02:46:48 PM PST 24
Finished	Feb 04 03:24:22 PM PST 24
Peak memory	380892 kb
Host	smart-b5806655-56f1-47da-8c69-a82ef17f2ad3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3836900911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.3836900911 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_384.1822717262
Short name	T429
Test name
Test status
Simulation time	29526260325 ps
CPU time	1773.56 seconds
Started	Feb 04 02:46:50 PM PST 24
Finished	Feb 04 03:16:25 PM PST 24
Peak memory	340880 kb
Host	smart-3eeb32dd-db43-4558-b5df-babee62e132c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1822717262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.1822717262 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_512.1563412283
Short name	T1067
Test name
Test status
Simulation time	79023754383 ps
CPU time	1449.12 seconds
Started	Feb 04 02:46:48 PM PST 24
Finished	Feb 04 03:10:58 PM PST 24
Peak memory	306216 kb
Host	smart-493a0a69-c254-42fd-94f1-0f44ed1ae004
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1563412283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.1563412283 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_shake_128.2056461609
Short name	T666
Test name
Test status
Simulation time	363976987529 ps
CPU time	6000.71 seconds
Started	Feb 04 02:46:46 PM PST 24
Finished	Feb 04 04:26:49 PM PST 24
Peak memory	656980 kb
Host	smart-8eecec7a-8cb5-41b0-aa29-0dd5c0f2727f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2056461609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.2056461609 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_shake_256.606926225
Short name	T956
Test name
Test status
Simulation time	403194406026 ps
CPU time	4885.05 seconds
Started	Feb 04 02:46:47 PM PST 24
Finished	Feb 04 04:08:14 PM PST 24
Peak memory	568704 kb
Host	smart-b30cce83-c082-456e-853d-8296a4b7ea32
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=606926225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.606926225 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/19.kmac_alert_test.4146815285
Short name	T244
Test name
Test status
Simulation time	19381048 ps
CPU time	0.85 seconds
Started	Feb 04 02:47:26 PM PST 24
Finished	Feb 04 02:47:28 PM PST 24
Peak memory	218372 kb
Host	smart-98393d4a-9a61-4470-a0e3-b836f40679c7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146815285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.4146815285 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_alert_test/latest

Test location	/workspace/coverage/default/19.kmac_app.1131572289
Short name	T619
Test name
Test status
Simulation time	1430434778 ps
CPU time	24.7 seconds
Started	Feb 04 02:47:18 PM PST 24
Finished	Feb 04 02:47:45 PM PST 24
Peak memory	226864 kb
Host	smart-910a4cf2-7268-43fb-84b7-dcc054fa8ff2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1131572289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.1131572289 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_app/latest

Test location	/workspace/coverage/default/19.kmac_burst_write.746273829
Short name	T472
Test name
Test status
Simulation time	13342033547 ps
CPU time	1259.47 seconds
Started	Feb 04 02:47:19 PM PST 24
Finished	Feb 04 03:08:20 PM PST 24
Peak memory	239768 kb
Host	smart-030dd4c2-4992-4d48-8b68-113c74e944fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=746273829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.746273829 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_burst_write/latest

Test location	/workspace/coverage/default/19.kmac_edn_timeout_error.4000194208
Short name	T289
Test name
Test status
Simulation time	3002890594 ps
CPU time	28.11 seconds
Started	Feb 04 02:47:10 PM PST 24
Finished	Feb 04 02:47:38 PM PST 24
Peak memory	234820 kb
Host	smart-a1a29158-a73f-4327-b9e1-623a2786c632
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4000194208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.4000194208 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/19.kmac_entropy_mode_error.1142092031
Short name	T684
Test name
Test status
Simulation time	15899546 ps
CPU time	0.83 seconds
Started	Feb 04 02:47:19 PM PST 24
Finished	Feb 04 02:47:21 PM PST 24
Peak memory	218444 kb
Host	smart-a2dcbbb8-2fb3-4619-acd8-e75b0a93356d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1142092031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.1142092031 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/19.kmac_entropy_refresh.2778242087
Short name	T849
Test name
Test status
Simulation time	12407423527 ps
CPU time	197.59 seconds
Started	Feb 04 02:47:13 PM PST 24
Finished	Feb 04 02:50:31 PM PST 24
Peak memory	240700 kb
Host	smart-2b4a388b-a760-4503-a692-70a3f933b901
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2778242087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.2778242087 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/19.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/19.kmac_error.3763882172
Short name	T44
Test name
Test status
Simulation time	82394752299 ps
CPU time	482.88 seconds
Started	Feb 04 02:47:14 PM PST 24
Finished	Feb 04 02:55:18 PM PST 24
Peak memory	267972 kb
Host	smart-3a4a0fd4-11b4-4516-ac03-3e57a5dbebb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3763882172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.3763882172 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_error/latest

Test location	/workspace/coverage/default/19.kmac_key_error.2369424578
Short name	T210
Test name
Test status
Simulation time	166673318 ps
CPU time	1.54 seconds
Started	Feb 04 02:47:10 PM PST 24
Finished	Feb 04 02:47:12 PM PST 24
Peak memory	218560 kb
Host	smart-e7a90241-4966-4abd-b8af-ccf6b3322022
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2369424578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.2369424578 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_key_error/latest

Test location	/workspace/coverage/default/19.kmac_lc_escalation.681982945
Short name	T941
Test name
Test status
Simulation time	2079054311 ps
CPU time	22.3 seconds
Started	Feb 04 02:47:21 PM PST 24
Finished	Feb 04 02:47:47 PM PST 24
Peak memory	235392 kb
Host	smart-727be9c2-cc5e-4325-a4bd-b69b9a0b0d60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=681982945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.681982945 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/19.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/19.kmac_long_msg_and_output.1607154902
Short name	T218
Test name
Test status
Simulation time	5223174974 ps
CPU time	119.93 seconds
Started	Feb 04 02:47:24 PM PST 24
Finished	Feb 04 02:49:26 PM PST 24
Peak memory	230760 kb
Host	smart-f59fe408-4658-45c4-bded-40b6dfe804ae
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607154902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a nd_output.1607154902 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/19.kmac_sideload.2411559658
Short name	T1052
Test name
Test status
Simulation time	81352050853 ps
CPU time	454.32 seconds
Started	Feb 04 02:47:19 PM PST 24
Finished	Feb 04 02:54:56 PM PST 24
Peak memory	253632 kb
Host	smart-dda0f4d0-d001-44fe-975a-c132c1dd2a0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2411559658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.2411559658 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_sideload/latest

Test location	/workspace/coverage/default/19.kmac_smoke.3279399804
Short name	T271
Test name
Test status
Simulation time	2227163297 ps
CPU time	32.21 seconds
Started	Feb 04 02:47:23 PM PST 24
Finished	Feb 04 02:47:58 PM PST 24
Peak memory	227036 kb
Host	smart-519b5ecb-36ea-4578-9c90-a141fb8a4450
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3279399804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.3279399804 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_smoke/latest

Test location	/workspace/coverage/default/19.kmac_stress_all.434113438
Short name	T733
Test name
Test status
Simulation time	31968115287 ps
CPU time	241.32 seconds
Started	Feb 04 02:47:19 PM PST 24
Finished	Feb 04 02:51:22 PM PST 24
Peak memory	260644 kb
Host	smart-f8ad4778-caa8-4645-81dc-990a2a858bef
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=434113438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.434113438 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_stress_all/latest

Test location	/workspace/coverage/default/19.kmac_stress_all_with_rand_reset.1284499492
Short name	T247
Test name
Test status
Simulation time	13560595535 ps
CPU time	418.46 seconds
Started	Feb 04 02:47:11 PM PST 24
Finished	Feb 04 02:54:10 PM PST 24
Peak memory	284492 kb
Host	smart-62c0e512-86e4-4c21-a523-929a04506227
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1284499492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all_with_rand_reset.1284499492 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_kmac.4128613167
Short name	T727
Test name
Test status
Simulation time	452076298 ps
CPU time	6.21 seconds
Started	Feb 04 02:47:16 PM PST 24
Finished	Feb 04 02:47:24 PM PST 24
Peak memory	220212 kb
Host	smart-92fe4304-55ee-4a14-8722-c2ab1ae43135
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128613167 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.kmac_test_vectors_kmac.4128613167 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_kmac_xof.2248930071
Short name	T170
Test name
Test status
Simulation time	896803255 ps
CPU time	6.7 seconds
Started	Feb 04 02:47:21 PM PST 24
Finished	Feb 04 02:47:32 PM PST 24
Peak memory	220092 kb
Host	smart-44fb60a6-1c37-4034-bc92-82b19c5cfb29
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248930071 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_kmac_xof.2248930071 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_224.3946867714
Short name	T864
Test name
Test status
Simulation time	205204183895 ps
CPU time	2614.12 seconds
Started	Feb 04 02:47:14 PM PST 24
Finished	Feb 04 03:30:50 PM PST 24
Peak memory	403868 kb
Host	smart-dc9e4507-2804-4c33-b28c-6edf95d7938a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3946867714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.3946867714 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_256.1136671682
Short name	T407
Test name
Test status
Simulation time	95826321807 ps
CPU time	2326.99 seconds
Started	Feb 04 02:47:11 PM PST 24
Finished	Feb 04 03:25:59 PM PST 24
Peak memory	382156 kb
Host	smart-2b183c51-af99-4c37-a4ac-69435a5eacb5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1136671682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.1136671682 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_384.3124962052
Short name	T730
Test name
Test status
Simulation time	14939691869 ps
CPU time	1592.92 seconds
Started	Feb 04 02:47:20 PM PST 24
Finished	Feb 04 03:13:57 PM PST 24
Peak memory	343372 kb
Host	smart-68408142-ed96-4b1e-86ea-2d0245a75f77
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3124962052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.3124962052 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_512.2294932857
Short name	T316
Test name
Test status
Simulation time	11079363990 ps
CPU time	1058.75 seconds
Started	Feb 04 02:47:16 PM PST 24
Finished	Feb 04 03:04:56 PM PST 24
Peak memory	300032 kb
Host	smart-eb6677d1-721d-422f-a346-4259e5c93487
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2294932857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.2294932857 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_shake_128.2348379992
Short name	T236
Test name
Test status
Simulation time	353090487403 ps
CPU time	6115.89 seconds
Started	Feb 04 02:47:16 PM PST 24
Finished	Feb 04 04:29:15 PM PST 24
Peak memory	656492 kb
Host	smart-5eef0d7d-cb94-4118-8cc2-3f1f4876a547
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2348379992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.2348379992 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_shake_256.2667172325
Short name	T655
Test name
Test status
Simulation time	373991395697 ps
CPU time	5029.9 seconds
Started	Feb 04 02:47:21 PM PST 24
Finished	Feb 04 04:11:15 PM PST 24
Peak memory	558472 kb
Host	smart-2109fe50-d179-4f56-b028-fab02d66e8fe
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2667172325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.2667172325 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/2.kmac_alert_test.2846212393
Short name	T230
Test name
Test status
Simulation time	32580257 ps
CPU time	0.8 seconds
Started	Feb 04 02:44:59 PM PST 24
Finished	Feb 04 02:45:23 PM PST 24
Peak memory	219352 kb
Host	smart-777ff16a-6261-4276-925d-881f10d9399d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846212393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.2846212393 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_alert_test/latest

Test location	/workspace/coverage/default/2.kmac_app.4277924126
Short name	T977
Test name
Test status
Simulation time	5997737773 ps
CPU time	161.45 seconds
Started	Feb 04 02:44:54 PM PST 24
Finished	Feb 04 02:47:57 PM PST 24
Peak memory	239436 kb
Host	smart-95ae297a-1777-40cf-a6ca-6c1ba115c478
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4277924126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.4277924126 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_app/latest

Test location	/workspace/coverage/default/2.kmac_app_with_partial_data.1396600223
Short name	T697
Test name
Test status
Simulation time	106323996652 ps
CPU time	320.21 seconds
Started	Feb 04 02:44:50 PM PST 24
Finished	Feb 04 02:50:35 PM PST 24
Peak memory	246368 kb
Host	smart-d91fb771-c0b0-49c7-a963-2d8c9617db69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1396600223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.1396600223 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/2.kmac_burst_write.3411162113
Short name	T598
Test name
Test status
Simulation time	6039177089 ps
CPU time	73.51 seconds
Started	Feb 04 02:44:59 PM PST 24
Finished	Feb 04 02:46:36 PM PST 24
Peak memory	235156 kb
Host	smart-aa529d45-c5a1-4272-a042-f936aca7784b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3411162113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.3411162113 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_burst_write/latest

Test location	/workspace/coverage/default/2.kmac_edn_timeout_error.1232175490
Short name	T969
Test name
Test status
Simulation time	3335633189 ps
CPU time	27.78 seconds
Started	Feb 04 02:44:54 PM PST 24
Finished	Feb 04 02:45:43 PM PST 24
Peak memory	226088 kb
Host	smart-25d0c935-49f3-4684-b36e-9c9ce2b7b4aa
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1232175490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.1232175490 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/2.kmac_entropy_mode_error.1534016376
Short name	T516
Test name
Test status
Simulation time	300638100 ps
CPU time	1.02 seconds
Started	Feb 04 02:44:48 PM PST 24
Finished	Feb 04 02:45:08 PM PST 24
Peak memory	218680 kb
Host	smart-31fa9ac8-93eb-41d1-a313-a36ffe5463ab
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1534016376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.1534016376 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/2.kmac_entropy_ready_error.3521367650
Short name	T679
Test name
Test status
Simulation time	3599815754 ps
CPU time	40.58 seconds
Started	Feb 04 02:44:52 PM PST 24
Finished	Feb 04 02:45:55 PM PST 24
Peak memory	219204 kb
Host	smart-4bac5da8-7c6a-48a5-a75c-89cf00953075
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3521367650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.3521367650 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/2.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/2.kmac_entropy_refresh.4205804591
Short name	T74
Test name
Test status
Simulation time	32112914660 ps
CPU time	181.86 seconds
Started	Feb 04 02:44:59 PM PST 24
Finished	Feb 04 02:48:24 PM PST 24
Peak memory	243668 kb
Host	smart-8bd003f0-ed7f-4fbe-a0a8-01d27c7caf66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4205804591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.4205804591 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/2.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/2.kmac_error.3624864036
Short name	T816
Test name
Test status
Simulation time	607056451 ps
CPU time	26.53 seconds
Started	Feb 04 02:44:55 PM PST 24
Finished	Feb 04 02:45:43 PM PST 24
Peak memory	242824 kb
Host	smart-54974471-2ded-4b56-9ecb-23441e25e17e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3624864036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.3624864036 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_error/latest

Test location	/workspace/coverage/default/2.kmac_key_error.3839528402
Short name	T276
Test name
Test status
Simulation time	7278819811 ps
CPU time	5.93 seconds
Started	Feb 04 02:44:47 PM PST 24
Finished	Feb 04 02:45:08 PM PST 24
Peak memory	218600 kb
Host	smart-ba37399f-a0c7-458f-8be9-d3f5c895efe2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3839528402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.3839528402 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_key_error/latest

Test location	/workspace/coverage/default/2.kmac_lc_escalation.2666696245
Short name	T791
Test name
Test status
Simulation time	546930032 ps
CPU time	25.92 seconds
Started	Feb 04 02:44:54 PM PST 24
Finished	Feb 04 02:45:41 PM PST 24
Peak memory	235904 kb
Host	smart-ea262bd8-6db2-4f7b-a648-8fa420518c34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2666696245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.2666696245 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/2.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/2.kmac_long_msg_and_output.828042259
Short name	T491
Test name
Test status
Simulation time	53413813558 ps
CPU time	3042.37 seconds
Started	Feb 04 02:44:51 PM PST 24
Finished	Feb 04 03:35:58 PM PST 24
Peak memory	479772 kb
Host	smart-7272e0be-b166-4a47-b9c8-7e1d382ea929
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828042259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and _output.828042259 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/2.kmac_mubi.2181931975
Short name	T393
Test name
Test status
Simulation time	9502631692 ps
CPU time	192.21 seconds
Started	Feb 04 02:44:54 PM PST 24
Finished	Feb 04 02:48:27 PM PST 24
Peak memory	241728 kb
Host	smart-c176a4f6-54df-4eae-9e67-70339b637d36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2181931975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.2181931975 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_mubi/latest

Test location	/workspace/coverage/default/2.kmac_sec_cm.993847389
Short name	T106
Test name
Test status
Simulation time	13879276294 ps
CPU time	118.31 seconds
Started	Feb 04 02:44:51 PM PST 24
Finished	Feb 04 02:47:13 PM PST 24
Peak memory	317840 kb
Host	smart-27dd68e5-53bc-4242-9e3d-cce01a52b518
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993847389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.993847389 +enable_masking =1 +sw_key_masked=0
Directory	/workspace/2.kmac_sec_cm/latest

Test location	/workspace/coverage/default/2.kmac_sideload.3006038274
Short name	T712
Test name
Test status
Simulation time	72119708055 ps
CPU time	401.32 seconds
Started	Feb 04 02:44:55 PM PST 24
Finished	Feb 04 02:51:58 PM PST 24
Peak memory	251824 kb
Host	smart-bacaaba3-c2a0-4e49-b657-d93f9bb069f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3006038274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.3006038274 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_sideload/latest

Test location	/workspace/coverage/default/2.kmac_smoke.3081543424
Short name	T495
Test name
Test status
Simulation time	269127615 ps
CPU time	12.07 seconds
Started	Feb 04 02:44:55 PM PST 24
Finished	Feb 04 02:45:29 PM PST 24
Peak memory	224064 kb
Host	smart-0e2a3fc7-f3c7-42f2-aa07-9a68e2213145
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3081543424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.3081543424 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_smoke/latest

Test location	/workspace/coverage/default/2.kmac_stress_all.749854223
Short name	T931
Test name
Test status
Simulation time	356072586740 ps
CPU time	1160.09 seconds
Started	Feb 04 02:44:54 PM PST 24
Finished	Feb 04 03:04:36 PM PST 24
Peak memory	325680 kb
Host	smart-c790c168-3d57-480f-83eb-0b48cfa5aee0
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=749854223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.749854223 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_stress_all/latest

Test location	/workspace/coverage/default/2.kmac_stress_all_with_rand_reset.296340092
Short name	T609
Test name
Test status
Simulation time	735326635126 ps
CPU time	1167.54 seconds
Started	Feb 04 02:44:54 PM PST 24
Finished	Feb 04 03:04:44 PM PST 24
Peak memory	309036 kb
Host	smart-a13c1aae-9240-4d4d-99a8-ca31a8d66b18
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=296340092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_with_rand_reset.296340092 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_kmac.2888399016
Short name	T628
Test name
Test status
Simulation time	139902305 ps
CPU time	6.14 seconds
Started	Feb 04 02:44:52 PM PST 24
Finished	Feb 04 02:45:21 PM PST 24
Peak memory	218828 kb
Host	smart-b6e4b22e-9cf8-46b7-a775-e2289caa0ae4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888399016 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.kmac_test_vectors_kmac.2888399016 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_kmac_xof.4055312912
Short name	T709
Test name
Test status
Simulation time	831513144 ps
CPU time	5.98 seconds
Started	Feb 04 02:44:54 PM PST 24
Finished	Feb 04 02:45:21 PM PST 24
Peak memory	220316 kb
Host	smart-a802a27f-fd63-4954-ad4f-640476bbf4bb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055312912 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.4055312912 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_224.4187858568
Short name	T795
Test name
Test status
Simulation time	40116220367 ps
CPU time	2081.81 seconds
Started	Feb 04 02:44:51 PM PST 24
Finished	Feb 04 03:19:57 PM PST 24
Peak memory	388076 kb
Host	smart-1a84e303-7759-4380-bfc2-7bfae3de14ca
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4187858568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.4187858568 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_256.167215001
Short name	T547
Test name
Test status
Simulation time	380638668688 ps
CPU time	2296.24 seconds
Started	Feb 04 02:44:52 PM PST 24
Finished	Feb 04 03:23:31 PM PST 24
Peak memory	389384 kb
Host	smart-e12b37ae-1942-4ad6-90d8-7815e7fe51d7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=167215001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.167215001 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_384.3673392036
Short name	T954
Test name
Test status
Simulation time	192493845075 ps
CPU time	1700.04 seconds
Started	Feb 04 02:44:51 PM PST 24
Finished	Feb 04 03:13:35 PM PST 24
Peak memory	345904 kb
Host	smart-a7a8f212-21da-450e-b22d-71491b66cf13
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3673392036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.3673392036 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_512.1952211454
Short name	T500
Test name
Test status
Simulation time	11337875348 ps
CPU time	1224.13 seconds
Started	Feb 04 02:44:50 PM PST 24
Finished	Feb 04 03:05:35 PM PST 24
Peak memory	303508 kb
Host	smart-315cf33b-c74b-44d2-8cbe-ae1c66413b30
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1952211454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.1952211454 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_shake_128.3227460510
Short name	T662
Test name
Test status
Simulation time	133130833688 ps
CPU time	5392.51 seconds
Started	Feb 04 02:44:50 PM PST 24
Finished	Feb 04 04:15:08 PM PST 24
Peak memory	668544 kb
Host	smart-8869fbb1-f726-4301-bd5e-30f1b2d8be8d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3227460510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.3227460510 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_shake_256.456909617
Short name	T501
Test name
Test status
Simulation time	155748472603 ps
CPU time	5026.09 seconds
Started	Feb 04 02:44:54 PM PST 24
Finished	Feb 04 04:09:03 PM PST 24
Peak memory	567644 kb
Host	smart-d25360ee-f21e-4306-adcb-da41b32a8554
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=456909617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.456909617 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/20.kmac_alert_test.4288660613
Short name	T1109
Test name
Test status
Simulation time	33985264 ps
CPU time	0.79 seconds
Started	Feb 04 02:47:17 PM PST 24
Finished	Feb 04 02:47:19 PM PST 24
Peak memory	219512 kb
Host	smart-de6e5549-fd73-4ed8-bb29-561deb7eee92
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288660613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.4288660613 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_alert_test/latest

Test location	/workspace/coverage/default/20.kmac_app.455117907
Short name	T826
Test name
Test status
Simulation time	51223608092 ps
CPU time	458.98 seconds
Started	Feb 04 02:47:19 PM PST 24
Finished	Feb 04 02:55:00 PM PST 24
Peak memory	253944 kb
Host	smart-5e972f87-b9ed-4821-8cac-27d90fa0853f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=455117907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.455117907 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_app/latest

Test location	/workspace/coverage/default/20.kmac_burst_write.2915431664
Short name	T988
Test name
Test status
Simulation time	10833440273 ps
CPU time	1153.68 seconds
Started	Feb 04 02:47:19 PM PST 24
Finished	Feb 04 03:06:34 PM PST 24
Peak memory	243472 kb
Host	smart-d88bb9dd-b10e-4bf5-881c-4dc8faa14c06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2915431664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.2915431664 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_burst_write/latest

Test location	/workspace/coverage/default/20.kmac_entropy_refresh.4055571484
Short name	T823
Test name
Test status
Simulation time	12860389896 ps
CPU time	168.14 seconds
Started	Feb 04 02:47:28 PM PST 24
Finished	Feb 04 02:50:17 PM PST 24
Peak memory	240504 kb
Host	smart-f07fe206-e4ea-44c2-80f2-66aa01416ada
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4055571484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.4055571484 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/20.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/20.kmac_error.840145262
Short name	T72
Test name
Test status
Simulation time	1909721415 ps
CPU time	54.23 seconds
Started	Feb 04 02:47:16 PM PST 24
Finished	Feb 04 02:48:12 PM PST 24
Peak memory	243340 kb
Host	smart-fdd1cd91-f125-4e5a-b330-9e8918f6802f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=840145262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.840145262 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_error/latest

Test location	/workspace/coverage/default/20.kmac_key_error.3567546468
Short name	T834
Test name
Test status
Simulation time	93245569 ps
CPU time	1.08 seconds
Started	Feb 04 02:47:27 PM PST 24
Finished	Feb 04 02:47:29 PM PST 24
Peak memory	218404 kb
Host	smart-1a1c2c54-75c8-4b9c-be6e-b7ce2ed2b9f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3567546468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.3567546468 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_key_error/latest

Test location	/workspace/coverage/default/20.kmac_lc_escalation.3200800378
Short name	T423
Test name
Test status
Simulation time	1785649158 ps
CPU time	21.6 seconds
Started	Feb 04 02:47:21 PM PST 24
Finished	Feb 04 02:47:46 PM PST 24
Peak memory	235376 kb
Host	smart-b2590cb9-b447-4aa4-bccf-42859ed20be9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3200800378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.3200800378 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/20.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/20.kmac_long_msg_and_output.3000041165
Short name	T717
Test name
Test status
Simulation time	26142306933 ps
CPU time	544.88 seconds
Started	Feb 04 02:47:16 PM PST 24
Finished	Feb 04 02:56:22 PM PST 24
Peak memory	271316 kb
Host	smart-82c184ac-1cb7-4680-bdaa-1edd33fd16b2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000041165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a nd_output.3000041165 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/20.kmac_sideload.1085765487
Short name	T280
Test name
Test status
Simulation time	18075185454 ps
CPU time	343.05 seconds
Started	Feb 04 02:47:19 PM PST 24
Finished	Feb 04 02:53:05 PM PST 24
Peak memory	249936 kb
Host	smart-f98fc715-8b21-4df3-80ad-64e481db17db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1085765487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.1085765487 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_sideload/latest

Test location	/workspace/coverage/default/20.kmac_smoke.3655232103
Short name	T980
Test name
Test status
Simulation time	3025304741 ps
CPU time	20.92 seconds
Started	Feb 04 02:47:19 PM PST 24
Finished	Feb 04 02:47:42 PM PST 24
Peak memory	227032 kb
Host	smart-5295e6c0-7813-4695-b791-09bf971bc9fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3655232103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.3655232103 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_smoke/latest

Test location	/workspace/coverage/default/20.kmac_stress_all.2554645447
Short name	T452
Test name
Test status
Simulation time	26239902979 ps
CPU time	1244.88 seconds
Started	Feb 04 02:47:29 PM PST 24
Finished	Feb 04 03:08:17 PM PST 24
Peak memory	330208 kb
Host	smart-1afa19ad-1a9b-4395-95e9-6831b6c32df2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2554645447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.2554645447 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_stress_all/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_kmac.207335628
Short name	T800
Test name
Test status
Simulation time	218196307 ps
CPU time	6.43 seconds
Started	Feb 04 02:47:24 PM PST 24
Finished	Feb 04 02:47:32 PM PST 24
Peak memory	220300 kb
Host	smart-fb608a45-cc78-4d2e-b5a8-2dd77a515995
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207335628 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 20.kmac_test_vectors_kmac.207335628 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_kmac_xof.3714321577
Short name	T420
Test name
Test status
Simulation time	304919203 ps
CPU time	6.99 seconds
Started	Feb 04 02:47:23 PM PST 24
Finished	Feb 04 02:47:32 PM PST 24
Peak memory	220348 kb
Host	smart-5371686b-c5fc-485f-8028-fb1f601dd008
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714321577 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_kmac_xof.3714321577 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_224.4063446341
Short name	T865
Test name
Test status
Simulation time	104048478571 ps
CPU time	2605.22 seconds
Started	Feb 04 02:47:27 PM PST 24
Finished	Feb 04 03:30:54 PM PST 24
Peak memory	404648 kb
Host	smart-c8faf0de-2528-4775-9774-c3cf2818c5f7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4063446341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.4063446341 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_256.2684989479
Short name	T650
Test name
Test status
Simulation time	43793637955 ps
CPU time	2052.75 seconds
Started	Feb 04 02:47:22 PM PST 24
Finished	Feb 04 03:21:38 PM PST 24
Peak memory	386216 kb
Host	smart-cda75872-b538-4936-8001-38506581cb59
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2684989479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.2684989479 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_384.226423621
Short name	T358
Test name
Test status
Simulation time	99579837119 ps
CPU time	1844.54 seconds
Started	Feb 04 02:47:26 PM PST 24
Finished	Feb 04 03:18:12 PM PST 24
Peak memory	342644 kb
Host	smart-b5a57071-6504-4722-8e05-347f187ba077
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=226423621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.226423621 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_512.162178761
Short name	T428
Test name
Test status
Simulation time	11452116433 ps
CPU time	1263.15 seconds
Started	Feb 04 02:47:18 PM PST 24
Finished	Feb 04 03:08:24 PM PST 24
Peak memory	302784 kb
Host	smart-02a3b17c-d2f5-4242-a9ad-7a8c67922549
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=162178761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.162178761 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_shake_128.401028508
Short name	T1113
Test name
Test status
Simulation time	228759674059 ps
CPU time	6143.58 seconds
Started	Feb 04 02:47:25 PM PST 24
Finished	Feb 04 04:29:51 PM PST 24
Peak memory	652556 kb
Host	smart-5377ea4b-82dc-4a26-8865-2f2dd7dbb1c1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=401028508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.401028508 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_shake_256.426687466
Short name	T201
Test name
Test status
Simulation time	298534928193 ps
CPU time	5014.79 seconds
Started	Feb 04 02:47:19 PM PST 24
Finished	Feb 04 04:10:56 PM PST 24
Peak memory	572972 kb
Host	smart-30e643f7-5620-431f-82f6-8bf618ccfc4a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=426687466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.426687466 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/21.kmac_alert_test.3533496686
Short name	T562
Test name
Test status
Simulation time	146588237 ps
CPU time	0.92 seconds
Started	Feb 04 02:47:17 PM PST 24
Finished	Feb 04 02:47:20 PM PST 24
Peak memory	219512 kb
Host	smart-97321bab-7b8f-4d45-bdbc-cd727dd8d6b2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533496686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.3533496686 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_alert_test/latest

Test location	/workspace/coverage/default/21.kmac_app.672573561
Short name	T473
Test name
Test status
Simulation time	18761595942 ps
CPU time	304.9 seconds
Started	Feb 04 02:47:32 PM PST 24
Finished	Feb 04 02:52:41 PM PST 24
Peak memory	250292 kb
Host	smart-3f9944d2-a8ab-4e56-9cc5-57a1719580a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=672573561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.672573561 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_app/latest

Test location	/workspace/coverage/default/21.kmac_burst_write.1473936662
Short name	T682
Test name
Test status
Simulation time	5317760594 ps
CPU time	151.53 seconds
Started	Feb 04 02:47:32 PM PST 24
Finished	Feb 04 02:50:07 PM PST 24
Peak memory	228512 kb
Host	smart-c143aad6-2484-4f17-9c4c-82816516d088
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1473936662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.1473936662 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_burst_write/latest

Test location	/workspace/coverage/default/21.kmac_entropy_refresh.3009123090
Short name	T997
Test name
Test status
Simulation time	29815799855 ps
CPU time	368.16 seconds
Started	Feb 04 02:47:20 PM PST 24
Finished	Feb 04 02:53:32 PM PST 24
Peak memory	250568 kb
Host	smart-6acac50a-6ff9-4a34-9e66-427ab6c799ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3009123090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.3009123090 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/21.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/21.kmac_error.3603919077
Short name	T1094
Test name
Test status
Simulation time	74015571469 ps
CPU time	385.91 seconds
Started	Feb 04 02:47:18 PM PST 24
Finished	Feb 04 02:53:46 PM PST 24
Peak memory	262952 kb
Host	smart-9159eb32-53bd-4c66-826e-325f8c1285e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3603919077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.3603919077 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_error/latest

Test location	/workspace/coverage/default/21.kmac_key_error.426843347
Short name	T1028
Test name
Test status
Simulation time	1566932699 ps
CPU time	5.46 seconds
Started	Feb 04 02:47:26 PM PST 24
Finished	Feb 04 02:47:33 PM PST 24
Peak memory	218700 kb
Host	smart-faa97270-9159-4994-91bc-66dc220a9087
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=426843347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.426843347 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_key_error/latest

Test location	/workspace/coverage/default/21.kmac_lc_escalation.2768116143
Short name	T1099
Test name
Test status
Simulation time	86861517 ps
CPU time	1.47 seconds
Started	Feb 04 02:47:29 PM PST 24
Finished	Feb 04 02:47:34 PM PST 24
Peak memory	219964 kb
Host	smart-c3641a68-0aab-4204-9276-93debd6fe01d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2768116143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.2768116143 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/21.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/21.kmac_long_msg_and_output.500799335
Short name	T601
Test name
Test status
Simulation time	14212149488 ps
CPU time	1370.08 seconds
Started	Feb 04 02:47:18 PM PST 24
Finished	Feb 04 03:10:10 PM PST 24
Peak memory	351540 kb
Host	smart-c8419e4f-2c4d-4754-8f6c-e78c28b7f105
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500799335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_an d_output.500799335 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/21.kmac_sideload.1148877342
Short name	T794
Test name
Test status
Simulation time	2914951299 ps
CPU time	281.71 seconds
Started	Feb 04 02:47:17 PM PST 24
Finished	Feb 04 02:52:01 PM PST 24
Peak memory	244532 kb
Host	smart-675c3435-2cc6-4533-8dcb-32360e806914
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1148877342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.1148877342 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_sideload/latest

Test location	/workspace/coverage/default/21.kmac_smoke.819006228
Short name	T212
Test name
Test status
Simulation time	10894263022 ps
CPU time	63.14 seconds
Started	Feb 04 02:47:25 PM PST 24
Finished	Feb 04 02:48:29 PM PST 24
Peak memory	224152 kb
Host	smart-24ca8c38-1844-4445-9b5a-e265f4080c2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=819006228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.819006228 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_smoke/latest

Test location	/workspace/coverage/default/21.kmac_stress_all.714529529
Short name	T331
Test name
Test status
Simulation time	52436209217 ps
CPU time	947.06 seconds
Started	Feb 04 02:47:27 PM PST 24
Finished	Feb 04 03:03:15 PM PST 24
Peak memory	324720 kb
Host	smart-5fac84b8-c63d-4710-9f0b-bc05608ec4bf
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=714529529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.714529529 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_stress_all/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_kmac.625800483
Short name	T265
Test name
Test status
Simulation time	718932307 ps
CPU time	5.57 seconds
Started	Feb 04 02:47:28 PM PST 24
Finished	Feb 04 02:47:35 PM PST 24
Peak memory	220432 kb
Host	smart-ae4eeaad-949f-45ad-8198-bdf6cf37eedc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625800483 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 21.kmac_test_vectors_kmac.625800483 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_kmac_xof.1371626999
Short name	T729
Test name
Test status
Simulation time	389369291 ps
CPU time	6.27 seconds
Started	Feb 04 02:47:18 PM PST 24
Finished	Feb 04 02:47:27 PM PST 24
Peak memory	220044 kb
Host	smart-809809b6-0d7c-4a41-ae79-b8e17ce29d1e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371626999 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_kmac_xof.1371626999 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_224.3555320525
Short name	T260
Test name
Test status
Simulation time	495184717362 ps
CPU time	2396.84 seconds
Started	Feb 04 02:47:26 PM PST 24
Finished	Feb 04 03:27:24 PM PST 24
Peak memory	391960 kb
Host	smart-98960696-78b0-4cb1-8328-6b6cf5aa0f96
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3555320525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.3555320525 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_256.2329010938
Short name	T190
Test name
Test status
Simulation time	242928404393 ps
CPU time	1949.06 seconds
Started	Feb 04 02:47:26 PM PST 24
Finished	Feb 04 03:19:57 PM PST 24
Peak memory	382284 kb
Host	smart-eb872389-5c2e-4e22-8a29-8e34d57c65a2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2329010938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.2329010938 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_384.2443608614
Short name	T799
Test name
Test status
Simulation time	53424989425 ps
CPU time	1639.58 seconds
Started	Feb 04 02:47:27 PM PST 24
Finished	Feb 04 03:14:48 PM PST 24
Peak memory	337356 kb
Host	smart-730139d6-38de-4176-9ed1-fbb5096bb62c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2443608614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.2443608614 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_512.4143898412
Short name	T402
Test name
Test status
Simulation time	262787969053 ps
CPU time	1481.93 seconds
Started	Feb 04 02:47:19 PM PST 24
Finished	Feb 04 03:12:03 PM PST 24
Peak memory	304784 kb
Host	smart-39008bd0-744f-4537-9b3c-1e9c82d7c6a3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4143898412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.4143898412 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_shake_128.3960259422
Short name	T394
Test name
Test status
Simulation time	59862928584 ps
CPU time	5811.41 seconds
Started	Feb 04 02:47:19 PM PST 24
Finished	Feb 04 04:24:14 PM PST 24
Peak memory	655800 kb
Host	smart-88b1ed9f-8849-4b7a-aef6-4380ca5f28a5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3960259422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.3960259422 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_shake_256.864312934
Short name	T607
Test name
Test status
Simulation time	54607231333 ps
CPU time	4786.63 seconds
Started	Feb 04 02:47:18 PM PST 24
Finished	Feb 04 04:07:07 PM PST 24
Peak memory	577196 kb
Host	smart-47c3401c-5826-4a2d-9f19-ea1937e3a039
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=864312934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.864312934 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/22.kmac_alert_test.3695212150
Short name	T98
Test name
Test status
Simulation time	19866940 ps
CPU time	0.89 seconds
Started	Feb 04 02:47:41 PM PST 24
Finished	Feb 04 02:47:43 PM PST 24
Peak memory	218380 kb
Host	smart-81058c68-d841-47b9-bb36-65baf1392edd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695212150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.3695212150 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_alert_test/latest

Test location	/workspace/coverage/default/22.kmac_app.3610322621
Short name	T899
Test name
Test status
Simulation time	7018202664 ps
CPU time	103.84 seconds
Started	Feb 04 02:47:35 PM PST 24
Finished	Feb 04 02:49:24 PM PST 24
Peak memory	234908 kb
Host	smart-0b3da680-0c7d-4a07-9807-6288f4eae8b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3610322621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.3610322621 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_app/latest

Test location	/workspace/coverage/default/22.kmac_burst_write.355631337
Short name	T689
Test name
Test status
Simulation time	24162275359 ps
CPU time	680.86 seconds
Started	Feb 04 02:47:31 PM PST 24
Finished	Feb 04 02:58:56 PM PST 24
Peak memory	243436 kb
Host	smart-732be5cc-7e44-4ce1-aefd-263bf169e7f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=355631337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.355631337 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_burst_write/latest

Test location	/workspace/coverage/default/22.kmac_entropy_refresh.4293576530
Short name	T571
Test name
Test status
Simulation time	2826828085 ps
CPU time	55.66 seconds
Started	Feb 04 02:47:38 PM PST 24
Finished	Feb 04 02:48:38 PM PST 24
Peak memory	230100 kb
Host	smart-ca1234a4-8375-49d1-8635-3a00779e7dae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4293576530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.4293576530 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/22.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/22.kmac_error.1233703676
Short name	T1112
Test name
Test status
Simulation time	1641177858 ps
CPU time	53.54 seconds
Started	Feb 04 02:47:40 PM PST 24
Finished	Feb 04 02:48:36 PM PST 24
Peak memory	243272 kb
Host	smart-9b6c6ac7-184e-4f44-8377-ab9c906148d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1233703676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.1233703676 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_error/latest

Test location	/workspace/coverage/default/22.kmac_key_error.2302426126
Short name	T901
Test name
Test status
Simulation time	812435319 ps
CPU time	2.39 seconds
Started	Feb 04 02:47:41 PM PST 24
Finished	Feb 04 02:47:45 PM PST 24
Peak memory	218640 kb
Host	smart-ae84215b-e87f-42d3-9f57-6efd08cb8924
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2302426126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.2302426126 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_key_error/latest

Test location	/workspace/coverage/default/22.kmac_lc_escalation.2993377458
Short name	T1080
Test name
Test status
Simulation time	44608947 ps
CPU time	1.41 seconds
Started	Feb 04 02:47:33 PM PST 24
Finished	Feb 04 02:47:38 PM PST 24
Peak memory	219784 kb
Host	smart-cd6563ef-525c-4d49-8e4e-7addf3c3b28e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2993377458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.2993377458 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/22.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/22.kmac_long_msg_and_output.2087289346
Short name	T5
Test name
Test status
Simulation time	15545186494 ps
CPU time	1115.56 seconds
Started	Feb 04 02:47:28 PM PST 24
Finished	Feb 04 03:06:05 PM PST 24
Peak memory	318556 kb
Host	smart-bc3c8f4c-efff-4fb4-b424-221336c64daf
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087289346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a nd_output.2087289346 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/22.kmac_sideload.3422169995
Short name	T468
Test name
Test status
Simulation time	26181457584 ps
CPU time	401.33 seconds
Started	Feb 04 02:47:31 PM PST 24
Finished	Feb 04 02:54:17 PM PST 24
Peak memory	251176 kb
Host	smart-bd72d4c6-8ca3-40d8-9f3e-dc2b625250e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3422169995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.3422169995 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_sideload/latest

Test location	/workspace/coverage/default/22.kmac_smoke.2870724439
Short name	T828
Test name
Test status
Simulation time	5307287759 ps
CPU time	81.35 seconds
Started	Feb 04 02:47:20 PM PST 24
Finished	Feb 04 02:48:45 PM PST 24
Peak memory	224152 kb
Host	smart-bf5dc267-b738-402d-a423-4659e65da6a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2870724439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.2870724439 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_smoke/latest

Test location	/workspace/coverage/default/22.kmac_stress_all.830486276
Short name	T370
Test name
Test status
Simulation time	21148999458 ps
CPU time	1927.01 seconds
Started	Feb 04 02:47:30 PM PST 24
Finished	Feb 04 03:19:41 PM PST 24
Peak memory	352668 kb
Host	smart-838e4383-2f97-4300-9072-6c7de3afb4aa
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=830486276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.830486276 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_stress_all/latest

Test location	/workspace/coverage/default/22.kmac_stress_all_with_rand_reset.872271933
Short name	T914
Test name
Test status
Simulation time	268339568768 ps
CPU time	5490.21 seconds
Started	Feb 04 02:47:39 PM PST 24
Finished	Feb 04 04:19:13 PM PST 24
Peak memory	498528 kb
Host	smart-a0a5f72b-be22-4b42-80b7-785c2a1e1a68
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=872271933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all_with_rand_reset.872271933 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_kmac.1748428245
Short name	T274
Test name
Test status
Simulation time	437709789 ps
CPU time	5.52 seconds
Started	Feb 04 02:47:41 PM PST 24
Finished	Feb 04 02:47:48 PM PST 24
Peak memory	220220 kb
Host	smart-d5ad2e9d-ea9b-41c7-a860-6efc42a6d16a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748428245 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 22.kmac_test_vectors_kmac.1748428245 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_kmac_xof.2038310663
Short name	T278
Test name
Test status
Simulation time	190352822 ps
CPU time	6.44 seconds
Started	Feb 04 02:47:33 PM PST 24
Finished	Feb 04 02:47:43 PM PST 24
Peak memory	220124 kb
Host	smart-c0a72f09-a87e-45cf-8f52-ee849e0a4fff
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038310663 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_kmac_xof.2038310663 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_224.535894578
Short name	T321
Test name
Test status
Simulation time	20633822815 ps
CPU time	1903.44 seconds
Started	Feb 04 02:47:28 PM PST 24
Finished	Feb 04 03:19:13 PM PST 24
Peak memory	393052 kb
Host	smart-5f1fc005-6f50-430a-94c7-7a85155b241a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=535894578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.535894578 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_256.3661313221
Short name	T539
Test name
Test status
Simulation time	112643103318 ps
CPU time	2076.46 seconds
Started	Feb 04 02:47:36 PM PST 24
Finished	Feb 04 03:22:17 PM PST 24
Peak memory	387344 kb
Host	smart-9306aab5-8257-4be4-8d3d-f3259ae9a825
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3661313221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.3661313221 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_384.1269809982
Short name	T775
Test name
Test status
Simulation time	70915930393 ps
CPU time	1915.94 seconds
Started	Feb 04 02:47:33 PM PST 24
Finished	Feb 04 03:19:32 PM PST 24
Peak memory	341272 kb
Host	smart-1d510d24-9b9a-40f6-8421-0dc16060ec5a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1269809982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.1269809982 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_512.3938875397
Short name	T874
Test name
Test status
Simulation time	21999301085 ps
CPU time	1102.6 seconds
Started	Feb 04 02:47:29 PM PST 24
Finished	Feb 04 03:05:55 PM PST 24
Peak memory	303040 kb
Host	smart-1ff2a0aa-056c-4321-a2ac-cb5010188679
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3938875397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.3938875397 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_shake_128.966156737
Short name	T611
Test name
Test status
Simulation time	426451269600 ps
CPU time	5212.6 seconds
Started	Feb 04 02:47:40 PM PST 24
Finished	Feb 04 04:14:36 PM PST 24
Peak memory	642100 kb
Host	smart-21bef023-06d1-4450-b596-d4eed2b2659a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=966156737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.966156737 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_shake_256.3956569355
Short name	T745
Test name
Test status
Simulation time	106955626514 ps
CPU time	4667.1 seconds
Started	Feb 04 02:47:37 PM PST 24
Finished	Feb 04 04:05:30 PM PST 24
Peak memory	574480 kb
Host	smart-3107c497-7d50-4cf5-a266-f6d026af01f3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3956569355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.3956569355 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/23.kmac_alert_test.2080143261
Short name	T456
Test name
Test status
Simulation time	38117148 ps
CPU time	0.81 seconds
Started	Feb 04 02:47:50 PM PST 24
Finished	Feb 04 02:47:57 PM PST 24
Peak memory	218268 kb
Host	smart-2382fbae-a1f9-464e-9679-9ee28b4827a9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080143261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.2080143261 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_alert_test/latest

Test location	/workspace/coverage/default/23.kmac_app.3974883439
Short name	T439
Test name
Test status
Simulation time	15461527795 ps
CPU time	332.96 seconds
Started	Feb 04 02:47:49 PM PST 24
Finished	Feb 04 02:53:23 PM PST 24
Peak memory	251864 kb
Host	smart-97c37785-4846-4b35-a744-afb89cc02ec6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3974883439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.3974883439 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_app/latest

Test location	/workspace/coverage/default/23.kmac_burst_write.618328007
Short name	T514
Test name
Test status
Simulation time	88386770245 ps
CPU time	804.37 seconds
Started	Feb 04 02:47:31 PM PST 24
Finished	Feb 04 03:01:00 PM PST 24
Peak memory	237528 kb
Host	smart-9b90cf4b-1bfb-445b-9674-9608a2d33182
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=618328007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.618328007 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_burst_write/latest

Test location	/workspace/coverage/default/23.kmac_entropy_refresh.1127132094
Short name	T34
Test name
Test status
Simulation time	7274328675 ps
CPU time	155.94 seconds
Started	Feb 04 02:47:47 PM PST 24
Finished	Feb 04 02:50:25 PM PST 24
Peak memory	237672 kb
Host	smart-6ecf5837-5240-4293-bbcd-a612ede72ff0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1127132094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.1127132094 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/23.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/23.kmac_error.3708384485
Short name	T135
Test name
Test status
Simulation time	2688575146 ps
CPU time	231.13 seconds
Started	Feb 04 02:48:07 PM PST 24
Finished	Feb 04 02:51:59 PM PST 24
Peak memory	259552 kb
Host	smart-35583d11-8f4a-4607-9f05-416b8277028a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3708384485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.3708384485 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_error/latest

Test location	/workspace/coverage/default/23.kmac_key_error.1527052923
Short name	T756
Test name
Test status
Simulation time	578976608 ps
CPU time	3.59 seconds
Started	Feb 04 02:47:49 PM PST 24
Finished	Feb 04 02:47:54 PM PST 24
Peak memory	218480 kb
Host	smart-c1a5b3ef-6de6-48a4-93bb-31952397febd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1527052923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.1527052923 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_key_error/latest

Test location	/workspace/coverage/default/23.kmac_lc_escalation.3915083799
Short name	T404
Test name
Test status
Simulation time	44383786 ps
CPU time	1.3 seconds
Started	Feb 04 02:47:45 PM PST 24
Finished	Feb 04 02:47:48 PM PST 24
Peak memory	219732 kb
Host	smart-57700792-4e12-4e72-849c-daeaa6b0ad82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3915083799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.3915083799 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/23.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/23.kmac_long_msg_and_output.2098261861
Short name	T762
Test name
Test status
Simulation time	9067990495 ps
CPU time	165.93 seconds
Started	Feb 04 02:47:35 PM PST 24
Finished	Feb 04 02:50:27 PM PST 24
Peak memory	236004 kb
Host	smart-9e43fa53-2bcb-4f53-b133-71a5fc1248d0
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098261861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a nd_output.2098261861 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/23.kmac_sideload.3104218172
Short name	T398
Test name
Test status
Simulation time	18235822812 ps
CPU time	418.28 seconds
Started	Feb 04 02:47:32 PM PST 24
Finished	Feb 04 02:54:34 PM PST 24
Peak memory	253004 kb
Host	smart-69992390-024f-485d-aa6b-d309195acec0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3104218172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.3104218172 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_sideload/latest

Test location	/workspace/coverage/default/23.kmac_smoke.2105213037
Short name	T720
Test name
Test status
Simulation time	1148382528 ps
CPU time	15.63 seconds
Started	Feb 04 02:47:29 PM PST 24
Finished	Feb 04 02:47:48 PM PST 24
Peak memory	227056 kb
Host	smart-c2064015-3c3c-4ac0-8c0c-fa04fb5f1411
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2105213037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.2105213037 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_smoke/latest

Test location	/workspace/coverage/default/23.kmac_stress_all.3142926680
Short name	T1033
Test name
Test status
Simulation time	48636591334 ps
CPU time	1507.99 seconds
Started	Feb 04 02:48:07 PM PST 24
Finished	Feb 04 03:13:16 PM PST 24
Peak memory	373468 kb
Host	smart-41474111-c846-4019-816d-d2ed84fafd6e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3142926680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.3142926680 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_stress_all/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_kmac.1666311340
Short name	T949
Test name
Test status
Simulation time	397550296 ps
CPU time	6.82 seconds
Started	Feb 04 02:47:38 PM PST 24
Finished	Feb 04 02:47:49 PM PST 24
Peak memory	218880 kb
Host	smart-592152f0-3a0d-4bbe-8c3f-5f2719eab7a8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666311340 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 23.kmac_test_vectors_kmac.1666311340 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_kmac_xof.1026624522
Short name	T913
Test name
Test status
Simulation time	796105902 ps
CPU time	5.95 seconds
Started	Feb 04 02:47:46 PM PST 24
Finished	Feb 04 02:47:54 PM PST 24
Peak memory	218804 kb
Host	smart-0c7e2812-ec0c-4ca4-9c67-8a5726401c25
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026624522 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_kmac_xof.1026624522 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_224.4283532747
Short name	T557
Test name
Test status
Simulation time	82641368192 ps
CPU time	2297.96 seconds
Started	Feb 04 02:47:30 PM PST 24
Finished	Feb 04 03:25:52 PM PST 24
Peak memory	390200 kb
Host	smart-e142dbf4-7592-443d-aa34-136a9c9bce47
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4283532747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.4283532747 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_256.1530297207
Short name	T564
Test name
Test status
Simulation time	37262412262 ps
CPU time	2156.53 seconds
Started	Feb 04 02:47:30 PM PST 24
Finished	Feb 04 03:23:32 PM PST 24
Peak memory	380644 kb
Host	smart-0627a918-3d4a-43f3-82c2-c28972ea89fe
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1530297207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.1530297207 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_384.3419002244
Short name	T1049
Test name
Test status
Simulation time	14770993428 ps
CPU time	1733.7 seconds
Started	Feb 04 02:47:29 PM PST 24
Finished	Feb 04 03:16:26 PM PST 24
Peak memory	335112 kb
Host	smart-9d400b8e-9ef3-418e-8ac6-972da16a1124
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3419002244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.3419002244 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_512.1146353012
Short name	T767
Test name
Test status
Simulation time	10488078492 ps
CPU time	1442.14 seconds
Started	Feb 04 02:47:41 PM PST 24
Finished	Feb 04 03:11:45 PM PST 24
Peak memory	299316 kb
Host	smart-04d66509-4ca5-45a7-b11f-8ad842154e49
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1146353012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.1146353012 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_shake_128.3657419002
Short name	T87
Test name
Test status
Simulation time	249482288426 ps
CPU time	5664.93 seconds
Started	Feb 04 02:47:40 PM PST 24
Finished	Feb 04 04:22:08 PM PST 24
Peak memory	650160 kb
Host	smart-46acc86b-8f56-455b-986d-d7afbaf0fce3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3657419002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.3657419002 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_shake_256.858761576
Short name	T355
Test name
Test status
Simulation time	158069203347 ps
CPU time	5240.39 seconds
Started	Feb 04 02:47:38 PM PST 24
Finished	Feb 04 04:15:03 PM PST 24
Peak memory	581908 kb
Host	smart-a100a9ae-5cfd-4a17-9c01-d78d84f5b513
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=858761576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.858761576 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/24.kmac_alert_test.4091230195
Short name	T189
Test name
Test status
Simulation time	26363194 ps
CPU time	0.9 seconds
Started	Feb 04 02:47:58 PM PST 24
Finished	Feb 04 02:48:00 PM PST 24
Peak memory	218156 kb
Host	smart-98fc4abb-5e08-45c5-93a0-3aadecffd438
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091230195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.4091230195 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_alert_test/latest

Test location	/workspace/coverage/default/24.kmac_app.1425831528
Short name	T856
Test name
Test status
Simulation time	371271940 ps
CPU time	29.47 seconds
Started	Feb 04 02:48:07 PM PST 24
Finished	Feb 04 02:48:38 PM PST 24
Peak memory	227728 kb
Host	smart-8dd7d6d2-0368-4dd1-951e-a55553e494ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1425831528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.1425831528 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_app/latest

Test location	/workspace/coverage/default/24.kmac_burst_write.4144603323
Short name	T403
Test name
Test status
Simulation time	28626727785 ps
CPU time	1159.9 seconds
Started	Feb 04 02:47:50 PM PST 24
Finished	Feb 04 03:07:17 PM PST 24
Peak memory	241508 kb
Host	smart-b08e4ffa-b9ed-43e1-9263-1668082537a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4144603323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.4144603323 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_burst_write/latest

Test location	/workspace/coverage/default/24.kmac_entropy_refresh.343133659
Short name	T577
Test name
Test status
Simulation time	28747304301 ps
CPU time	303.85 seconds
Started	Feb 04 02:47:49 PM PST 24
Finished	Feb 04 02:52:54 PM PST 24
Peak memory	250052 kb
Host	smart-b0644217-60e5-442b-ad32-5906a6ce7371
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=343133659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.343133659 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/24.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/24.kmac_error.1007163940
Short name	T267
Test name
Test status
Simulation time	5872471773 ps
CPU time	248.94 seconds
Started	Feb 04 02:48:07 PM PST 24
Finished	Feb 04 02:52:17 PM PST 24
Peak memory	255520 kb
Host	smart-3bdf13d3-668c-4d61-b0fb-3431341f5ab5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1007163940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.1007163940 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_error/latest

Test location	/workspace/coverage/default/24.kmac_key_error.3598064950
Short name	T105
Test name
Test status
Simulation time	572788307 ps
CPU time	1.86 seconds
Started	Feb 04 02:48:00 PM PST 24
Finished	Feb 04 02:48:03 PM PST 24
Peak memory	218544 kb
Host	smart-6b687df7-5ff5-4ba9-8b62-d8a0fe91c90a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3598064950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.3598064950 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_key_error/latest

Test location	/workspace/coverage/default/24.kmac_lc_escalation.592161146
Short name	T346
Test name
Test status
Simulation time	104176918 ps
CPU time	1.38 seconds
Started	Feb 04 02:47:56 PM PST 24
Finished	Feb 04 02:48:00 PM PST 24
Peak memory	219792 kb
Host	smart-85fc1b4f-f162-47eb-ae40-caf7a2a949a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=592161146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.592161146 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/24.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/24.kmac_long_msg_and_output.3915017529
Short name	T351
Test name
Test status
Simulation time	11206126785 ps
CPU time	388.64 seconds
Started	Feb 04 02:47:45 PM PST 24
Finished	Feb 04 02:54:15 PM PST 24
Peak memory	253920 kb
Host	smart-6633120a-9a80-4a5b-9336-d1ab4282a109
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915017529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a nd_output.3915017529 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/24.kmac_sideload.836001039
Short name	T165
Test name
Test status
Simulation time	6782900576 ps
CPU time	93.78 seconds
Started	Feb 04 02:48:07 PM PST 24
Finished	Feb 04 02:49:42 PM PST 24
Peak memory	240068 kb
Host	smart-8ae7d22f-59f0-401d-a715-fc68ede343c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=836001039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.836001039 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_sideload/latest

Test location	/workspace/coverage/default/24.kmac_smoke.113768608
Short name	T416
Test name
Test status
Simulation time	1442815969 ps
CPU time	53.28 seconds
Started	Feb 04 02:47:49 PM PST 24
Finished	Feb 04 02:48:44 PM PST 24
Peak memory	224436 kb
Host	smart-3bd46486-3b0f-4e22-a349-0ae819a4a78d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113768608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.113768608 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_smoke/latest

Test location	/workspace/coverage/default/24.kmac_stress_all.2496229195
Short name	T18
Test name
Test status
Simulation time	25526644553 ps
CPU time	434.43 seconds
Started	Feb 04 02:47:56 PM PST 24
Finished	Feb 04 02:55:13 PM PST 24
Peak memory	297536 kb
Host	smart-79a9dbef-634b-429f-a816-5826cc309e54
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2496229195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.2496229195 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_stress_all/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_kmac.2228670889
Short name	T776
Test name
Test status
Simulation time	407448890 ps
CPU time	6.74 seconds
Started	Feb 04 02:48:07 PM PST 24
Finished	Feb 04 02:48:15 PM PST 24
Peak memory	218876 kb
Host	smart-9ad0e0b2-92b0-4263-8669-c616f5ef15c7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228670889 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 24.kmac_test_vectors_kmac.2228670889 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_kmac_xof.1713980881
Short name	T963
Test name
Test status
Simulation time	372205301 ps
CPU time	5.68 seconds
Started	Feb 04 02:47:46 PM PST 24
Finished	Feb 04 02:47:54 PM PST 24
Peak memory	220244 kb
Host	smart-b0c47de7-5c0b-4b95-a5b8-8e37ef31f089
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713980881 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_kmac_xof.1713980881 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_224.897531744
Short name	T1081
Test name
Test status
Simulation time	344880503747 ps
CPU time	2385.23 seconds
Started	Feb 04 02:47:49 PM PST 24
Finished	Feb 04 03:27:36 PM PST 24
Peak memory	392172 kb
Host	smart-9543f1f6-b752-4a0b-9ea0-bf80661371be
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=897531744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.897531744 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_256.1854791751
Short name	T237
Test name
Test status
Simulation time	19487844831 ps
CPU time	1998.9 seconds
Started	Feb 04 02:48:07 PM PST 24
Finished	Feb 04 03:21:27 PM PST 24
Peak memory	391964 kb
Host	smart-075dd078-cf37-43dd-9934-42d00abde163
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1854791751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.1854791751 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_384.673468273
Short name	T1059
Test name
Test status
Simulation time	30719612266 ps
CPU time	1755.71 seconds
Started	Feb 04 02:47:48 PM PST 24
Finished	Feb 04 03:17:06 PM PST 24
Peak memory	342776 kb
Host	smart-b4f767a0-58e6-48d6-b557-80f18b419d09
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=673468273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.673468273 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_512.2123633777
Short name	T1096
Test name
Test status
Simulation time	33950078209 ps
CPU time	1190.98 seconds
Started	Feb 04 02:47:52 PM PST 24
Finished	Feb 04 03:07:49 PM PST 24
Peak memory	302388 kb
Host	smart-77284846-99cf-413c-a7ca-deb19c837d94
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2123633777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.2123633777 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_shake_128.3465660301
Short name	T881
Test name
Test status
Simulation time	63417000573 ps
CPU time	5082.68 seconds
Started	Feb 04 02:48:07 PM PST 24
Finished	Feb 04 04:12:52 PM PST 24
Peak memory	652400 kb
Host	smart-853b42b0-c343-4c95-95b3-e15c2e2ec9f3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3465660301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.3465660301 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_shake_256.2623644730
Short name	T604
Test name
Test status
Simulation time	161754294317 ps
CPU time	5548.32 seconds
Started	Feb 04 02:48:07 PM PST 24
Finished	Feb 04 04:20:37 PM PST 24
Peak memory	569396 kb
Host	smart-010f00b6-7ea4-48b3-9a43-0a14a09463a2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2623644730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.2623644730 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/25.kmac_alert_test.1852230763
Short name	T181
Test name
Test status
Simulation time	53705810 ps
CPU time	0.87 seconds
Started	Feb 04 02:48:22 PM PST 24
Finished	Feb 04 02:48:24 PM PST 24
Peak memory	219408 kb
Host	smart-1d1d4f10-0e33-48c3-acbc-3ed7303b229f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852230763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.1852230763 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_alert_test/latest

Test location	/workspace/coverage/default/25.kmac_app.2408401979
Short name	T698
Test name
Test status
Simulation time	13025556557 ps
CPU time	199.22 seconds
Started	Feb 04 02:48:16 PM PST 24
Finished	Feb 04 02:51:36 PM PST 24
Peak memory	244232 kb
Host	smart-6a6baf9a-45a5-40a6-abd8-9d3577ef15e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2408401979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.2408401979 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_app/latest

Test location	/workspace/coverage/default/25.kmac_burst_write.2093812348
Short name	T1134
Test name
Test status
Simulation time	16847762066 ps
CPU time	631.36 seconds
Started	Feb 04 02:48:04 PM PST 24
Finished	Feb 04 02:58:36 PM PST 24
Peak memory	243472 kb
Host	smart-8320a9d7-4e60-41e2-a31d-8b197b2490b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2093812348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.2093812348 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_burst_write/latest

Test location	/workspace/coverage/default/25.kmac_entropy_refresh.386777071
Short name	T1102
Test name
Test status
Simulation time	10235724246 ps
CPU time	67.94 seconds
Started	Feb 04 02:48:21 PM PST 24
Finished	Feb 04 02:49:31 PM PST 24
Peak memory	229792 kb
Host	smart-0a7c5cff-0019-4a96-8d7b-b326568afab1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=386777071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.386777071 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/25.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/25.kmac_error.2742930952
Short name	T732
Test name
Test status
Simulation time	8783299351 ps
CPU time	147.8 seconds
Started	Feb 04 02:48:24 PM PST 24
Finished	Feb 04 02:50:53 PM PST 24
Peak memory	255324 kb
Host	smart-e3aa29e4-0a29-4773-b4dd-0dfbdf55515a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2742930952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.2742930952 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_error/latest

Test location	/workspace/coverage/default/25.kmac_key_error.541805018
Short name	T241
Test name
Test status
Simulation time	751470165 ps
CPU time	2.08 seconds
Started	Feb 04 02:48:25 PM PST 24
Finished	Feb 04 02:48:28 PM PST 24
Peak memory	218652 kb
Host	smart-47c68deb-36fe-44ec-9f60-53b8f077f350
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=541805018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.541805018 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_key_error/latest

Test location	/workspace/coverage/default/25.kmac_lc_escalation.3344547474
Short name	T622
Test name
Test status
Simulation time	165113280 ps
CPU time	1.25 seconds
Started	Feb 04 02:48:25 PM PST 24
Finished	Feb 04 02:48:28 PM PST 24
Peak memory	219772 kb
Host	smart-dac3b58a-df21-4ff0-8297-a7737c41c0ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3344547474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.3344547474 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/25.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/25.kmac_long_msg_and_output.3341592082
Short name	T509
Test name
Test status
Simulation time	40597025805 ps
CPU time	947.98 seconds
Started	Feb 04 02:48:04 PM PST 24
Finished	Feb 04 03:03:53 PM PST 24
Peak memory	292264 kb
Host	smart-8fc91f8a-fcad-4b2d-8ba7-c41d5d5070be
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341592082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a nd_output.3341592082 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/25.kmac_smoke.132740386
Short name	T301
Test name
Test status
Simulation time	1746006189 ps
CPU time	11.07 seconds
Started	Feb 04 02:47:56 PM PST 24
Finished	Feb 04 02:48:09 PM PST 24
Peak memory	218908 kb
Host	smart-b832a42a-cfbb-455b-8fb8-dd1c822f5375
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=132740386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.132740386 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_smoke/latest

Test location	/workspace/coverage/default/25.kmac_stress_all.248118045
Short name	T806
Test name
Test status
Simulation time	1920347439 ps
CPU time	43.91 seconds
Started	Feb 04 02:48:24 PM PST 24
Finished	Feb 04 02:49:09 PM PST 24
Peak memory	243644 kb
Host	smart-ea3fc1f8-6c3e-4cfc-a8da-38c6d03f7ea1
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=248118045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.248118045 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_stress_all/latest

Test location	/workspace/coverage/default/25.kmac_stress_all_with_rand_reset.425544243
Short name	T14
Test name
Test status
Simulation time	132036664081 ps
CPU time	778.16 seconds
Started	Feb 04 02:48:17 PM PST 24
Finished	Feb 04 03:01:22 PM PST 24
Peak memory	291668 kb
Host	smart-3086f80e-ccd8-4b69-b959-04411766851c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=425544243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all_with_rand_reset.425544243 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_kmac.3855382943
Short name	T347
Test name
Test status
Simulation time	112211214 ps
CPU time	6.75 seconds
Started	Feb 04 02:48:05 PM PST 24
Finished	Feb 04 02:48:12 PM PST 24
Peak memory	220352 kb
Host	smart-f07403f2-5c88-4c2c-b433-04ea67092937
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855382943 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 25.kmac_test_vectors_kmac.3855382943 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_kmac_xof.781989188
Short name	T187
Test name
Test status
Simulation time	120627184 ps
CPU time	6.33 seconds
Started	Feb 04 02:48:27 PM PST 24
Finished	Feb 04 02:48:34 PM PST 24
Peak memory	220256 kb
Host	smart-a7cc4025-8d06-4aa6-b6e1-797a6efad171
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781989188 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 25.kmac_test_vectors_kmac_xof.781989188 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_224.2338528261
Short name	T200
Test name
Test status
Simulation time	48060510843 ps
CPU time	1993.04 seconds
Started	Feb 04 02:48:04 PM PST 24
Finished	Feb 04 03:21:18 PM PST 24
Peak memory	393376 kb
Host	smart-629ea069-8c03-4da5-91fb-4b5dac43e0f9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2338528261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.2338528261 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_256.441669928
Short name	T962
Test name
Test status
Simulation time	20300426971 ps
CPU time	1987.53 seconds
Started	Feb 04 02:48:05 PM PST 24
Finished	Feb 04 03:21:14 PM PST 24
Peak memory	395552 kb
Host	smart-cc09248a-26f0-4ef9-b67a-58fda6544313
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=441669928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.441669928 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_384.4014645004
Short name	T250
Test name
Test status
Simulation time	15251122889 ps
CPU time	1350.48 seconds
Started	Feb 04 02:48:07 PM PST 24
Finished	Feb 04 03:10:39 PM PST 24
Peak memory	339160 kb
Host	smart-155a641b-127b-49d6-be11-e135cbe5c0d9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4014645004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.4014645004 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_512.1110756374
Short name	T989
Test name
Test status
Simulation time	14136513937 ps
CPU time	1384.65 seconds
Started	Feb 04 02:48:04 PM PST 24
Finished	Feb 04 03:11:10 PM PST 24
Peak memory	300224 kb
Host	smart-42bcddff-ba83-4e81-b1cd-2f3010b7c31a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1110756374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.1110756374 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_shake_128.3903402258
Short name	T1026
Test name
Test status
Simulation time	60720497839 ps
CPU time	5672.99 seconds
Started	Feb 04 02:48:06 PM PST 24
Finished	Feb 04 04:22:42 PM PST 24
Peak memory	665648 kb
Host	smart-f059b6ef-5257-4fdd-8155-f65546007fb5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3903402258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.3903402258 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_shake_256.3574816272
Short name	T396
Test name
Test status
Simulation time	241929244590 ps
CPU time	4787.56 seconds
Started	Feb 04 02:48:10 PM PST 24
Finished	Feb 04 04:08:00 PM PST 24
Peak memory	565328 kb
Host	smart-e7bb000f-73d4-4d27-8a79-0686bfa2cc73
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3574816272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.3574816272 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/26.kmac_alert_test.3580137939
Short name	T220
Test name
Test status
Simulation time	97073490 ps
CPU time	0.88 seconds
Started	Feb 04 02:48:37 PM PST 24
Finished	Feb 04 02:48:41 PM PST 24
Peak memory	219316 kb
Host	smart-fef3e283-593f-4771-8658-729fa970c75c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580137939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.3580137939 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_alert_test/latest

Test location	/workspace/coverage/default/26.kmac_app.4205236062
Short name	T992
Test name
Test status
Simulation time	2951125347 ps
CPU time	72.07 seconds
Started	Feb 04 02:48:33 PM PST 24
Finished	Feb 04 02:49:46 PM PST 24
Peak memory	232892 kb
Host	smart-1d4bd2ad-75b4-43d6-a683-f617d30cb01b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4205236062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.4205236062 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_app/latest

Test location	/workspace/coverage/default/26.kmac_burst_write.2132809043
Short name	T853
Test name
Test status
Simulation time	19568080885 ps
CPU time	481.96 seconds
Started	Feb 04 02:48:22 PM PST 24
Finished	Feb 04 02:56:26 PM PST 24
Peak memory	235436 kb
Host	smart-b9dfcc97-8f3d-49bb-890a-b64c7e2dfadd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2132809043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.2132809043 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_burst_write/latest

Test location	/workspace/coverage/default/26.kmac_entropy_refresh.1208373423
Short name	T869
Test name
Test status
Simulation time	4217497833 ps
CPU time	189.13 seconds
Started	Feb 04 02:48:32 PM PST 24
Finished	Feb 04 02:51:43 PM PST 24
Peak memory	241356 kb
Host	smart-b0aae194-b28a-4300-aecd-39bb0a5d9bb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1208373423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.1208373423 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/26.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/26.kmac_error.2440648875
Short name	T572
Test name
Test status
Simulation time	4926443871 ps
CPU time	155.32 seconds
Started	Feb 04 02:48:37 PM PST 24
Finished	Feb 04 02:51:14 PM PST 24
Peak memory	253376 kb
Host	smart-1c34fabe-7273-463e-88b0-202f92784ca5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2440648875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.2440648875 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_error/latest

Test location	/workspace/coverage/default/26.kmac_key_error.717476263
Short name	T595
Test name
Test status
Simulation time	3402059154 ps
CPU time	5.28 seconds
Started	Feb 04 02:48:36 PM PST 24
Finished	Feb 04 02:48:42 PM PST 24
Peak memory	218696 kb
Host	smart-d4c37d6f-3add-4de6-958a-b0dedb53ccac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=717476263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.717476263 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_key_error/latest

Test location	/workspace/coverage/default/26.kmac_lc_escalation.888109271
Short name	T542
Test name
Test status
Simulation time	143263139 ps
CPU time	1.44 seconds
Started	Feb 04 02:48:30 PM PST 24
Finished	Feb 04 02:48:32 PM PST 24
Peak memory	219756 kb
Host	smart-69861be0-3df6-40f1-aba3-3d3bdc8d2284
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=888109271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.888109271 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/26.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/26.kmac_long_msg_and_output.4201387009
Short name	T896
Test name
Test status
Simulation time	41807994677 ps
CPU time	2772.47 seconds
Started	Feb 04 02:48:25 PM PST 24
Finished	Feb 04 03:34:39 PM PST 24
Peak memory	447336 kb
Host	smart-b91e29f8-3494-4bbb-a866-759eb147cb7f
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201387009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a nd_output.4201387009 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/26.kmac_sideload.145121907
Short name	T386
Test name
Test status
Simulation time	956816511 ps
CPU time	29.96 seconds
Started	Feb 04 02:48:24 PM PST 24
Finished	Feb 04 02:48:56 PM PST 24
Peak memory	233840 kb
Host	smart-2dd6789b-53ad-44df-9844-4e6fdf4574b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=145121907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.145121907 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_sideload/latest

Test location	/workspace/coverage/default/26.kmac_smoke.3691761670
Short name	T302
Test name
Test status
Simulation time	6770265566 ps
CPU time	53.84 seconds
Started	Feb 04 02:48:16 PM PST 24
Finished	Feb 04 02:49:15 PM PST 24
Peak memory	227052 kb
Host	smart-b82a221f-43c7-4b88-80ac-662d8ad3e828
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3691761670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.3691761670 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_smoke/latest

Test location	/workspace/coverage/default/26.kmac_stress_all.1417932911
Short name	T995
Test name
Test status
Simulation time	384651966 ps
CPU time	10.65 seconds
Started	Feb 04 02:48:31 PM PST 24
Finished	Feb 04 02:48:43 PM PST 24
Peak memory	226964 kb
Host	smart-fc83fbca-b23a-4359-bea7-9fcbfb8b372c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1417932911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.1417932911 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_stress_all/latest

Test location	/workspace/coverage/default/26.kmac_stress_all_with_rand_reset.3024632242
Short name	T21
Test name
Test status
Simulation time	24159471472 ps
CPU time	347.06 seconds
Started	Feb 04 02:48:32 PM PST 24
Finished	Feb 04 02:54:20 PM PST 24
Peak memory	243828 kb
Host	smart-b58e345b-b7d1-42e9-9ddf-779d3815d82a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3024632242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all_with_rand_reset.3024632242 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_kmac.3734445006
Short name	T985
Test name
Test status
Simulation time	358029528 ps
CPU time	5.82 seconds
Started	Feb 04 02:48:32 PM PST 24
Finished	Feb 04 02:48:39 PM PST 24
Peak memory	218824 kb
Host	smart-05de6a04-d369-48b3-a169-8fb095fafa17
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734445006 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 26.kmac_test_vectors_kmac.3734445006 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_kmac_xof.2281155129
Short name	T803
Test name
Test status
Simulation time	201253863 ps
CPU time	6.3 seconds
Started	Feb 04 02:48:38 PM PST 24
Finished	Feb 04 02:48:47 PM PST 24
Peak memory	218576 kb
Host	smart-9da73956-c0e6-4bdb-82b7-bb3c5e3a5244
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281155129 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_kmac_xof.2281155129 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_224.2258160284
Short name	T1108
Test name
Test status
Simulation time	257090902578 ps
CPU time	2195.51 seconds
Started	Feb 04 02:48:20 PM PST 24
Finished	Feb 04 03:24:59 PM PST 24
Peak memory	392936 kb
Host	smart-66328dd8-a7ba-492e-b200-c8f34179f4da
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2258160284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.2258160284 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_256.1722993517
Short name	T1055
Test name
Test status
Simulation time	253108934865 ps
CPU time	2025.79 seconds
Started	Feb 04 02:48:17 PM PST 24
Finished	Feb 04 03:22:09 PM PST 24
Peak memory	383336 kb
Host	smart-db49ac8b-0fc1-4bbc-8b98-5b8f6f29e91d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1722993517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.1722993517 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_384.1760220339
Short name	T406
Test name
Test status
Simulation time	28745871172 ps
CPU time	1578 seconds
Started	Feb 04 02:48:25 PM PST 24
Finished	Feb 04 03:14:44 PM PST 24
Peak memory	340724 kb
Host	smart-4c6b7eb2-d6aa-4767-8ece-19e8cf1dd4e3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1760220339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.1760220339 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_512.983292102
Short name	T582
Test name
Test status
Simulation time	12519986486 ps
CPU time	1343.01 seconds
Started	Feb 04 02:48:30 PM PST 24
Finished	Feb 04 03:10:54 PM PST 24
Peak memory	304052 kb
Host	smart-25afbb1c-b910-46f4-bc9b-7bec2ea33de3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=983292102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.983292102 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_shake_128.149938040
Short name	T481
Test name
Test status
Simulation time	712889473445 ps
CPU time	6006.34 seconds
Started	Feb 04 02:48:33 PM PST 24
Finished	Feb 04 04:28:41 PM PST 24
Peak memory	640104 kb
Host	smart-a6688183-e569-4d1c-8cc9-a406044f2829
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=149938040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.149938040 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_shake_256.3004907905
Short name	T350
Test name
Test status
Simulation time	214939344632 ps
CPU time	4370.51 seconds
Started	Feb 04 02:48:38 PM PST 24
Finished	Feb 04 04:01:32 PM PST 24
Peak memory	556516 kb
Host	smart-bcf14cec-d959-4cdd-b1ba-cfd913018c0b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3004907905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.3004907905 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/27.kmac_alert_test.2967876457
Short name	T517
Test name
Test status
Simulation time	16804247 ps
CPU time	0.85 seconds
Started	Feb 04 02:49:05 PM PST 24
Finished	Feb 04 02:49:12 PM PST 24
Peak memory	218372 kb
Host	smart-67060308-ca23-4b50-a4fb-123de914483b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967876457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.2967876457 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_alert_test/latest

Test location	/workspace/coverage/default/27.kmac_app.1821155088
Short name	T559
Test name
Test status
Simulation time	49809975895 ps
CPU time	395.25 seconds
Started	Feb 04 02:48:45 PM PST 24
Finished	Feb 04 02:55:24 PM PST 24
Peak memory	253112 kb
Host	smart-b127713f-4322-4d1b-b021-99048d7ef7e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1821155088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.1821155088 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_app/latest

Test location	/workspace/coverage/default/27.kmac_burst_write.3896776048
Short name	T573
Test name
Test status
Simulation time	12400707402 ps
CPU time	1501.47 seconds
Started	Feb 04 02:48:32 PM PST 24
Finished	Feb 04 03:13:35 PM PST 24
Peak memory	243468 kb
Host	smart-f494cb65-fc57-45f2-899d-1e6538b453ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3896776048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.3896776048 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_burst_write/latest

Test location	/workspace/coverage/default/27.kmac_entropy_refresh.2415766579
Short name	T560
Test name
Test status
Simulation time	12208311674 ps
CPU time	84.06 seconds
Started	Feb 04 02:48:44 PM PST 24
Finished	Feb 04 02:50:13 PM PST 24
Peak memory	243464 kb
Host	smart-9d03e3f6-3c63-44d0-9c3c-f9866fa678ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2415766579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.2415766579 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/27.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/27.kmac_error.1590751817
Short name	T527
Test name
Test status
Simulation time	2057945119 ps
CPU time	43.41 seconds
Started	Feb 04 02:48:44 PM PST 24
Finished	Feb 04 02:49:33 PM PST 24
Peak memory	243272 kb
Host	smart-0c41386e-b3f2-4b7d-b0f4-7f9d067c5ec3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1590751817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.1590751817 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_error/latest

Test location	/workspace/coverage/default/27.kmac_key_error.456525078
Short name	T603
Test name
Test status
Simulation time	194921172 ps
CPU time	1.32 seconds
Started	Feb 04 02:48:54 PM PST 24
Finished	Feb 04 02:48:56 PM PST 24
Peak memory	218244 kb
Host	smart-670e75b0-234c-4523-a7e7-1e11cdd55c2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=456525078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.456525078 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_key_error/latest

Test location	/workspace/coverage/default/27.kmac_lc_escalation.2623317795
Short name	T1064
Test name
Test status
Simulation time	213244644 ps
CPU time	13.06 seconds
Started	Feb 04 02:48:53 PM PST 24
Finished	Feb 04 02:49:07 PM PST 24
Peak memory	235052 kb
Host	smart-1bd23d72-4cf7-46f5-9f71-e638de93754d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2623317795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.2623317795 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/27.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/27.kmac_long_msg_and_output.1614473202
Short name	T1056
Test name
Test status
Simulation time	10563139621 ps
CPU time	1249.78 seconds
Started	Feb 04 02:48:33 PM PST 24
Finished	Feb 04 03:09:24 PM PST 24
Peak memory	317792 kb
Host	smart-06c7b2f0-0869-46c0-b0f5-bef525061c7a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614473202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a nd_output.1614473202 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/27.kmac_sideload.3514544992
Short name	T222
Test name
Test status
Simulation time	23346474761 ps
CPU time	622.49 seconds
Started	Feb 04 02:48:32 PM PST 24
Finished	Feb 04 02:58:55 PM PST 24
Peak memory	262712 kb
Host	smart-37a8b7eb-56cf-437d-a33a-0b205224397d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3514544992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.3514544992 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_sideload/latest

Test location	/workspace/coverage/default/27.kmac_smoke.2466189177
Short name	T618
Test name
Test status
Simulation time	3007325919 ps
CPU time	57.47 seconds
Started	Feb 04 02:48:32 PM PST 24
Finished	Feb 04 02:49:30 PM PST 24
Peak memory	223972 kb
Host	smart-bb678e81-18b1-4bde-9870-6cc45865985e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2466189177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.2466189177 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_smoke/latest

Test location	/workspace/coverage/default/27.kmac_stress_all_with_rand_reset.1414928407
Short name	T372
Test name
Test status
Simulation time	70525856331 ps
CPU time	953.17 seconds
Started	Feb 04 02:48:46 PM PST 24
Finished	Feb 04 03:04:42 PM PST 24
Peak memory	325068 kb
Host	smart-297aa1be-8829-46b1-bd9e-799d39a8ba0f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1414928407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all_with_rand_reset.1414928407 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_kmac.2096435924
Short name	T544
Test name
Test status
Simulation time	212169218 ps
CPU time	6.07 seconds
Started	Feb 04 02:48:54 PM PST 24
Finished	Feb 04 02:49:01 PM PST 24
Peak memory	220048 kb
Host	smart-e7593f92-369b-4713-a049-52483fe5bc82
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096435924 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 27.kmac_test_vectors_kmac.2096435924 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_kmac_xof.1585427335
Short name	T107
Test name
Test status
Simulation time	166187174 ps
CPU time	6.39 seconds
Started	Feb 04 02:48:43 PM PST 24
Finished	Feb 04 02:48:55 PM PST 24
Peak memory	218812 kb
Host	smart-0de50c61-f2ca-4dfa-bc56-63cc034d18c5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585427335 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_kmac_xof.1585427335 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_224.2125561319
Short name	T211
Test name
Test status
Simulation time	270890627353 ps
CPU time	2313.95 seconds
Started	Feb 04 02:48:38 PM PST 24
Finished	Feb 04 03:27:15 PM PST 24
Peak memory	395632 kb
Host	smart-3cbc4e8a-7853-4d74-8aa3-4daadddc97c0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2125561319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.2125561319 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_256.2184216865
Short name	T444
Test name
Test status
Simulation time	92654022842 ps
CPU time	2429.11 seconds
Started	Feb 04 02:48:42 PM PST 24
Finished	Feb 04 03:29:17 PM PST 24
Peak memory	380484 kb
Host	smart-be5890fb-d15f-4bfe-ae11-f42b7ca1edaa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2184216865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.2184216865 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_384.2980819982
Short name	T252
Test name
Test status
Simulation time	671602913809 ps
CPU time	1953.54 seconds
Started	Feb 04 02:48:54 PM PST 24
Finished	Feb 04 03:21:29 PM PST 24
Peak memory	339052 kb
Host	smart-e1cec42b-3338-4ae3-b933-f596858da62a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2980819982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.2980819982 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_512.4226225950
Short name	T173
Test name
Test status
Simulation time	38121318734 ps
CPU time	1231.17 seconds
Started	Feb 04 02:48:42 PM PST 24
Finished	Feb 04 03:09:20 PM PST 24
Peak memory	298972 kb
Host	smart-283ab1f5-3b5e-495c-aa92-77e20bfe5fa0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4226225950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.4226225950 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_shake_128.1529868674
Short name	T829
Test name
Test status
Simulation time	1435571895243 ps
CPU time	6660.77 seconds
Started	Feb 04 02:48:43 PM PST 24
Finished	Feb 04 04:39:51 PM PST 24
Peak memory	655316 kb
Host	smart-52411576-d744-4cbc-858a-193cfc66efd3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1529868674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.1529868674 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_shake_256.4096995479
Short name	T390
Test name
Test status
Simulation time	128088199974 ps
CPU time	4704.42 seconds
Started	Feb 04 02:48:43 PM PST 24
Finished	Feb 04 04:07:14 PM PST 24
Peak memory	566128 kb
Host	smart-79c14eed-571f-4a3d-aefe-0c5e4a7852ef
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4096995479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.4096995479 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/28.kmac_alert_test.43602982
Short name	T877
Test name
Test status
Simulation time	11980596 ps
CPU time	0.83 seconds
Started	Feb 04 02:49:33 PM PST 24
Finished	Feb 04 02:49:35 PM PST 24
Peak memory	219496 kb
Host	smart-31e39251-ffd1-4768-bc38-32fd6d91bf8d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43602982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.43602982 +enable_mas king=1 +sw_key_masked=0
Directory	/workspace/28.kmac_alert_test/latest

Test location	/workspace/coverage/default/28.kmac_app.4196925479
Short name	T137
Test name
Test status
Simulation time	24857677708 ps
CPU time	279.34 seconds
Started	Feb 04 02:49:06 PM PST 24
Finished	Feb 04 02:53:50 PM PST 24
Peak memory	249948 kb
Host	smart-4b03c6f6-bc3f-48c2-b199-dc8160d4fc5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4196925479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.4196925479 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_app/latest

Test location	/workspace/coverage/default/28.kmac_burst_write.1654569407
Short name	T915
Test name
Test status
Simulation time	12068013846 ps
CPU time	1314.29 seconds
Started	Feb 04 02:49:05 PM PST 24
Finished	Feb 04 03:11:06 PM PST 24
Peak memory	238968 kb
Host	smart-ad847718-8b8e-4422-8735-e871e8c14d5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1654569407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.1654569407 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_burst_write/latest

Test location	/workspace/coverage/default/28.kmac_error.1908742065
Short name	T964
Test name
Test status
Simulation time	7323619886 ps
CPU time	223.58 seconds
Started	Feb 04 02:49:06 PM PST 24
Finished	Feb 04 02:52:55 PM PST 24
Peak memory	251692 kb
Host	smart-0029ac55-57da-4a33-b0b3-0fb2269f2143
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1908742065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.1908742065 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_error/latest

Test location	/workspace/coverage/default/28.kmac_key_error.1329310818
Short name	T379
Test name
Test status
Simulation time	2739113445 ps
CPU time	3.73 seconds
Started	Feb 04 02:49:06 PM PST 24
Finished	Feb 04 02:49:15 PM PST 24
Peak memory	218772 kb
Host	smart-f2bb2104-fcf1-41e2-b00b-c4b61e9671fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1329310818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.1329310818 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_key_error/latest

Test location	/workspace/coverage/default/28.kmac_lc_escalation.1901051825
Short name	T304
Test name
Test status
Simulation time	68674071 ps
CPU time	1.37 seconds
Started	Feb 04 02:49:05 PM PST 24
Finished	Feb 04 02:49:13 PM PST 24
Peak memory	219728 kb
Host	smart-7d855d75-5f25-4f8e-94f4-cfc14bfe9516
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1901051825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.1901051825 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/28.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/28.kmac_long_msg_and_output.2958293260
Short name	T191
Test name
Test status
Simulation time	102715956246 ps
CPU time	1403.41 seconds
Started	Feb 04 02:49:02 PM PST 24
Finished	Feb 04 03:12:34 PM PST 24
Peak memory	329248 kb
Host	smart-245977a8-a59f-43a1-903d-34eb3b7e7868
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958293260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a nd_output.2958293260 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/28.kmac_sideload.719526158
Short name	T496
Test name
Test status
Simulation time	1277388681 ps
CPU time	12.07 seconds
Started	Feb 04 02:49:02 PM PST 24
Finished	Feb 04 02:49:21 PM PST 24
Peak memory	223016 kb
Host	smart-7e5a134b-ed65-4a89-a802-682422c7725c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=719526158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.719526158 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_sideload/latest

Test location	/workspace/coverage/default/28.kmac_smoke.2498695909
Short name	T1098
Test name
Test status
Simulation time	4837890402 ps
CPU time	89.62 seconds
Started	Feb 04 02:49:05 PM PST 24
Finished	Feb 04 02:50:41 PM PST 24
Peak memory	227136 kb
Host	smart-a13fe180-47a7-496b-9319-6f57a66f6ceb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2498695909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.2498695909 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_smoke/latest

Test location	/workspace/coverage/default/28.kmac_stress_all.2646037918
Short name	T906
Test name
Test status
Simulation time	37039504250 ps
CPU time	1445.29 seconds
Started	Feb 04 02:49:33 PM PST 24
Finished	Feb 04 03:13:40 PM PST 24
Peak memory	351844 kb
Host	smart-9b38483c-37e2-4c50-9bc9-3be92db77d8f
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2646037918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.2646037918 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_stress_all/latest

Test location	/workspace/coverage/default/28.kmac_stress_all_with_rand_reset.929750274
Short name	T268
Test name
Test status
Simulation time	311830107991 ps
CPU time	2041.5 seconds
Started	Feb 04 02:49:34 PM PST 24
Finished	Feb 04 03:23:36 PM PST 24
Peak memory	374000 kb
Host	smart-368a4236-c3fb-4b03-8e8c-598ce018c665
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=929750274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all_with_rand_reset.929750274 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_kmac.1852955588
Short name	T948
Test name
Test status
Simulation time	1302329733 ps
CPU time	6.13 seconds
Started	Feb 04 02:49:05 PM PST 24
Finished	Feb 04 02:49:17 PM PST 24
Peak memory	218860 kb
Host	smart-54f2305a-33a6-442c-83a1-bda15eae5d57
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852955588 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 28.kmac_test_vectors_kmac.1852955588 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_kmac_xof.123092648
Short name	T530
Test name
Test status
Simulation time	237587234 ps
CPU time	5.91 seconds
Started	Feb 04 02:49:04 PM PST 24
Finished	Feb 04 02:49:17 PM PST 24
Peak memory	220116 kb
Host	smart-8ec67ed3-4e86-43f7-879b-b7761452b254
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123092648 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 28.kmac_test_vectors_kmac_xof.123092648 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_224.3006617814
Short name	T751
Test name
Test status
Simulation time	88183878918 ps
CPU time	2114.46 seconds
Started	Feb 04 02:49:04 PM PST 24
Finished	Feb 04 03:24:26 PM PST 24
Peak memory	395324 kb
Host	smart-0ee49447-3e88-4608-ba16-3fa2c929a83f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3006617814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.3006617814 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_256.3932240655
Short name	T285
Test name
Test status
Simulation time	319854445429 ps
CPU time	2339.49 seconds
Started	Feb 04 02:49:06 PM PST 24
Finished	Feb 04 03:28:11 PM PST 24
Peak memory	392584 kb
Host	smart-48dab694-a89f-44a0-8423-fd5d19dff8cf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3932240655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.3932240655 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_384.1467301801
Short name	T700
Test name
Test status
Simulation time	71084484565 ps
CPU time	1948.16 seconds
Started	Feb 04 02:49:05 PM PST 24
Finished	Feb 04 03:21:39 PM PST 24
Peak memory	344348 kb
Host	smart-e68737ce-b269-4b3d-b2f3-1b3e3b0de8fa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1467301801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.1467301801 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_512.248497946
Short name	T972
Test name
Test status
Simulation time	68252716940 ps
CPU time	1219.93 seconds
Started	Feb 04 02:49:05 PM PST 24
Finished	Feb 04 03:09:31 PM PST 24
Peak memory	304084 kb
Host	smart-e2edf3fb-0572-4cab-8087-cb0455adf724
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=248497946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.248497946 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_shake_256.2380581081
Short name	T811
Test name
Test status
Simulation time	230219926147 ps
CPU time	5679.31 seconds
Started	Feb 04 02:49:05 PM PST 24
Finished	Feb 04 04:23:51 PM PST 24
Peak memory	574044 kb
Host	smart-889fee95-e0eb-4498-9828-9b7edaa6280a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2380581081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.2380581081 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/29.kmac_alert_test.283368242
Short name	T409
Test name
Test status
Simulation time	13976057 ps
CPU time	0.83 seconds
Started	Feb 04 02:49:40 PM PST 24
Finished	Feb 04 02:49:41 PM PST 24
Peak memory	218408 kb
Host	smart-bb05d613-0156-4d85-b3fa-f30849a3a4a6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283368242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.283368242 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_alert_test/latest

Test location	/workspace/coverage/default/29.kmac_app.2796812699
Short name	T937
Test name
Test status
Simulation time	8050793604 ps
CPU time	268.99 seconds
Started	Feb 04 02:49:43 PM PST 24
Finished	Feb 04 02:54:13 PM PST 24
Peak memory	247460 kb
Host	smart-10389e89-f984-4480-8128-60b624075247
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2796812699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.2796812699 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_app/latest

Test location	/workspace/coverage/default/29.kmac_burst_write.2525290843
Short name	T753
Test name
Test status
Simulation time	3023794742 ps
CPU time	116.95 seconds
Started	Feb 04 02:49:34 PM PST 24
Finished	Feb 04 02:51:31 PM PST 24
Peak memory	236920 kb
Host	smart-dcd2105b-56fa-4bb6-87f4-f5e18f95dd1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2525290843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.2525290843 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_burst_write/latest

Test location	/workspace/coverage/default/29.kmac_entropy_refresh.2877386869
Short name	T687
Test name
Test status
Simulation time	4987759506 ps
CPU time	97.85 seconds
Started	Feb 04 02:49:43 PM PST 24
Finished	Feb 04 02:51:23 PM PST 24
Peak memory	234388 kb
Host	smart-968e45a1-e7f5-4bd7-8bd1-5be5a688b7e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2877386869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.2877386869 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/29.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/29.kmac_key_error.3433695208
Short name	T292
Test name
Test status
Simulation time	792470339 ps
CPU time	4.98 seconds
Started	Feb 04 02:49:40 PM PST 24
Finished	Feb 04 02:49:46 PM PST 24
Peak memory	218636 kb
Host	smart-4d9e6154-7c1e-4075-8859-feaf30968561
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3433695208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.3433695208 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_key_error/latest

Test location	/workspace/coverage/default/29.kmac_lc_escalation.3522273891
Short name	T1042
Test name
Test status
Simulation time	55378192 ps
CPU time	1.52 seconds
Started	Feb 04 02:49:44 PM PST 24
Finished	Feb 04 02:49:48 PM PST 24
Peak memory	220308 kb
Host	smart-39637de1-7ee3-456f-883d-5b9030c1e7e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3522273891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.3522273891 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/29.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/29.kmac_long_msg_and_output.2693993342
Short name	T825
Test name
Test status
Simulation time	80088938310 ps
CPU time	2923 seconds
Started	Feb 04 02:49:34 PM PST 24
Finished	Feb 04 03:38:18 PM PST 24
Peak memory	449420 kb
Host	smart-8fe20f91-97f6-4cf2-a553-8af280606ab6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693993342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a nd_output.2693993342 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/29.kmac_sideload.1065032437
Short name	T734
Test name
Test status
Simulation time	19732912494 ps
CPU time	478.99 seconds
Started	Feb 04 02:49:27 PM PST 24
Finished	Feb 04 02:57:29 PM PST 24
Peak memory	256976 kb
Host	smart-18d47756-6526-4b10-be3e-9045fdab2136
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1065032437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.1065032437 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_sideload/latest

Test location	/workspace/coverage/default/29.kmac_smoke.395958912
Short name	T658
Test name
Test status
Simulation time	95528495 ps
CPU time	3.09 seconds
Started	Feb 04 02:49:28 PM PST 24
Finished	Feb 04 02:49:33 PM PST 24
Peak memory	220312 kb
Host	smart-12546b91-ea0f-42c9-9622-0c4643947cc5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=395958912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.395958912 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_smoke/latest

Test location	/workspace/coverage/default/29.kmac_stress_all.3052484036
Short name	T669
Test name
Test status
Simulation time	20120957098 ps
CPU time	423.2 seconds
Started	Feb 04 02:49:40 PM PST 24
Finished	Feb 04 02:56:44 PM PST 24
Peak memory	292384 kb
Host	smart-28afd783-de0e-4195-b03f-e16860075183
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3052484036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.3052484036 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_stress_all/latest

Test location	/workspace/coverage/default/29.kmac_stress_all_with_rand_reset.1796907991
Short name	T608
Test name
Test status
Simulation time	22450675902 ps
CPU time	1199.01 seconds
Started	Feb 04 02:49:40 PM PST 24
Finished	Feb 04 03:09:40 PM PST 24
Peak memory	316536 kb
Host	smart-cf5f1d07-26e1-429c-9a18-7bb39f536431
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1796907991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all_with_rand_reset.1796907991 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_kmac.4200854044
Short name	T921
Test name
Test status
Simulation time	242270172 ps
CPU time	5.93 seconds
Started	Feb 04 02:49:42 PM PST 24
Finished	Feb 04 02:49:49 PM PST 24
Peak memory	218652 kb
Host	smart-1f1eadd0-aa89-47d1-a044-a6048b953597
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200854044 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 29.kmac_test_vectors_kmac.4200854044 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_kmac_xof.3320260337
Short name	T296
Test name
Test status
Simulation time	522920451 ps
CPU time	6.89 seconds
Started	Feb 04 02:49:44 PM PST 24
Finished	Feb 04 02:49:54 PM PST 24
Peak memory	220220 kb
Host	smart-86191b93-6c88-4db0-8a37-5eb329b0e675
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320260337 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_kmac_xof.3320260337 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_224.2983599543
Short name	T831
Test name
Test status
Simulation time	267562716278 ps
CPU time	2693.06 seconds
Started	Feb 04 02:49:33 PM PST 24
Finished	Feb 04 03:34:27 PM PST 24
Peak memory	391636 kb
Host	smart-0dce74bd-5045-42fd-bd76-b2739f0c30df
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2983599543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.2983599543 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_256.3725926813
Short name	T584
Test name
Test status
Simulation time	128063082190 ps
CPU time	2154.76 seconds
Started	Feb 04 02:49:34 PM PST 24
Finished	Feb 04 03:25:30 PM PST 24
Peak memory	385724 kb
Host	smart-b11dc3cf-4215-43b7-a3ef-f462009c78a4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3725926813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.3725926813 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_384.1691897705
Short name	T690
Test name
Test status
Simulation time	30351487537 ps
CPU time	1642.67 seconds
Started	Feb 04 02:49:35 PM PST 24
Finished	Feb 04 03:16:58 PM PST 24
Peak memory	341288 kb
Host	smart-258025cf-ef98-43fb-8b13-87f8ba817ac0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1691897705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.1691897705 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_512.1834251116
Short name	T998
Test name
Test status
Simulation time	102092656758 ps
CPU time	1397.28 seconds
Started	Feb 04 02:49:44 PM PST 24
Finished	Feb 04 03:13:03 PM PST 24
Peak memory	296416 kb
Host	smart-e609c82a-c138-47ef-a6bd-a0d4c4791b8d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1834251116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.1834251116 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_shake_128.3209018355
Short name	T1122
Test name
Test status
Simulation time	180943332169 ps
CPU time	6118.81 seconds
Started	Feb 04 02:49:44 PM PST 24
Finished	Feb 04 04:31:47 PM PST 24
Peak memory	652560 kb
Host	smart-a79aacbf-fe55-4795-8896-51a3ca0b4970
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3209018355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.3209018355 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_shake_256.1083146206
Short name	T1100
Test name
Test status
Simulation time	103588344519 ps
CPU time	4487.64 seconds
Started	Feb 04 02:49:38 PM PST 24
Finished	Feb 04 04:04:27 PM PST 24
Peak memory	558980 kb
Host	smart-bd3b729b-ce64-484a-b99f-d16cfd52fe03
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1083146206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.1083146206 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/3.kmac_alert_test.887650192
Short name	T445
Test name
Test status
Simulation time	26868004 ps
CPU time	0.89 seconds
Started	Feb 04 02:44:58 PM PST 24
Finished	Feb 04 02:45:23 PM PST 24
Peak memory	218300 kb
Host	smart-b7acd494-ae08-47f8-a08b-e93c99979521
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887650192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.887650192 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_alert_test/latest

Test location	/workspace/coverage/default/3.kmac_app.2461431507
Short name	T487
Test name
Test status
Simulation time	5153124204 ps
CPU time	31.79 seconds
Started	Feb 04 02:45:02 PM PST 24
Finished	Feb 04 02:45:56 PM PST 24
Peak memory	227452 kb
Host	smart-bf49a63d-91ae-4e39-9c1c-0287b2591e5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2461431507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.2461431507 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_app/latest

Test location	/workspace/coverage/default/3.kmac_app_with_partial_data.2297596756
Short name	T742
Test name
Test status
Simulation time	34763497129 ps
CPU time	250.03 seconds
Started	Feb 04 02:44:54 PM PST 24
Finished	Feb 04 02:49:25 PM PST 24
Peak memory	247324 kb
Host	smart-c3a947b7-b00b-4ab6-8250-5f3fe736b54d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2297596756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.2297596756 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/3.kmac_burst_write.3935859950
Short name	T311
Test name
Test status
Simulation time	61769601773 ps
CPU time	370.44 seconds
Started	Feb 04 02:45:01 PM PST 24
Finished	Feb 04 02:51:34 PM PST 24
Peak memory	240332 kb
Host	smart-45b5f23e-7c76-4730-848f-0e5321f43daa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3935859950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.3935859950 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_burst_write/latest

Test location	/workspace/coverage/default/3.kmac_edn_timeout_error.1671091887
Short name	T1060
Test name
Test status
Simulation time	512827318 ps
CPU time	14.55 seconds
Started	Feb 04 02:45:04 PM PST 24
Finished	Feb 04 02:45:41 PM PST 24
Peak memory	238536 kb
Host	smart-8a0a305b-14fc-4afb-b21e-6886f00c8bbe
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1671091887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.1671091887 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/3.kmac_entropy_mode_error.2917827858
Short name	T769
Test name
Test status
Simulation time	52677332 ps
CPU time	1.09 seconds
Started	Feb 04 02:45:00 PM PST 24
Finished	Feb 04 02:45:25 PM PST 24
Peak memory	218536 kb
Host	smart-6f125217-8687-4d95-bd9c-120e6ba6118f
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2917827858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.2917827858 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/3.kmac_entropy_ready_error.1402337324
Short name	T477
Test name
Test status
Simulation time	7443808843 ps
CPU time	18.03 seconds
Started	Feb 04 02:45:04 PM PST 24
Finished	Feb 04 02:45:45 PM PST 24
Peak memory	218824 kb
Host	smart-c4bb6527-8c9a-4ea4-8d78-1fab5ebe7c44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1402337324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.1402337324 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/3.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/3.kmac_entropy_refresh.3986935240
Short name	T797
Test name
Test status
Simulation time	13307440859 ps
CPU time	372.43 seconds
Started	Feb 04 02:45:13 PM PST 24
Finished	Feb 04 02:51:43 PM PST 24
Peak memory	251804 kb
Host	smart-8245d8bc-9f1f-46ee-bbfd-b80f34c7ad58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3986935240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.3986935240 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/3.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/3.kmac_error.1877096360
Short name	T6
Test name
Test status
Simulation time	36431358871 ps
CPU time	194.2 seconds
Started	Feb 04 02:45:00 PM PST 24
Finished	Feb 04 02:48:37 PM PST 24
Peak memory	251868 kb
Host	smart-800f5121-303d-447b-a396-d6006ca20c73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1877096360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.1877096360 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_error/latest

Test location	/workspace/coverage/default/3.kmac_key_error.2467297370
Short name	T232
Test name
Test status
Simulation time	150202034 ps
CPU time	0.98 seconds
Started	Feb 04 02:45:04 PM PST 24
Finished	Feb 04 02:45:27 PM PST 24
Peak memory	218428 kb
Host	smart-f458eabd-496a-410a-847a-ba553390be8f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2467297370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.2467297370 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_key_error/latest

Test location	/workspace/coverage/default/3.kmac_lc_escalation.172884578
Short name	T305
Test name
Test status
Simulation time	5934767828 ps
CPU time	46.22 seconds
Started	Feb 04 02:44:59 PM PST 24
Finished	Feb 04 02:46:09 PM PST 24
Peak memory	238480 kb
Host	smart-824cca0b-cb7b-41f2-8913-49c9e9c0a66c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=172884578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.172884578 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/3.kmac_long_msg_and_output.1392169878
Short name	T329
Test name
Test status
Simulation time	189377588300 ps
CPU time	956.48 seconds
Started	Feb 04 02:44:55 PM PST 24
Finished	Feb 04 03:01:13 PM PST 24
Peak memory	299912 kb
Host	smart-88dc8643-7026-48f2-bf91-513f0ff154c4
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392169878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an d_output.1392169878 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/3.kmac_mubi.1288783838
Short name	T497
Test name
Test status
Simulation time	10352141801 ps
CPU time	257.15 seconds
Started	Feb 04 02:44:55 PM PST 24
Finished	Feb 04 02:49:34 PM PST 24
Peak memory	248224 kb
Host	smart-19504cfb-d23b-4e4c-af6d-5080f2a9adae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1288783838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.1288783838 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_mubi/latest

Test location	/workspace/coverage/default/3.kmac_sec_cm.3606870138
Short name	T9
Test name
Test status
Simulation time	10831108468 ps
CPU time	119.5 seconds
Started	Feb 04 02:44:59 PM PST 24
Finished	Feb 04 02:47:23 PM PST 24
Peak memory	316504 kb
Host	smart-f9ac0af4-b213-4916-a9ec-b7230588d9b4
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606870138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.3606870138 +enable_maski ng=1 +sw_key_masked=0
Directory	/workspace/3.kmac_sec_cm/latest

Test location	/workspace/coverage/default/3.kmac_sideload.1315751641
Short name	T1047
Test name
Test status
Simulation time	13766020746 ps
CPU time	414.93 seconds
Started	Feb 04 02:44:56 PM PST 24
Finished	Feb 04 02:52:12 PM PST 24
Peak memory	253568 kb
Host	smart-c647de7b-2417-43c6-a31e-72d90f7b65c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1315751641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.1315751641 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_sideload/latest

Test location	/workspace/coverage/default/3.kmac_smoke.2798812150
Short name	T431
Test name
Test status
Simulation time	252318641 ps
CPU time	10.75 seconds
Started	Feb 04 02:44:55 PM PST 24
Finished	Feb 04 02:45:27 PM PST 24
Peak memory	224224 kb
Host	smart-894a9258-df49-4786-b52a-c3f453463a19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2798812150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.2798812150 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_smoke/latest

Test location	/workspace/coverage/default/3.kmac_stress_all.3530082079
Short name	T551
Test name
Test status
Simulation time	135059609019 ps
CPU time	1420.17 seconds
Started	Feb 04 02:45:04 PM PST 24
Finished	Feb 04 03:09:06 PM PST 24
Peak memory	358420 kb
Host	smart-87e8cfb1-9861-4dec-82f6-0652657422b5
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3530082079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.3530082079 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_stress_all/latest

Test location	/workspace/coverage/default/3.kmac_stress_all_with_rand_reset.3749975717
Short name	T725
Test name
Test status
Simulation time	178438360076 ps
CPU time	2033.71 seconds
Started	Feb 04 02:45:05 PM PST 24
Finished	Feb 04 03:19:21 PM PST 24
Peak memory	329792 kb
Host	smart-a457b60a-6c61-4ca5-9266-bf186f356e43
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3749975717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_with_rand_reset.3749975717 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_kmac.2064651795
Short name	T193
Test name
Test status
Simulation time	178484163 ps
CPU time	5.86 seconds
Started	Feb 04 02:45:02 PM PST 24
Finished	Feb 04 02:45:30 PM PST 24
Peak memory	220088 kb
Host	smart-ad2917a4-ebfc-4447-b2eb-7d12c854d6a5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064651795 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 3.kmac_test_vectors_kmac.2064651795 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_kmac_xof.4212213139
Short name	T575
Test name
Test status
Simulation time	804493118 ps
CPU time	6.61 seconds
Started	Feb 04 02:45:10 PM PST 24
Finished	Feb 04 02:45:36 PM PST 24
Peak memory	218892 kb
Host	smart-182e39e8-fda0-4304-9f83-a6c28f4a78d1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212213139 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.4212213139 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_224.975321079
Short name	T907
Test name
Test status
Simulation time	102171451444 ps
CPU time	2519.5 seconds
Started	Feb 04 02:44:55 PM PST 24
Finished	Feb 04 03:27:16 PM PST 24
Peak memory	393876 kb
Host	smart-ea54d7c2-a3e3-4924-97c8-ddb95966e155
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=975321079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.975321079 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_256.3037592194
Short name	T570
Test name
Test status
Simulation time	137362512209 ps
CPU time	2091.5 seconds
Started	Feb 04 02:45:13 PM PST 24
Finished	Feb 04 03:20:22 PM PST 24
Peak memory	380888 kb
Host	smart-94d21e2b-a0a1-4e7e-8774-e380a6c7c02b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3037592194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.3037592194 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_384.238104295
Short name	T597
Test name
Test status
Simulation time	60551576008 ps
CPU time	1626.65 seconds
Started	Feb 04 02:45:01 PM PST 24
Finished	Feb 04 03:12:31 PM PST 24
Peak memory	335772 kb
Host	smart-8300ac6f-a9bd-47ab-8ae7-b5a8f6e59f27
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=238104295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.238104295 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_512.3879628793
Short name	T814
Test name
Test status
Simulation time	33415233085 ps
CPU time	1253.48 seconds
Started	Feb 04 02:45:13 PM PST 24
Finished	Feb 04 03:06:24 PM PST 24
Peak memory	303700 kb
Host	smart-13171eed-4523-4d95-8b01-ba95d593c633
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3879628793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.3879628793 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_shake_128.81597623
Short name	T824
Test name
Test status
Simulation time	250328601194 ps
CPU time	5660.05 seconds
Started	Feb 04 02:44:55 PM PST 24
Finished	Feb 04 04:19:37 PM PST 24
Peak memory	656428 kb
Host	smart-776a82c5-731a-4bcf-a907-33e2dc32685d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=81597623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.81597623 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_shake_256.1876914177
Short name	T786
Test name
Test status
Simulation time	54225919435 ps
CPU time	4524.75 seconds
Started	Feb 04 02:44:56 PM PST 24
Finished	Feb 04 04:00:42 PM PST 24
Peak memory	575764 kb
Host	smart-0de027c2-0b99-43ee-8566-5266aa0412a5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1876914177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.1876914177 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/30.kmac_alert_test.1466827429
Short name	T29
Test name
Test status
Simulation time	41301391 ps
CPU time	0.82 seconds
Started	Feb 04 02:50:05 PM PST 24
Finished	Feb 04 02:50:09 PM PST 24
Peak memory	218296 kb
Host	smart-ab94551f-e41e-4998-a1fb-5ae8614d06e1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466827429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.1466827429 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_alert_test/latest

Test location	/workspace/coverage/default/30.kmac_app.2948682759
Short name	T724
Test name
Test status
Simulation time	17524651957 ps
CPU time	245.24 seconds
Started	Feb 04 02:49:59 PM PST 24
Finished	Feb 04 02:54:05 PM PST 24
Peak memory	247008 kb
Host	smart-699a3146-e4b6-471c-bcfa-6032ea1f3f48
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2948682759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.2948682759 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_app/latest

Test location	/workspace/coverage/default/30.kmac_burst_write.2747781091
Short name	T790
Test name
Test status
Simulation time	42331255687 ps
CPU time	935.45 seconds
Started	Feb 04 02:49:44 PM PST 24
Finished	Feb 04 03:05:22 PM PST 24
Peak memory	243140 kb
Host	smart-6bd45cb4-f2a5-4c5b-9ed0-b443e5319fc3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2747781091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.2747781091 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_burst_write/latest

Test location	/workspace/coverage/default/30.kmac_entropy_refresh.3419778729
Short name	T81
Test name
Test status
Simulation time	156660646558 ps
CPU time	402.07 seconds
Started	Feb 04 02:49:51 PM PST 24
Finished	Feb 04 02:56:38 PM PST 24
Peak memory	254240 kb
Host	smart-76d6c6e9-771f-4af4-b296-f741dbcfed40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3419778729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.3419778729 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/30.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/30.kmac_error.928008304
Short name	T71
Test name
Test status
Simulation time	1732540143 ps
CPU time	162.5 seconds
Started	Feb 04 02:49:52 PM PST 24
Finished	Feb 04 02:52:38 PM PST 24
Peak memory	259700 kb
Host	smart-c916abaf-1e20-45ba-b7cf-763cf2b8cf28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=928008304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.928008304 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_error/latest

Test location	/workspace/coverage/default/30.kmac_key_error.1170124118
Short name	T215
Test name
Test status
Simulation time	1444037262 ps
CPU time	2.82 seconds
Started	Feb 04 02:50:01 PM PST 24
Finished	Feb 04 02:50:04 PM PST 24
Peak memory	218564 kb
Host	smart-9491d841-16e4-4981-ace2-ee681eb53b94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1170124118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.1170124118 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_key_error/latest

Test location	/workspace/coverage/default/30.kmac_lc_escalation.1184478523
Short name	T643
Test name
Test status
Simulation time	51105298 ps
CPU time	1.62 seconds
Started	Feb 04 02:50:04 PM PST 24
Finished	Feb 04 02:50:07 PM PST 24
Peak memory	220192 kb
Host	smart-bba2f859-ddc6-480b-aa12-4060fe9254aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1184478523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.1184478523 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/30.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/30.kmac_long_msg_and_output.803754873
Short name	T180
Test name
Test status
Simulation time	95024551716 ps
CPU time	3404.29 seconds
Started	Feb 04 02:49:44 PM PST 24
Finished	Feb 04 03:46:32 PM PST 24
Peak memory	474960 kb
Host	smart-12450099-2d4e-444a-a303-42a9ae158e6b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803754873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_an d_output.803754873 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/30.kmac_sideload.1680830784
Short name	T419
Test name
Test status
Simulation time	10096385126 ps
CPU time	277.62 seconds
Started	Feb 04 02:49:40 PM PST 24
Finished	Feb 04 02:54:18 PM PST 24
Peak memory	243484 kb
Host	smart-f0385b5d-0e79-4997-ba40-43a4a8977204
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1680830784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.1680830784 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_sideload/latest

Test location	/workspace/coverage/default/30.kmac_smoke.47226781
Short name	T217
Test name
Test status
Simulation time	3277934089 ps
CPU time	71.19 seconds
Started	Feb 04 02:49:41 PM PST 24
Finished	Feb 04 02:50:53 PM PST 24
Peak memory	227160 kb
Host	smart-8cdc47db-e3d6-4a97-b398-ab1dc83abf34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=47226781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.47226781 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_smoke/latest

Test location	/workspace/coverage/default/30.kmac_stress_all.4231379879
Short name	T335
Test name
Test status
Simulation time	145703001840 ps
CPU time	1088.87 seconds
Started	Feb 04 02:50:03 PM PST 24
Finished	Feb 04 03:08:12 PM PST 24
Peak memory	304256 kb
Host	smart-4662766f-e3d8-445b-a194-eeec73d61822
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4231379879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.4231379879 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_stress_all/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_kmac.1973624427
Short name	T1104
Test name
Test status
Simulation time	186297230 ps
CPU time	5.88 seconds
Started	Feb 04 02:49:59 PM PST 24
Finished	Feb 04 02:50:06 PM PST 24
Peak memory	218732 kb
Host	smart-23e68d41-e7a4-477b-9eea-7efd1ad2d722
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973624427 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 30.kmac_test_vectors_kmac.1973624427 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_kmac_xof.2719370343
Short name	T269
Test name
Test status
Simulation time	469812406 ps
CPU time	6.3 seconds
Started	Feb 04 02:49:52 PM PST 24
Finished	Feb 04 02:50:02 PM PST 24
Peak memory	220244 kb
Host	smart-b8260cb5-b879-48bb-a77d-ae64a5bcfa7f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719370343 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_kmac_xof.2719370343 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_224.289559982
Short name	T1118
Test name
Test status
Simulation time	20657389817 ps
CPU time	1837.21 seconds
Started	Feb 04 02:49:40 PM PST 24
Finished	Feb 04 03:20:18 PM PST 24
Peak memory	393168 kb
Host	smart-fd483c3a-80f9-4d07-9f39-a8e2b7e7419a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=289559982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.289559982 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_256.3317639740
Short name	T312
Test name
Test status
Simulation time	197784672578 ps
CPU time	2072.11 seconds
Started	Feb 04 02:49:41 PM PST 24
Finished	Feb 04 03:24:15 PM PST 24
Peak memory	396848 kb
Host	smart-1b1e0533-1bcb-4396-9940-3b9abad8d2bf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3317639740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.3317639740 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_384.1955970381
Short name	T905
Test name
Test status
Simulation time	290319394411 ps
CPU time	1987.07 seconds
Started	Feb 04 02:49:42 PM PST 24
Finished	Feb 04 03:22:50 PM PST 24
Peak memory	339848 kb
Host	smart-a6163740-2567-4f35-a6a2-f3d5dbf062da
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1955970381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.1955970381 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_512.2184066694
Short name	T448
Test name
Test status
Simulation time	92026525315 ps
CPU time	1422.2 seconds
Started	Feb 04 02:49:53 PM PST 24
Finished	Feb 04 03:13:38 PM PST 24
Peak memory	306840 kb
Host	smart-920b77dd-3dc6-400d-b0e1-44fc9c020a1d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2184066694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.2184066694 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_shake_128.203700436
Short name	T327
Test name
Test status
Simulation time	61527117655 ps
CPU time	5241.95 seconds
Started	Feb 04 02:49:54 PM PST 24
Finished	Feb 04 04:17:19 PM PST 24
Peak memory	653608 kb
Host	smart-f6160e10-91f9-49a2-bbee-2e6f9c3bf352
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=203700436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.203700436 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_shake_256.1177116158
Short name	T354
Test name
Test status
Simulation time	907606390376 ps
CPU time	5993.48 seconds
Started	Feb 04 02:49:59 PM PST 24
Finished	Feb 04 04:29:54 PM PST 24
Peak memory	566564 kb
Host	smart-a383619d-d204-4094-a965-807260770ec2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1177116158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.1177116158 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/31.kmac_alert_test.1300879315
Short name	T894
Test name
Test status
Simulation time	19480019 ps
CPU time	0.83 seconds
Started	Feb 04 02:50:32 PM PST 24
Finished	Feb 04 02:50:36 PM PST 24
Peak memory	218380 kb
Host	smart-023b1617-c5ea-4238-92b2-771c8ef5044c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300879315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.1300879315 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_alert_test/latest

Test location	/workspace/coverage/default/31.kmac_app.2364676736
Short name	T306
Test name
Test status
Simulation time	8852060198 ps
CPU time	271.7 seconds
Started	Feb 04 02:50:33 PM PST 24
Finished	Feb 04 02:55:07 PM PST 24
Peak memory	246548 kb
Host	smart-f5a02b1f-6e74-4443-88dd-4374562d51ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2364676736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.2364676736 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_app/latest

Test location	/workspace/coverage/default/31.kmac_entropy_refresh.3208728554
Short name	T876
Test name
Test status
Simulation time	46968363761 ps
CPU time	275.46 seconds
Started	Feb 04 02:50:33 PM PST 24
Finished	Feb 04 02:55:11 PM PST 24
Peak memory	246036 kb
Host	smart-47ac019e-c6de-49c7-9af0-dd9e0bcb19ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3208728554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.3208728554 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/31.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/31.kmac_error.3313574390
Short name	T798
Test name
Test status
Simulation time	4144530105 ps
CPU time	138.56 seconds
Started	Feb 04 02:50:27 PM PST 24
Finished	Feb 04 02:52:47 PM PST 24
Peak memory	251640 kb
Host	smart-5d876376-7844-42a3-8267-2d323a2bca1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3313574390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.3313574390 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_error/latest

Test location	/workspace/coverage/default/31.kmac_key_error.2690656991
Short name	T286
Test name
Test status
Simulation time	312743191 ps
CPU time	2.27 seconds
Started	Feb 04 02:50:25 PM PST 24
Finished	Feb 04 02:50:30 PM PST 24
Peak memory	218436 kb
Host	smart-f47ff84d-c5a0-4fd5-802e-c235a5ad37de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2690656991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.2690656991 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_key_error/latest

Test location	/workspace/coverage/default/31.kmac_lc_escalation.1643447409
Short name	T953
Test name
Test status
Simulation time	242583622 ps
CPU time	1.64 seconds
Started	Feb 04 02:50:24 PM PST 24
Finished	Feb 04 02:50:29 PM PST 24
Peak memory	219916 kb
Host	smart-2b32a606-cf14-42eb-88a8-1de6de71e0ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1643447409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.1643447409 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/31.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/31.kmac_long_msg_and_output.285394876
Short name	T715
Test name
Test status
Simulation time	54024277157 ps
CPU time	2971.53 seconds
Started	Feb 04 02:50:22 PM PST 24
Finished	Feb 04 03:39:56 PM PST 24
Peak memory	471964 kb
Host	smart-e54629e5-166b-4d6b-95c7-2d85f95dced6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285394876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_an d_output.285394876 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/31.kmac_sideload.4133412215
Short name	T410
Test name
Test status
Simulation time	30046976486 ps
CPU time	537.05 seconds
Started	Feb 04 02:50:19 PM PST 24
Finished	Feb 04 02:59:18 PM PST 24
Peak memory	257492 kb
Host	smart-0c071500-2f0e-49e4-9fa4-6468443f3278
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4133412215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.4133412215 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_sideload/latest

Test location	/workspace/coverage/default/31.kmac_smoke.770443358
Short name	T633
Test name
Test status
Simulation time	11295219020 ps
CPU time	89.73 seconds
Started	Feb 04 02:49:59 PM PST 24
Finished	Feb 04 02:51:29 PM PST 24
Peak memory	226976 kb
Host	smart-e9ff1897-928d-4844-ae21-b11c991bff00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=770443358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.770443358 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_smoke/latest

Test location	/workspace/coverage/default/31.kmac_stress_all.1756087730
Short name	T17
Test name
Test status
Simulation time	133424671130 ps
CPU time	2004.33 seconds
Started	Feb 04 02:50:28 PM PST 24
Finished	Feb 04 03:23:58 PM PST 24
Peak memory	415508 kb
Host	smart-be425f98-38a9-4cf1-b8d7-368c18438a88
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1756087730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.1756087730 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_stress_all/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_kmac.621040874
Short name	T1119
Test name
Test status
Simulation time	171384824 ps
CPU time	6.45 seconds
Started	Feb 04 02:50:25 PM PST 24
Finished	Feb 04 02:50:34 PM PST 24
Peak memory	218776 kb
Host	smart-b298829d-5155-44fe-b30a-a4a25466fd38
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621040874 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 31.kmac_test_vectors_kmac.621040874 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_kmac_xof.3067694030
Short name	T1070
Test name
Test status
Simulation time	372648892 ps
CPU time	6.44 seconds
Started	Feb 04 02:50:19 PM PST 24
Finished	Feb 04 02:50:27 PM PST 24
Peak memory	218788 kb
Host	smart-cb21a939-7e74-47cb-90e6-ad709d322e9e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067694030 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_kmac_xof.3067694030 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_224.1344139716
Short name	T822
Test name
Test status
Simulation time	515341362627 ps
CPU time	2520.47 seconds
Started	Feb 04 02:50:17 PM PST 24
Finished	Feb 04 03:32:19 PM PST 24
Peak memory	405660 kb
Host	smart-e6e10df9-e883-4278-9987-256beeb9ffbb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1344139716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.1344139716 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_256.971923614
Short name	T167
Test name
Test status
Simulation time	76641499484 ps
CPU time	2181.29 seconds
Started	Feb 04 02:50:16 PM PST 24
Finished	Feb 04 03:26:39 PM PST 24
Peak memory	388532 kb
Host	smart-153b4002-fcdd-42d1-8ab2-529f9e4af313
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=971923614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.971923614 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_384.2812987257
Short name	T437
Test name
Test status
Simulation time	51307204038 ps
CPU time	1808.26 seconds
Started	Feb 04 02:50:23 PM PST 24
Finished	Feb 04 03:20:33 PM PST 24
Peak memory	341920 kb
Host	smart-2cc9978f-d36b-4f34-9c3c-a35b6aca3c68
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2812987257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.2812987257 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_512.55684690
Short name	T450
Test name
Test status
Simulation time	42133674698 ps
CPU time	1300.16 seconds
Started	Feb 04 02:50:21 PM PST 24
Finished	Feb 04 03:12:02 PM PST 24
Peak memory	303516 kb
Host	smart-e98318a5-c2e4-4792-bd4f-687af1df6728
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=55684690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.55684690 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_shake_128.2312401068
Short name	T216
Test name
Test status
Simulation time	266835228846 ps
CPU time	6821.87 seconds
Started	Feb 04 02:50:17 PM PST 24
Finished	Feb 04 04:44:01 PM PST 24
Peak memory	655604 kb
Host	smart-ac666ba6-4cc9-4cc9-a45e-b48dc908f27b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2312401068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.2312401068 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_shake_256.4155787688
Short name	T328
Test name
Test status
Simulation time	219548134637 ps
CPU time	5748.93 seconds
Started	Feb 04 02:50:19 PM PST 24
Finished	Feb 04 04:26:10 PM PST 24
Peak memory	580484 kb
Host	smart-0dbe4add-0739-46b6-9fac-bcff0e545793
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4155787688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.4155787688 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/32.kmac_alert_test.3335792290
Short name	T324
Test name
Test status
Simulation time	39670001 ps
CPU time	0.83 seconds
Started	Feb 04 02:51:07 PM PST 24
Finished	Feb 04 02:51:09 PM PST 24
Peak memory	218384 kb
Host	smart-4a7093f4-4ac2-45d8-ba3b-7a03137ef275
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335792290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.3335792290 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_alert_test/latest

Test location	/workspace/coverage/default/32.kmac_app.4060294125
Short name	T383
Test name
Test status
Simulation time	55771244625 ps
CPU time	359.94 seconds
Started	Feb 04 02:50:33 PM PST 24
Finished	Feb 04 02:56:35 PM PST 24
Peak memory	250132 kb
Host	smart-3ec8d743-ac8e-4be8-a265-ce0c5eadcc6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4060294125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.4060294125 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_app/latest

Test location	/workspace/coverage/default/32.kmac_burst_write.962213691
Short name	T1072
Test name
Test status
Simulation time	24076058467 ps
CPU time	853.65 seconds
Started	Feb 04 02:50:29 PM PST 24
Finished	Feb 04 03:04:48 PM PST 24
Peak memory	238336 kb
Host	smart-f334a7d4-1ee9-4023-a48e-371076cffa84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=962213691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.962213691 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_burst_write/latest

Test location	/workspace/coverage/default/32.kmac_entropy_refresh.1561445384
Short name	T675
Test name
Test status
Simulation time	18917287508 ps
CPU time	432.03 seconds
Started	Feb 04 02:50:33 PM PST 24
Finished	Feb 04 02:57:47 PM PST 24
Peak memory	252212 kb
Host	smart-580e2625-caae-424c-874c-b7d520abdff1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1561445384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.1561445384 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/32.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/32.kmac_error.505075
Short name	T510
Test name
Test status
Simulation time	2058448141 ps
CPU time	87.7 seconds
Started	Feb 04 02:50:33 PM PST 24
Finished	Feb 04 02:52:03 PM PST 24
Peak memory	243428 kb
Host	smart-73a60066-9d6b-42c8-936d-e22ecedc1d84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=505075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.505075 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_error/latest

Test location	/workspace/coverage/default/32.kmac_lc_escalation.510786508
Short name	T100
Test name
Test status
Simulation time	60130132 ps
CPU time	1.42 seconds
Started	Feb 04 02:50:44 PM PST 24
Finished	Feb 04 02:50:46 PM PST 24
Peak memory	219772 kb
Host	smart-8077a44d-88d2-473c-8f44-b5e9d8603e86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=510786508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.510786508 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/32.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/32.kmac_long_msg_and_output.3230949475
Short name	T1014
Test name
Test status
Simulation time	67062374585 ps
CPU time	2019.16 seconds
Started	Feb 04 02:50:24 PM PST 24
Finished	Feb 04 03:24:07 PM PST 24
Peak memory	386316 kb
Host	smart-9b5a1218-6434-41f2-91f0-29260a978b7f
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230949475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a nd_output.3230949475 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/32.kmac_sideload.401706561
Short name	T376
Test name
Test status
Simulation time	15256634462 ps
CPU time	115.56 seconds
Started	Feb 04 02:50:33 PM PST 24
Finished	Feb 04 02:52:31 PM PST 24
Peak memory	234104 kb
Host	smart-301ce7b4-dfc8-4c26-918f-8c93384e30b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=401706561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.401706561 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_sideload/latest

Test location	/workspace/coverage/default/32.kmac_smoke.79034898
Short name	T235
Test name
Test status
Simulation time	8941654354 ps
CPU time	63.76 seconds
Started	Feb 04 02:50:33 PM PST 24
Finished	Feb 04 02:51:39 PM PST 24
Peak memory	223124 kb
Host	smart-5df7ed4d-7aaf-4620-a00d-b665fc4df33a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=79034898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.79034898 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_smoke/latest

Test location	/workspace/coverage/default/32.kmac_stress_all.1559505885
Short name	T83
Test name
Test status
Simulation time	5997401513 ps
CPU time	428.45 seconds
Started	Feb 04 02:50:46 PM PST 24
Finished	Feb 04 02:57:56 PM PST 24
Peak memory	269456 kb
Host	smart-ae18ffe6-755e-47ba-a603-e3ad24faf8c3
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1559505885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.1559505885 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_stress_all/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_kmac.1598806728
Short name	T588
Test name
Test status
Simulation time	183960079 ps
CPU time	6.13 seconds
Started	Feb 04 02:50:34 PM PST 24
Finished	Feb 04 02:50:42 PM PST 24
Peak memory	218800 kb
Host	smart-6680d360-0a13-4d94-bbf6-b176addd4d2f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598806728 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 32.kmac_test_vectors_kmac.1598806728 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_kmac_xof.2530670082
Short name	T480
Test name
Test status
Simulation time	167218666 ps
CPU time	7.02 seconds
Started	Feb 04 02:50:36 PM PST 24
Finished	Feb 04 02:50:44 PM PST 24
Peak memory	218888 kb
Host	smart-26e4df46-032e-4a0d-b759-f37c96a0adad
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530670082 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_kmac_xof.2530670082 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_224.1585448068
Short name	T340
Test name
Test status
Simulation time	131641379347 ps
CPU time	2486.34 seconds
Started	Feb 04 02:50:26 PM PST 24
Finished	Feb 04 03:31:55 PM PST 24
Peak memory	401768 kb
Host	smart-aa2d139c-76fc-4e31-9058-3368fbe0ee12
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1585448068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.1585448068 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_256.1873528800
Short name	T942
Test name
Test status
Simulation time	77753645938 ps
CPU time	1851.87 seconds
Started	Feb 04 02:50:23 PM PST 24
Finished	Feb 04 03:21:18 PM PST 24
Peak memory	395344 kb
Host	smart-f94cb3d3-dd70-49b0-8560-a635492e0b32
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1873528800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.1873528800 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_384.522364100
Short name	T670
Test name
Test status
Simulation time	199449003932 ps
CPU time	1827.19 seconds
Started	Feb 04 02:50:35 PM PST 24
Finished	Feb 04 03:21:04 PM PST 24
Peak memory	342116 kb
Host	smart-825b20b3-67ba-4210-aa24-012f4151f601
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=522364100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.522364100 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_512.542018213
Short name	T840
Test name
Test status
Simulation time	151550947135 ps
CPU time	1382.18 seconds
Started	Feb 04 02:50:33 PM PST 24
Finished	Feb 04 03:13:37 PM PST 24
Peak memory	302092 kb
Host	smart-942ad753-e6f7-4d74-85ad-661b0ae18f1c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=542018213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.542018213 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_shake_128.2834186999
Short name	T109
Test name
Test status
Simulation time	544197739766 ps
CPU time	5583.72 seconds
Started	Feb 04 02:50:33 PM PST 24
Finished	Feb 04 04:23:39 PM PST 24
Peak memory	659708 kb
Host	smart-28f2f647-4f20-4bcf-8467-e527cd969542
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2834186999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.2834186999 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_shake_256.1880517809
Short name	T154
Test name
Test status
Simulation time	439934964532 ps
CPU time	5527.86 seconds
Started	Feb 04 02:50:34 PM PST 24
Finished	Feb 04 04:22:44 PM PST 24
Peak memory	577156 kb
Host	smart-eea2ef1f-e0a2-4f6c-a8c1-aec95d95da6c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1880517809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.1880517809 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/33.kmac_alert_test.465415010
Short name	T843
Test name
Test status
Simulation time	34822520 ps
CPU time	0.84 seconds
Started	Feb 04 02:51:53 PM PST 24
Finished	Feb 04 02:51:59 PM PST 24
Peak memory	219508 kb
Host	smart-f7087562-0dfc-493b-a907-5020858472c9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465415010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.465415010 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_alert_test/latest

Test location	/workspace/coverage/default/33.kmac_app.1614850621
Short name	T623
Test name
Test status
Simulation time	16829300136 ps
CPU time	153.83 seconds
Started	Feb 04 02:51:20 PM PST 24
Finished	Feb 04 02:53:55 PM PST 24
Peak memory	235976 kb
Host	smart-1b47b7e4-1804-42bf-9b97-26aa4725f944
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1614850621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.1614850621 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_app/latest

Test location	/workspace/coverage/default/33.kmac_burst_write.3557772642
Short name	T31
Test name
Test status
Simulation time	10899433576 ps
CPU time	557.11 seconds
Started	Feb 04 02:51:06 PM PST 24
Finished	Feb 04 03:00:25 PM PST 24
Peak memory	243520 kb
Host	smart-d19ed73f-d3bd-422f-8ba9-035adb10f047
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3557772642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.3557772642 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_burst_write/latest

Test location	/workspace/coverage/default/33.kmac_entropy_refresh.65461930
Short name	T947
Test name
Test status
Simulation time	18000989823 ps
CPU time	198.43 seconds
Started	Feb 04 02:51:21 PM PST 24
Finished	Feb 04 02:54:40 PM PST 24
Peak memory	244804 kb
Host	smart-9b232c0d-cbe6-40b5-9373-7a6bb37146b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=65461930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.65461930 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/33.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/33.kmac_key_error.3236437603
Short name	T1030
Test name
Test status
Simulation time	109063502 ps
CPU time	1.28 seconds
Started	Feb 04 02:51:21 PM PST 24
Finished	Feb 04 02:51:23 PM PST 24
Peak memory	218376 kb
Host	smart-ff49101c-bb45-4499-ac68-25b815293edb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3236437603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.3236437603 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_key_error/latest

Test location	/workspace/coverage/default/33.kmac_lc_escalation.2145462159
Short name	T1032
Test name
Test status
Simulation time	157410735 ps
CPU time	1.7 seconds
Started	Feb 04 02:51:20 PM PST 24
Finished	Feb 04 02:51:22 PM PST 24
Peak memory	219776 kb
Host	smart-1be595a1-d94c-4634-ab09-966b7dcd8bc5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2145462159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.2145462159 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/33.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/33.kmac_long_msg_and_output.1931971971
Short name	T458
Test name
Test status
Simulation time	16438110505 ps
CPU time	105.42 seconds
Started	Feb 04 02:51:07 PM PST 24
Finished	Feb 04 02:52:53 PM PST 24
Peak memory	236532 kb
Host	smart-8807817a-f9ec-4e32-839c-6da05c7fa80a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931971971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a nd_output.1931971971 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/33.kmac_sideload.3189279054
Short name	T175
Test name
Test status
Simulation time	4942003551 ps
CPU time	482 seconds
Started	Feb 04 02:51:05 PM PST 24
Finished	Feb 04 02:59:08 PM PST 24
Peak memory	254384 kb
Host	smart-c0082916-e853-47df-b4ac-355e2b152a23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3189279054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.3189279054 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_sideload/latest

Test location	/workspace/coverage/default/33.kmac_smoke.72248845
Short name	T685
Test name
Test status
Simulation time	259639019 ps
CPU time	5.48 seconds
Started	Feb 04 02:51:11 PM PST 24
Finished	Feb 04 02:51:19 PM PST 24
Peak memory	223040 kb
Host	smart-291f7931-59a7-4d06-8da2-7864b59d91cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=72248845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.72248845 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_smoke/latest

Test location	/workspace/coverage/default/33.kmac_stress_all.3641491835
Short name	T373
Test name
Test status
Simulation time	653614319456 ps
CPU time	3597.11 seconds
Started	Feb 04 02:51:57 PM PST 24
Finished	Feb 04 03:51:56 PM PST 24
Peak memory	473176 kb
Host	smart-5adc814c-b9ee-4c9d-b649-762b5f4b1093
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3641491835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.3641491835 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_stress_all/latest

Test location	/workspace/coverage/default/33.kmac_stress_all_with_rand_reset.4195630101
Short name	T710
Test name
Test status
Simulation time	364299707371 ps
CPU time	3208.43 seconds
Started	Feb 04 02:51:57 PM PST 24
Finished	Feb 04 03:45:28 PM PST 24
Peak memory	430536 kb
Host	smart-e168e327-74d4-475a-84b6-e1bc3de6550b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4195630101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all_with_rand_reset.4195630101 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_kmac.2839324073
Short name	T705
Test name
Test status
Simulation time	482358286 ps
CPU time	6.49 seconds
Started	Feb 04 02:51:23 PM PST 24
Finished	Feb 04 02:51:30 PM PST 24
Peak memory	218780 kb
Host	smart-b24abd8d-a573-44ee-928f-78777e4a7002
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839324073 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 33.kmac_test_vectors_kmac.2839324073 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_kmac_xof.683739885
Short name	T656
Test name
Test status
Simulation time	482726890 ps
CPU time	6.95 seconds
Started	Feb 04 02:51:23 PM PST 24
Finished	Feb 04 02:51:31 PM PST 24
Peak memory	220044 kb
Host	smart-2d6b4a77-05ec-43b4-8cc9-c51dc9c74323
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683739885 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 33.kmac_test_vectors_kmac_xof.683739885 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_224.1123418387
Short name	T368
Test name
Test status
Simulation time	46358473686 ps
CPU time	2159.01 seconds
Started	Feb 04 02:51:00 PM PST 24
Finished	Feb 04 03:27:00 PM PST 24
Peak memory	392416 kb
Host	smart-561181b8-1f35-44e2-9393-4c8bd2e91edb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1123418387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.1123418387 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_256.2576991990
Short name	T164
Test name
Test status
Simulation time	67970225367 ps
CPU time	2186.76 seconds
Started	Feb 04 02:51:08 PM PST 24
Finished	Feb 04 03:27:36 PM PST 24
Peak memory	389816 kb
Host	smart-87111935-3ea9-4ed5-b41e-e05cc2d86ff0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2576991990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.2576991990 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_384.3250901777
Short name	T412
Test name
Test status
Simulation time	74272730220 ps
CPU time	1824.64 seconds
Started	Feb 04 02:51:10 PM PST 24
Finished	Feb 04 03:21:37 PM PST 24
Peak memory	343904 kb
Host	smart-3451a30a-e1f6-4d81-8bd9-812843456977
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3250901777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.3250901777 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_512.3959779922
Short name	T872
Test name
Test status
Simulation time	10626028790 ps
CPU time	1394.69 seconds
Started	Feb 04 02:51:07 PM PST 24
Finished	Feb 04 03:14:23 PM PST 24
Peak memory	301404 kb
Host	smart-ae8e3582-82e3-4979-9156-d6e1ec0b17b7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3959779922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.3959779922 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_shake_128.4122489423
Short name	T885
Test name
Test status
Simulation time	295730727281 ps
CPU time	5688.16 seconds
Started	Feb 04 02:51:20 PM PST 24
Finished	Feb 04 04:26:10 PM PST 24
Peak memory	657008 kb
Host	smart-d324e61a-0612-45ea-8d40-4ee236af5772
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4122489423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.4122489423 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_shake_256.3471835301
Short name	T508
Test name
Test status
Simulation time	446839396941 ps
CPU time	5699.98 seconds
Started	Feb 04 02:51:22 PM PST 24
Finished	Feb 04 04:26:23 PM PST 24
Peak memory	559448 kb
Host	smart-ceed7085-da56-4df3-bde6-020178f965f7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3471835301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.3471835301 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/34.kmac_alert_test.3611054715
Short name	T648
Test name
Test status
Simulation time	27856574 ps
CPU time	0.81 seconds
Started	Feb 04 02:51:58 PM PST 24
Finished	Feb 04 02:52:00 PM PST 24
Peak memory	219424 kb
Host	smart-6298b1b8-ae45-4924-a00c-c156c5e17742
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611054715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.3611054715 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_alert_test/latest

Test location	/workspace/coverage/default/34.kmac_app.2331146681
Short name	T596
Test name
Test status
Simulation time	11540625159 ps
CPU time	340.91 seconds
Started	Feb 04 02:52:06 PM PST 24
Finished	Feb 04 02:57:48 PM PST 24
Peak memory	249744 kb
Host	smart-0ad4e36f-510a-4472-be62-85264b182953
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2331146681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.2331146681 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_app/latest

Test location	/workspace/coverage/default/34.kmac_burst_write.19364279
Short name	T722
Test name
Test status
Simulation time	11258293135 ps
CPU time	1179.48 seconds
Started	Feb 04 02:51:58 PM PST 24
Finished	Feb 04 03:11:39 PM PST 24
Peak memory	238888 kb
Host	smart-1b08b6a5-4d03-43ee-b593-dac7c2f304fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=19364279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.19364279 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_burst_write/latest

Test location	/workspace/coverage/default/34.kmac_entropy_refresh.845772363
Short name	T1021
Test name
Test status
Simulation time	16590729020 ps
CPU time	417.85 seconds
Started	Feb 04 02:52:05 PM PST 24
Finished	Feb 04 02:59:04 PM PST 24
Peak memory	252908 kb
Host	smart-09c05541-2ad1-4353-9196-b93ed7d9f508
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=845772363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.845772363 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/34.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/34.kmac_error.884700031
Short name	T862
Test name
Test status
Simulation time	1767107612 ps
CPU time	144 seconds
Started	Feb 04 02:52:04 PM PST 24
Finished	Feb 04 02:54:28 PM PST 24
Peak memory	251568 kb
Host	smart-9afafed7-9e2a-4c3f-ad6f-cfe6e9f3332d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=884700031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.884700031 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_error/latest

Test location	/workspace/coverage/default/34.kmac_key_error.2344660179
Short name	T202
Test name
Test status
Simulation time	1026381274 ps
CPU time	3.6 seconds
Started	Feb 04 02:52:01 PM PST 24
Finished	Feb 04 02:52:05 PM PST 24
Peak memory	218672 kb
Host	smart-ee33951a-6776-43fe-b073-beff2c59be2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2344660179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.2344660179 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_key_error/latest

Test location	/workspace/coverage/default/34.kmac_lc_escalation.1133690040
Short name	T273
Test name
Test status
Simulation time	224017354 ps
CPU time	1.49 seconds
Started	Feb 04 02:52:06 PM PST 24
Finished	Feb 04 02:52:09 PM PST 24
Peak memory	219940 kb
Host	smart-2fc06024-94a8-4811-88ee-a7ecf96a3c8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1133690040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.1133690040 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/34.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/34.kmac_long_msg_and_output.439188423
Short name	T467
Test name
Test status
Simulation time	19020789935 ps
CPU time	2145.42 seconds
Started	Feb 04 02:51:53 PM PST 24
Finished	Feb 04 03:27:44 PM PST 24
Peak memory	400228 kb
Host	smart-a7f90943-4bc6-49b4-9fbe-a75596b3af86
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439188423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_an d_output.439188423 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/34.kmac_sideload.45308676
Short name	T613
Test name
Test status
Simulation time	83472088 ps
CPU time	6.72 seconds
Started	Feb 04 02:51:53 PM PST 24
Finished	Feb 04 02:52:05 PM PST 24
Peak memory	225800 kb
Host	smart-876d2c83-c308-48dc-8372-bde6ff2c8641
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=45308676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.45308676 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_sideload/latest

Test location	/workspace/coverage/default/34.kmac_smoke.1298084765
Short name	T465
Test name
Test status
Simulation time	1451604808 ps
CPU time	37.13 seconds
Started	Feb 04 02:52:07 PM PST 24
Finished	Feb 04 02:52:45 PM PST 24
Peak memory	224200 kb
Host	smart-affcab62-0393-4eb2-a32c-98387677dd23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1298084765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.1298084765 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_smoke/latest

Test location	/workspace/coverage/default/34.kmac_stress_all.1638432515
Short name	T519
Test name
Test status
Simulation time	147905734599 ps
CPU time	1110.69 seconds
Started	Feb 04 02:51:54 PM PST 24
Finished	Feb 04 03:10:29 PM PST 24
Peak memory	342024 kb
Host	smart-9dfbc77e-ea41-4542-9f67-89a7d9accfe4
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1638432515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.1638432515 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_stress_all/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_kmac.3057310358
Short name	T1023
Test name
Test status
Simulation time	211876134 ps
CPU time	6.36 seconds
Started	Feb 04 02:51:58 PM PST 24
Finished	Feb 04 02:52:06 PM PST 24
Peak memory	218792 kb
Host	smart-1930e264-c59d-44ec-9c6a-f47343835f90
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057310358 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 34.kmac_test_vectors_kmac.3057310358 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_kmac_xof.1987790741
Short name	T569
Test name
Test status
Simulation time	2202129082 ps
CPU time	7.67 seconds
Started	Feb 04 02:51:47 PM PST 24
Finished	Feb 04 02:51:56 PM PST 24
Peak memory	220436 kb
Host	smart-07c885bd-3439-4baf-b4b8-64968d404842
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987790741 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_kmac_xof.1987790741 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_224.3951415545
Short name	T512
Test name
Test status
Simulation time	21830228949 ps
CPU time	1915.81 seconds
Started	Feb 04 02:51:59 PM PST 24
Finished	Feb 04 03:23:56 PM PST 24
Peak memory	399236 kb
Host	smart-79e5bfc5-9ba1-4c1b-8206-d112413ce213
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3951415545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.3951415545 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_256.393247333
Short name	T579
Test name
Test status
Simulation time	39021013055 ps
CPU time	1797.09 seconds
Started	Feb 04 02:51:59 PM PST 24
Finished	Feb 04 03:21:57 PM PST 24
Peak memory	394292 kb
Host	smart-a28a934a-58c8-4d4d-b7bd-eb98124eee05
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=393247333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.393247333 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_384.673583124
Short name	T574
Test name
Test status
Simulation time	14723863108 ps
CPU time	1607.85 seconds
Started	Feb 04 02:51:56 PM PST 24
Finished	Feb 04 03:18:47 PM PST 24
Peak memory	336704 kb
Host	smart-356c9f3b-dbff-4a08-a60e-1d5718ae556a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=673583124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.673583124 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_512.3526669708
Short name	T838
Test name
Test status
Simulation time	139279463838 ps
CPU time	1333.13 seconds
Started	Feb 04 02:51:55 PM PST 24
Finished	Feb 04 03:14:12 PM PST 24
Peak memory	302580 kb
Host	smart-fc41d0f0-c6ba-4459-b0d1-127a5d6b5095
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3526669708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.3526669708 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_shake_128.2594908027
Short name	T221
Test name
Test status
Simulation time	1255104210707 ps
CPU time	6750.04 seconds
Started	Feb 04 02:51:46 PM PST 24
Finished	Feb 04 04:44:18 PM PST 24
Peak memory	669264 kb
Host	smart-03aab98f-47c9-4513-b9a6-0e694159b95c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2594908027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.2594908027 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_shake_256.1730026445
Short name	T898
Test name
Test status
Simulation time	238551001092 ps
CPU time	5326.52 seconds
Started	Feb 04 02:52:07 PM PST 24
Finished	Feb 04 04:20:55 PM PST 24
Peak memory	566360 kb
Host	smart-128debd4-5752-4362-947e-799b096bf4a7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1730026445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.1730026445 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/35.kmac_alert_test.1093606158
Short name	T1063
Test name
Test status
Simulation time	26637760 ps
CPU time	0.87 seconds
Started	Feb 04 02:52:49 PM PST 24
Finished	Feb 04 02:52:52 PM PST 24
Peak memory	219492 kb
Host	smart-ce73b093-7efc-44a4-a162-d80f8bd2ab35
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093606158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.1093606158 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_alert_test/latest

Test location	/workspace/coverage/default/35.kmac_app.1261021330
Short name	T290
Test name
Test status
Simulation time	10648039949 ps
CPU time	268.51 seconds
Started	Feb 04 02:52:22 PM PST 24
Finished	Feb 04 02:56:52 PM PST 24
Peak memory	245268 kb
Host	smart-1dd0c9a4-5170-440c-bdbb-8b2b0e053749
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1261021330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.1261021330 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_app/latest

Test location	/workspace/coverage/default/35.kmac_burst_write.3370826952
Short name	T602
Test name
Test status
Simulation time	23077940304 ps
CPU time	333.71 seconds
Started	Feb 04 02:52:08 PM PST 24
Finished	Feb 04 02:57:42 PM PST 24
Peak memory	239496 kb
Host	smart-855b346a-a602-4a14-a099-d5403e98d3ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3370826952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.3370826952 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_burst_write/latest

Test location	/workspace/coverage/default/35.kmac_entropy_refresh.647076856
Short name	T75
Test name
Test status
Simulation time	20696511287 ps
CPU time	352.93 seconds
Started	Feb 04 02:52:22 PM PST 24
Finished	Feb 04 02:58:17 PM PST 24
Peak memory	249236 kb
Host	smart-9204902f-2f95-4cf8-a032-a2f575c2db17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=647076856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.647076856 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/35.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/35.kmac_error.1794664203
Short name	T223
Test name
Test status
Simulation time	1603390075 ps
CPU time	14.49 seconds
Started	Feb 04 02:52:21 PM PST 24
Finished	Feb 04 02:52:36 PM PST 24
Peak memory	238368 kb
Host	smart-48d9d656-d973-4bb6-a4eb-dfaa04d9a3e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1794664203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.1794664203 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_error/latest

Test location	/workspace/coverage/default/35.kmac_key_error.2337614840
Short name	T462
Test name
Test status
Simulation time	1922477373 ps
CPU time	3.93 seconds
Started	Feb 04 02:52:19 PM PST 24
Finished	Feb 04 02:52:25 PM PST 24
Peak memory	218612 kb
Host	smart-30357fe4-7615-4734-b15f-c548c6756ce8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2337614840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.2337614840 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_key_error/latest

Test location	/workspace/coverage/default/35.kmac_lc_escalation.3775117749
Short name	T672
Test name
Test status
Simulation time	176998695 ps
CPU time	1.3 seconds
Started	Feb 04 02:52:43 PM PST 24
Finished	Feb 04 02:52:46 PM PST 24
Peak memory	218796 kb
Host	smart-64e4c712-7053-4832-8863-9ee2431fb7d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3775117749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.3775117749 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/35.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/35.kmac_long_msg_and_output.2742465047
Short name	T880
Test name
Test status
Simulation time	34706615533 ps
CPU time	675.23 seconds
Started	Feb 04 02:52:07 PM PST 24
Finished	Feb 04 03:03:24 PM PST 24
Peak memory	270584 kb
Host	smart-4f342fef-570e-4cbb-94fc-dba8dfb371ed
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742465047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a nd_output.2742465047 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/35.kmac_sideload.1504866739
Short name	T1127
Test name
Test status
Simulation time	27134788416 ps
CPU time	206.12 seconds
Started	Feb 04 02:52:08 PM PST 24
Finished	Feb 04 02:55:35 PM PST 24
Peak memory	238352 kb
Host	smart-af8eb08f-e760-43fd-a4c8-5f4fba8abbab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1504866739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.1504866739 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_sideload/latest

Test location	/workspace/coverage/default/35.kmac_smoke.1653130555
Short name	T447
Test name
Test status
Simulation time	14466140748 ps
CPU time	84.87 seconds
Started	Feb 04 02:52:08 PM PST 24
Finished	Feb 04 02:53:34 PM PST 24
Peak memory	227164 kb
Host	smart-c12311d7-dc2f-4e55-996f-a306533d868c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1653130555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.1653130555 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_smoke/latest

Test location	/workspace/coverage/default/35.kmac_stress_all.2274988415
Short name	T681
Test name
Test status
Simulation time	105279384808 ps
CPU time	1812.47 seconds
Started	Feb 04 02:52:47 PM PST 24
Finished	Feb 04 03:23:00 PM PST 24
Peak memory	389760 kb
Host	smart-e1386baa-a402-4d75-8ecd-4aadc41fa31b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2274988415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.2274988415 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_stress_all/latest

Test location	/workspace/coverage/default/35.kmac_stress_all_with_rand_reset.1626171199
Short name	T861
Test name
Test status
Simulation time	81620667499 ps
CPU time	3881.13 seconds
Started	Feb 04 02:52:50 PM PST 24
Finished	Feb 04 03:57:34 PM PST 24
Peak memory	513760 kb
Host	smart-a53ba4f2-c643-459b-ae69-d26b0bd17bb1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1626171199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all_with_rand_reset.1626171199 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_kmac.128012156
Short name	T214
Test name
Test status
Simulation time	546620925 ps
CPU time	7.24 seconds
Started	Feb 04 02:52:19 PM PST 24
Finished	Feb 04 02:52:29 PM PST 24
Peak memory	218984 kb
Host	smart-bb73db09-b1e1-4a24-a1b7-c197e7741700
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128012156 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 35.kmac_test_vectors_kmac.128012156 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_kmac_xof.452232078
Short name	T538
Test name
Test status
Simulation time	1241876938 ps
CPU time	5.73 seconds
Started	Feb 04 02:52:20 PM PST 24
Finished	Feb 04 02:52:27 PM PST 24
Peak memory	220248 kb
Host	smart-5463efcf-3cf2-4957-b82f-ce01b1058de6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452232078 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 35.kmac_test_vectors_kmac_xof.452232078 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_224.2676178673
Short name	T943
Test name
Test status
Simulation time	82867478094 ps
CPU time	2302.38 seconds
Started	Feb 04 02:52:08 PM PST 24
Finished	Feb 04 03:30:32 PM PST 24
Peak memory	400068 kb
Host	smart-c32b9023-9354-47db-b80e-c20c608f149d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2676178673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.2676178673 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_256.940096119
Short name	T422
Test name
Test status
Simulation time	19718114085 ps
CPU time	1886.19 seconds
Started	Feb 04 02:52:08 PM PST 24
Finished	Feb 04 03:23:36 PM PST 24
Peak memory	391768 kb
Host	smart-ec3034da-c30e-44e6-85f7-09659bfbefcb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=940096119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.940096119 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_384.537792139
Short name	T334
Test name
Test status
Simulation time	92869304415 ps
CPU time	1925.55 seconds
Started	Feb 04 02:52:08 PM PST 24
Finished	Feb 04 03:24:15 PM PST 24
Peak memory	336508 kb
Host	smart-ae9f8bcd-bc65-4ae2-8c7d-846b060fb8c6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=537792139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.537792139 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_512.1219520812
Short name	T251
Test name
Test status
Simulation time	48058205154 ps
CPU time	1308.15 seconds
Started	Feb 04 02:52:08 PM PST 24
Finished	Feb 04 03:13:57 PM PST 24
Peak memory	298640 kb
Host	smart-52e932a4-837d-4a39-9285-254710c6e4a0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1219520812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.1219520812 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_shake_128.2495514588
Short name	T581
Test name
Test status
Simulation time	700898393120 ps
CPU time	6123.25 seconds
Started	Feb 04 02:52:21 PM PST 24
Finished	Feb 04 04:34:26 PM PST 24
Peak memory	645824 kb
Host	smart-3f9c75a7-a350-402e-88ec-6aaac60c390e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2495514588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.2495514588 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_shake_256.299779674
Short name	T369
Test name
Test status
Simulation time	277439493203 ps
CPU time	5989.64 seconds
Started	Feb 04 02:52:22 PM PST 24
Finished	Feb 04 04:32:13 PM PST 24
Peak memory	565376 kb
Host	smart-549e0ba1-2aa1-4697-a749-dab58bb7bdd1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=299779674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.299779674 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/36.kmac_alert_test.2012017876
Short name	T471
Test name
Test status
Simulation time	19856479 ps
CPU time	0.86 seconds
Started	Feb 04 02:53:15 PM PST 24
Finished	Feb 04 02:53:18 PM PST 24
Peak memory	219476 kb
Host	smart-2d2be17d-6a0c-44db-b9a5-c30b8adf0e4d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012017876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.2012017876 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_alert_test/latest

Test location	/workspace/coverage/default/36.kmac_app.3496979228
Short name	T238
Test name
Test status
Simulation time	2724083770 ps
CPU time	136.05 seconds
Started	Feb 04 02:53:00 PM PST 24
Finished	Feb 04 02:55:17 PM PST 24
Peak memory	240532 kb
Host	smart-f5a1a5c2-f6a4-4fb3-8f9c-03ed84ff98fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3496979228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.3496979228 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_app/latest

Test location	/workspace/coverage/default/36.kmac_burst_write.3579899070
Short name	T616
Test name
Test status
Simulation time	46138963560 ps
CPU time	1699.11 seconds
Started	Feb 04 02:52:50 PM PST 24
Finished	Feb 04 03:21:11 PM PST 24
Peak memory	243492 kb
Host	smart-46531dda-75b2-40f8-9171-9be1e23cf607
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3579899070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.3579899070 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_burst_write/latest

Test location	/workspace/coverage/default/36.kmac_entropy_refresh.4076151074
Short name	T246
Test name
Test status
Simulation time	108312948548 ps
CPU time	393.71 seconds
Started	Feb 04 02:52:58 PM PST 24
Finished	Feb 04 02:59:33 PM PST 24
Peak memory	250488 kb
Host	smart-abb32445-9f3d-4e4d-b416-fe543d2bafeb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4076151074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.4076151074 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/36.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/36.kmac_error.3804143974
Short name	T482
Test name
Test status
Simulation time	34082021752 ps
CPU time	299.96 seconds
Started	Feb 04 02:52:59 PM PST 24
Finished	Feb 04 02:58:00 PM PST 24
Peak memory	259804 kb
Host	smart-e659fbd3-9c14-4a5d-b98c-56c3ce45a1fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3804143974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.3804143974 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_error/latest

Test location	/workspace/coverage/default/36.kmac_key_error.3890401960
Short name	T46
Test name
Test status
Simulation time	86481800 ps
CPU time	1.22 seconds
Started	Feb 04 02:52:56 PM PST 24
Finished	Feb 04 02:53:01 PM PST 24
Peak memory	218428 kb
Host	smart-469f3eef-f2e9-488d-8b6b-2d78fa31525f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3890401960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.3890401960 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_key_error/latest

Test location	/workspace/coverage/default/36.kmac_lc_escalation.66415980
Short name	T850
Test name
Test status
Simulation time	224832620 ps
CPU time	3 seconds
Started	Feb 04 02:52:58 PM PST 24
Finished	Feb 04 02:53:03 PM PST 24
Peak memory	222580 kb
Host	smart-d195dc1e-1aaf-4949-ac09-610d302ed9e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66415980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.66415980 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/36.kmac_long_msg_and_output.4145577652
Short name	T721
Test name
Test status
Simulation time	32011765399 ps
CPU time	859.4 seconds
Started	Feb 04 02:52:48 PM PST 24
Finished	Feb 04 03:07:10 PM PST 24
Peak memory	282836 kb
Host	smart-afda7327-3736-434b-954e-a83f2b04ab61
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145577652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a nd_output.4145577652 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/36.kmac_sideload.3274009655
Short name	T1016
Test name
Test status
Simulation time	6753565177 ps
CPU time	172.93 seconds
Started	Feb 04 02:52:43 PM PST 24
Finished	Feb 04 02:55:37 PM PST 24
Peak memory	238852 kb
Host	smart-3f5419a6-d46a-4e20-8036-9cca712e154e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3274009655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.3274009655 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_sideload/latest

Test location	/workspace/coverage/default/36.kmac_smoke.1379371524
Short name	T1087
Test name
Test status
Simulation time	1675446247 ps
CPU time	11.46 seconds
Started	Feb 04 02:52:52 PM PST 24
Finished	Feb 04 02:53:04 PM PST 24
Peak memory	227004 kb
Host	smart-3120a95a-a695-4bd8-aca3-33a5f78cba42
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1379371524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.1379371524 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_smoke/latest

Test location	/workspace/coverage/default/36.kmac_stress_all.1939542379
Short name	T297
Test name
Test status
Simulation time	16890253873 ps
CPU time	1541.9 seconds
Started	Feb 04 02:53:00 PM PST 24
Finished	Feb 04 03:18:43 PM PST 24
Peak memory	375248 kb
Host	smart-55a6136d-d5e8-463c-a697-05a0f823d95b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1939542379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.1939542379 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_stress_all/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_kmac.3059459480
Short name	T589
Test name
Test status
Simulation time	163306293 ps
CPU time	6.15 seconds
Started	Feb 04 02:52:57 PM PST 24
Finished	Feb 04 02:53:06 PM PST 24
Peak memory	218908 kb
Host	smart-34b60414-1df2-4a53-abe4-e11cf594022f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059459480 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 36.kmac_test_vectors_kmac.3059459480 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_kmac_xof.2644689045
Short name	T659
Test name
Test status
Simulation time	113953753 ps
CPU time	6.8 seconds
Started	Feb 04 02:52:56 PM PST 24
Finished	Feb 04 02:53:06 PM PST 24
Peak memory	220096 kb
Host	smart-d6a25bb3-67d2-4c87-b3e0-612d3efeea4c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644689045 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_kmac_xof.2644689045 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_224.1653632573
Short name	T1111
Test name
Test status
Simulation time	37178106287 ps
CPU time	1867.3 seconds
Started	Feb 04 02:52:50 PM PST 24
Finished	Feb 04 03:24:00 PM PST 24
Peak memory	396644 kb
Host	smart-05c08469-ab4c-4094-acac-7b6c8514dab7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1653632573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.1653632573 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_256.3885202172
Short name	T567
Test name
Test status
Simulation time	19281761608 ps
CPU time	1939.83 seconds
Started	Feb 04 02:52:42 PM PST 24
Finished	Feb 04 03:25:04 PM PST 24
Peak memory	383184 kb
Host	smart-afd5ba83-e19e-45d8-a136-3859fd201ce1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3885202172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.3885202172 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_384.1880697734
Short name	T226
Test name
Test status
Simulation time	191641489220 ps
CPU time	1890.8 seconds
Started	Feb 04 02:52:59 PM PST 24
Finished	Feb 04 03:24:31 PM PST 24
Peak memory	343856 kb
Host	smart-2bb35e52-b56a-48e5-bc0a-4aeb036fd4ce
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1880697734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.1880697734 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_512.2029680540
Short name	T229
Test name
Test status
Simulation time	10882357424 ps
CPU time	1186.34 seconds
Started	Feb 04 02:52:50 PM PST 24
Finished	Feb 04 03:12:39 PM PST 24
Peak memory	302376 kb
Host	smart-63166a91-21b5-46dc-9d8e-fef0c79d7080
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2029680540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.2029680540 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_shake_128.3207950695
Short name	T738
Test name
Test status
Simulation time	231869240301 ps
CPU time	5584.21 seconds
Started	Feb 04 02:52:49 PM PST 24
Finished	Feb 04 04:25:56 PM PST 24
Peak memory	668352 kb
Host	smart-f1a4f0b9-58e4-4991-887d-c2dd96868fbe
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3207950695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.3207950695 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_shake_256.1933159930
Short name	T460
Test name
Test status
Simulation time	62423254717 ps
CPU time	4629.86 seconds
Started	Feb 04 02:52:57 PM PST 24
Finished	Feb 04 04:10:10 PM PST 24
Peak memory	577124 kb
Host	smart-0099861e-50c8-44b6-bb3d-f87877c250e3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1933159930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.1933159930 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/37.kmac_alert_test.3500784800
Short name	T979
Test name
Test status
Simulation time	15760751 ps
CPU time	0.86 seconds
Started	Feb 04 02:53:44 PM PST 24
Finished	Feb 04 02:53:45 PM PST 24
Peak memory	219496 kb
Host	smart-57584bdb-4af5-4418-bb18-db9f55bf6486
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500784800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.3500784800 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_alert_test/latest

Test location	/workspace/coverage/default/37.kmac_app.1142389270
Short name	T136
Test name
Test status
Simulation time	42665253932 ps
CPU time	263.75 seconds
Started	Feb 04 02:53:22 PM PST 24
Finished	Feb 04 02:57:48 PM PST 24
Peak memory	247852 kb
Host	smart-cb70ab24-20c4-4ec3-953e-4d7e949375d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1142389270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.1142389270 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_app/latest

Test location	/workspace/coverage/default/37.kmac_burst_write.1835072329
Short name	T489
Test name
Test status
Simulation time	2383247504 ps
CPU time	86.3 seconds
Started	Feb 04 02:53:09 PM PST 24
Finished	Feb 04 02:54:36 PM PST 24
Peak memory	227236 kb
Host	smart-811ff594-adb9-40fe-924a-aca9b7d106e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1835072329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.1835072329 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_burst_write/latest

Test location	/workspace/coverage/default/37.kmac_entropy_refresh.25782694
Short name	T430
Test name
Test status
Simulation time	59541739657 ps
CPU time	220.54 seconds
Started	Feb 04 02:53:25 PM PST 24
Finished	Feb 04 02:57:09 PM PST 24
Peak memory	242768 kb
Host	smart-217b5cfe-5553-4188-8218-2986aecc6b97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=25782694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.25782694 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/37.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/37.kmac_error.3706729339
Short name	T900
Test name
Test status
Simulation time	5916396533 ps
CPU time	389.94 seconds
Started	Feb 04 02:53:31 PM PST 24
Finished	Feb 04 03:00:05 PM PST 24
Peak memory	256848 kb
Host	smart-76e3aba1-b45b-4a20-8eb4-d20b09a73cc6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3706729339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.3706729339 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_error/latest

Test location	/workspace/coverage/default/37.kmac_key_error.2048396835
Short name	T432
Test name
Test status
Simulation time	2704050456 ps
CPU time	4.31 seconds
Started	Feb 04 02:53:29 PM PST 24
Finished	Feb 04 02:53:38 PM PST 24
Peak memory	218700 kb
Host	smart-816d31eb-43cd-4f16-be28-e6d91be07c9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2048396835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.2048396835 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_key_error/latest

Test location	/workspace/coverage/default/37.kmac_lc_escalation.2754063803
Short name	T723
Test name
Test status
Simulation time	139479230 ps
CPU time	1.41 seconds
Started	Feb 04 02:53:25 PM PST 24
Finished	Feb 04 02:53:29 PM PST 24
Peak memory	219756 kb
Host	smart-4347f287-222e-4db8-bbb1-12b4c8516f38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2754063803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.2754063803 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/37.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/37.kmac_long_msg_and_output.1056821825
Short name	T694
Test name
Test status
Simulation time	341217282881 ps
CPU time	844.75 seconds
Started	Feb 04 02:53:10 PM PST 24
Finished	Feb 04 03:07:15 PM PST 24
Peak memory	280120 kb
Host	smart-2556aec2-d17f-43bb-b8e2-782b1a24c822
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056821825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a nd_output.1056821825 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/37.kmac_sideload.3074978296
Short name	T860
Test name
Test status
Simulation time	18476969799 ps
CPU time	345.01 seconds
Started	Feb 04 02:53:10 PM PST 24
Finished	Feb 04 02:58:56 PM PST 24
Peak memory	251720 kb
Host	smart-e15c245e-3668-4be1-a40f-f55eddde68c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3074978296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.3074978296 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_sideload/latest

Test location	/workspace/coverage/default/37.kmac_smoke.3005877167
Short name	T719
Test name
Test status
Simulation time	771881362 ps
CPU time	29.88 seconds
Started	Feb 04 02:53:14 PM PST 24
Finished	Feb 04 02:53:47 PM PST 24
Peak memory	226900 kb
Host	smart-7413e2a1-9862-4c8f-ba1d-4564665d7965
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3005877167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.3005877167 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_smoke/latest

Test location	/workspace/coverage/default/37.kmac_stress_all.280688546
Short name	T341
Test name
Test status
Simulation time	13464158402 ps
CPU time	266.19 seconds
Started	Feb 04 02:53:25 PM PST 24
Finished	Feb 04 02:57:55 PM PST 24
Peak memory	282472 kb
Host	smart-997c90a7-77dd-4507-b348-c4c20b7add66
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=280688546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.280688546 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_stress_all/latest

Test location	/workspace/coverage/default/37.kmac_stress_all_with_rand_reset.2720657099
Short name	T912
Test name
Test status
Simulation time	64977315223 ps
CPU time	1891.92 seconds
Started	Feb 04 02:53:44 PM PST 24
Finished	Feb 04 03:25:17 PM PST 24
Peak memory	374208 kb
Host	smart-a6b83b29-b6b4-4341-bd5c-20003a1e8d21
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2720657099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all_with_rand_reset.2720657099 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_kmac.2061330700
Short name	T789
Test name
Test status
Simulation time	472588221 ps
CPU time	6.58 seconds
Started	Feb 04 02:53:25 PM PST 24
Finished	Feb 04 02:53:35 PM PST 24
Peak memory	218752 kb
Host	smart-16a67d1a-f269-4e44-8c3c-ee83ca70cfc1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061330700 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 37.kmac_test_vectors_kmac.2061330700 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_kmac_xof.2967161604
Short name	T833
Test name
Test status
Simulation time	220552641 ps
CPU time	6.82 seconds
Started	Feb 04 02:53:25 PM PST 24
Finished	Feb 04 02:53:34 PM PST 24
Peak memory	218924 kb
Host	smart-7fe4251e-930a-45a6-9e82-968d2dbb55b9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967161604 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_kmac_xof.2967161604 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_224.2457012540
Short name	T967
Test name
Test status
Simulation time	96930855919 ps
CPU time	2231.63 seconds
Started	Feb 04 02:53:08 PM PST 24
Finished	Feb 04 03:30:21 PM PST 24
Peak memory	394812 kb
Host	smart-baa442da-4971-44bd-8501-183f7a5d6679
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2457012540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.2457012540 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_256.4023867715
Short name	T932
Test name
Test status
Simulation time	63471010373 ps
CPU time	2344.78 seconds
Started	Feb 04 02:53:15 PM PST 24
Finished	Feb 04 03:32:22 PM PST 24
Peak memory	392500 kb
Host	smart-cb91417e-4970-4c45-a7d0-5a9a0c9d62f0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4023867715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.4023867715 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_384.650306186
Short name	T243
Test name
Test status
Simulation time	148112030468 ps
CPU time	1862.14 seconds
Started	Feb 04 02:53:09 PM PST 24
Finished	Feb 04 03:24:13 PM PST 24
Peak memory	343068 kb
Host	smart-10c0ceb9-e8d2-46f5-b517-b20209328374
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=650306186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.650306186 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_512.4014438948
Short name	T919
Test name
Test status
Simulation time	45557921028 ps
CPU time	999.87 seconds
Started	Feb 04 02:53:15 PM PST 24
Finished	Feb 04 03:09:57 PM PST 24
Peak memory	298988 kb
Host	smart-e311a812-504b-456c-81f6-ba7884ffae54
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4014438948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.4014438948 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_shake_128.1613654866
Short name	T674
Test name
Test status
Simulation time	542097811274 ps
CPU time	6398.91 seconds
Started	Feb 04 02:53:15 PM PST 24
Finished	Feb 04 04:39:57 PM PST 24
Peak memory	665280 kb
Host	smart-28c93e3c-3ede-448b-bea1-1da0e1b44701
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1613654866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.1613654866 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_shake_256.585691263
Short name	T737
Test name
Test status
Simulation time	222267697135 ps
CPU time	5033.04 seconds
Started	Feb 04 02:53:22 PM PST 24
Finished	Feb 04 04:17:18 PM PST 24
Peak memory	565432 kb
Host	smart-c7c5af5e-5e69-4ed9-87a8-db16bfc75e48
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=585691263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.585691263 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/38.kmac_alert_test.2587678301
Short name	T774
Test name
Test status
Simulation time	24109808 ps
CPU time	0.86 seconds
Started	Feb 04 02:54:00 PM PST 24
Finished	Feb 04 02:54:02 PM PST 24
Peak memory	218276 kb
Host	smart-af5cfad7-4aa6-483d-a58f-33c13b8103de
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587678301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.2587678301 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_alert_test/latest

Test location	/workspace/coverage/default/38.kmac_app.3383027262
Short name	T313
Test name
Test status
Simulation time	3019525270 ps
CPU time	81.74 seconds
Started	Feb 04 02:53:56 PM PST 24
Finished	Feb 04 02:55:23 PM PST 24
Peak memory	231772 kb
Host	smart-2848c1e4-ade7-4e47-a9a5-57953de30a29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3383027262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.3383027262 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_app/latest

Test location	/workspace/coverage/default/38.kmac_burst_write.939416256
Short name	T342
Test name
Test status
Simulation time	18501822609 ps
CPU time	756.38 seconds
Started	Feb 04 02:53:44 PM PST 24
Finished	Feb 04 03:06:21 PM PST 24
Peak memory	243320 kb
Host	smart-2a7c48a8-44ba-4710-b525-2af991c16b9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=939416256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.939416256 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_burst_write/latest

Test location	/workspace/coverage/default/38.kmac_entropy_refresh.1122150356
Short name	T388
Test name
Test status
Simulation time	8566633680 ps
CPU time	392.41 seconds
Started	Feb 04 02:53:57 PM PST 24
Finished	Feb 04 03:00:34 PM PST 24
Peak memory	254060 kb
Host	smart-41eca9a9-76b7-4338-a05a-450f77bfbab2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1122150356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.1122150356 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/38.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/38.kmac_error.2104790649
Short name	T257
Test name
Test status
Simulation time	3734471344 ps
CPU time	213.85 seconds
Started	Feb 04 02:53:58 PM PST 24
Finished	Feb 04 02:57:35 PM PST 24
Peak memory	259840 kb
Host	smart-1eb2b677-18a2-48ad-bc0b-d71c8775ef46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2104790649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.2104790649 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_error/latest

Test location	/workspace/coverage/default/38.kmac_key_error.1160943521
Short name	T617
Test name
Test status
Simulation time	570507351 ps
CPU time	3.72 seconds
Started	Feb 04 02:53:57 PM PST 24
Finished	Feb 04 02:54:05 PM PST 24
Peak memory	218668 kb
Host	smart-eb4175c3-ecb8-40b3-92d8-7bef4b680ee5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1160943521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.1160943521 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_key_error/latest

Test location	/workspace/coverage/default/38.kmac_lc_escalation.2012377745
Short name	T585
Test name
Test status
Simulation time	30155719 ps
CPU time	1.36 seconds
Started	Feb 04 02:53:58 PM PST 24
Finished	Feb 04 02:54:03 PM PST 24
Peak memory	219716 kb
Host	smart-f21a04cb-7c47-4f0a-b920-dfbd03694b0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2012377745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.2012377745 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/38.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/38.kmac_long_msg_and_output.1189788764
Short name	T654
Test name
Test status
Simulation time	142799120140 ps
CPU time	1786.9 seconds
Started	Feb 04 02:53:43 PM PST 24
Finished	Feb 04 03:23:31 PM PST 24
Peak memory	360896 kb
Host	smart-37b682ce-6234-4b58-9f8c-4136860c5458
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189788764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a nd_output.1189788764 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/38.kmac_sideload.4848006
Short name	T832
Test name
Test status
Simulation time	61900339346 ps
CPU time	412.04 seconds
Started	Feb 04 02:53:45 PM PST 24
Finished	Feb 04 03:00:38 PM PST 24
Peak memory	253152 kb
Host	smart-fdba25e9-e9c1-472c-b570-1118e95edd13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4848006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.4848006 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_sideload/latest

Test location	/workspace/coverage/default/38.kmac_smoke.4259322565
Short name	T338
Test name
Test status
Simulation time	1439653693 ps
CPU time	60.97 seconds
Started	Feb 04 02:53:44 PM PST 24
Finished	Feb 04 02:54:46 PM PST 24
Peak memory	226896 kb
Host	smart-c83c504c-fb75-443f-9f0c-0f495eadf406
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4259322565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.4259322565 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_smoke/latest

Test location	/workspace/coverage/default/38.kmac_stress_all.1551159430
Short name	T323
Test name
Test status
Simulation time	7433318630 ps
CPU time	206.08 seconds
Started	Feb 04 02:54:00 PM PST 24
Finished	Feb 04 02:57:28 PM PST 24
Peak memory	243472 kb
Host	smart-ec5fe092-5635-4669-8829-a28757f302ec
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1551159430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.1551159430 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_stress_all/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_kmac.387822808
Short name	T299
Test name
Test status
Simulation time	117425873 ps
CPU time	5.89 seconds
Started	Feb 04 02:53:56 PM PST 24
Finished	Feb 04 02:54:07 PM PST 24
Peak memory	220396 kb
Host	smart-2709cc14-b96f-47f5-abbe-4748d26cf4db
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387822808 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 38.kmac_test_vectors_kmac.387822808 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_kmac_xof.1890455738
Short name	T224
Test name
Test status
Simulation time	1398273257 ps
CPU time	6.32 seconds
Started	Feb 04 02:53:56 PM PST 24
Finished	Feb 04 02:54:08 PM PST 24
Peak memory	218908 kb
Host	smart-3ba7e02a-33d9-4762-b1a6-79cc590cbd48
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890455738 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_kmac_xof.1890455738 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_224.2762825750
Short name	T728
Test name
Test status
Simulation time	896766438832 ps
CPU time	2694.84 seconds
Started	Feb 04 02:53:57 PM PST 24
Finished	Feb 04 03:38:57 PM PST 24
Peak memory	404444 kb
Host	smart-aa9bd2a2-e6ab-4c0f-845f-fa2a78890bfa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2762825750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.2762825750 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_256.1778812907
Short name	T868
Test name
Test status
Simulation time	328992885755 ps
CPU time	2351.91 seconds
Started	Feb 04 02:53:57 PM PST 24
Finished	Feb 04 03:33:14 PM PST 24
Peak memory	400500 kb
Host	smart-aec279ab-7b1f-4d39-a477-1e059e5c5385
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1778812907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.1778812907 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_384.1962976138
Short name	T640
Test name
Test status
Simulation time	147775707379 ps
CPU time	2000.73 seconds
Started	Feb 04 02:53:58 PM PST 24
Finished	Feb 04 03:27:22 PM PST 24
Peak memory	344256 kb
Host	smart-717141c6-c3b7-4e09-88d0-ef35601e8a9d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1962976138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.1962976138 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_512.3402528478
Short name	T454
Test name
Test status
Simulation time	12023541431 ps
CPU time	1079.83 seconds
Started	Feb 04 02:53:55 PM PST 24
Finished	Feb 04 03:12:00 PM PST 24
Peak memory	297720 kb
Host	smart-7ffee47d-cac7-4713-afd6-d1eeafd9e489
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3402528478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.3402528478 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_shake_128.1756283779
Short name	T532
Test name
Test status
Simulation time	65534786710 ps
CPU time	5455.21 seconds
Started	Feb 04 02:53:56 PM PST 24
Finished	Feb 04 04:24:57 PM PST 24
Peak memory	654360 kb
Host	smart-15066d97-0669-4aea-add4-b2abfa1396ab
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1756283779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.1756283779 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_shake_256.1453568193
Short name	T632
Test name
Test status
Simulation time	222776189547 ps
CPU time	5486.62 seconds
Started	Feb 04 02:53:55 PM PST 24
Finished	Feb 04 04:25:23 PM PST 24
Peak memory	571256 kb
Host	smart-2b343bf8-eb3a-4e5e-9b9e-a059e534be04
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1453568193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.1453568193 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/39.kmac_alert_test.3903634135
Short name	T314
Test name
Test status
Simulation time	12369945 ps
CPU time	0.84 seconds
Started	Feb 04 02:54:32 PM PST 24
Finished	Feb 04 02:54:37 PM PST 24
Peak memory	219584 kb
Host	smart-51b2926c-8d56-4076-b329-efdae9fb0ebb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903634135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.3903634135 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_alert_test/latest

Test location	/workspace/coverage/default/39.kmac_app.724493582
Short name	T757
Test name
Test status
Simulation time	944441670 ps
CPU time	11.55 seconds
Started	Feb 04 02:54:31 PM PST 24
Finished	Feb 04 02:54:48 PM PST 24
Peak memory	220892 kb
Host	smart-abf867c5-550e-46bc-80e2-7993057e3527
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=724493582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.724493582 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_app/latest

Test location	/workspace/coverage/default/39.kmac_burst_write.1461128049
Short name	T392
Test name
Test status
Simulation time	27621098088 ps
CPU time	642.36 seconds
Started	Feb 04 02:54:27 PM PST 24
Finished	Feb 04 03:05:11 PM PST 24
Peak memory	235852 kb
Host	smart-aad36fc9-67a6-4632-9fa6-6c358ebca87d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1461128049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.1461128049 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_burst_write/latest

Test location	/workspace/coverage/default/39.kmac_entropy_refresh.1581244291
Short name	T494
Test name
Test status
Simulation time	16976647395 ps
CPU time	383.85 seconds
Started	Feb 04 02:54:28 PM PST 24
Finished	Feb 04 03:00:54 PM PST 24
Peak memory	255068 kb
Host	smart-af4d8f43-dc12-49de-b31d-c467d53ece05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1581244291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.1581244291 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/39.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/39.kmac_error.2553021278
Short name	T359
Test name
Test status
Simulation time	15625345708 ps
CPU time	524.95 seconds
Started	Feb 04 02:54:27 PM PST 24
Finished	Feb 04 03:03:13 PM PST 24
Peak memory	269300 kb
Host	smart-05ee1f22-d7db-4aca-9f35-d26b8547358a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2553021278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.2553021278 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_error/latest

Test location	/workspace/coverage/default/39.kmac_key_error.3393769662
Short name	T330
Test name
Test status
Simulation time	32446681 ps
CPU time	0.99 seconds
Started	Feb 04 02:54:29 PM PST 24
Finished	Feb 04 02:54:36 PM PST 24
Peak memory	218308 kb
Host	smart-efbfdfc3-3bc2-4055-a73c-5b4ef375a44d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3393769662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.3393769662 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_key_error/latest

Test location	/workspace/coverage/default/39.kmac_lc_escalation.1653374130
Short name	T793
Test name
Test status
Simulation time	91581334 ps
CPU time	1.42 seconds
Started	Feb 04 02:54:32 PM PST 24
Finished	Feb 04 02:54:38 PM PST 24
Peak memory	219736 kb
Host	smart-2cc063e3-b02f-4d37-8034-1f99cbac6e1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1653374130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.1653374130 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/39.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/39.kmac_long_msg_and_output.2490178785
Short name	T1034
Test name
Test status
Simulation time	22366395621 ps
CPU time	165.51 seconds
Started	Feb 04 02:54:31 PM PST 24
Finished	Feb 04 02:57:21 PM PST 24
Peak memory	243436 kb
Host	smart-1c8c504c-cde9-47a9-b6a0-01c382bf9567
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490178785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a nd_output.2490178785 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/39.kmac_sideload.2435433468
Short name	T1012
Test name
Test status
Simulation time	15150460519 ps
CPU time	458.56 seconds
Started	Feb 04 02:54:30 PM PST 24
Finished	Feb 04 03:02:14 PM PST 24
Peak memory	255252 kb
Host	smart-7165ca9d-1b36-4a72-a82c-4f8cb1e80277
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2435433468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.2435433468 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_sideload/latest

Test location	/workspace/coverage/default/39.kmac_smoke.4292466378
Short name	T308
Test name
Test status
Simulation time	1515269664 ps
CPU time	37.13 seconds
Started	Feb 04 02:54:20 PM PST 24
Finished	Feb 04 02:54:59 PM PST 24
Peak memory	224852 kb
Host	smart-f4326e92-7b9e-4bd8-a35f-b70b7e65930d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4292466378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.4292466378 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_smoke/latest

Test location	/workspace/coverage/default/39.kmac_stress_all.1469701709
Short name	T15
Test name
Test status
Simulation time	27733732469 ps
CPU time	1170.74 seconds
Started	Feb 04 02:54:37 PM PST 24
Finished	Feb 04 03:14:08 PM PST 24
Peak memory	317492 kb
Host	smart-f0b039e9-3084-486f-ba0c-7c0f3d95e086
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1469701709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.1469701709 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_stress_all/latest

Test location	/workspace/coverage/default/39.kmac_stress_all_with_rand_reset.3036838260
Short name	T418
Test name
Test status
Simulation time	62555962203 ps
CPU time	985.21 seconds
Started	Feb 04 02:54:37 PM PST 24
Finished	Feb 04 03:11:03 PM PST 24
Peak memory	287900 kb
Host	smart-0ae0cd29-e6cc-4207-8d9c-c737e8d51387
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3036838260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all_with_rand_reset.3036838260 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_kmac.4277744279
Short name	T1082
Test name
Test status
Simulation time	1202464671 ps
CPU time	6.73 seconds
Started	Feb 04 02:54:31 PM PST 24
Finished	Feb 04 02:54:43 PM PST 24
Peak memory	218936 kb
Host	smart-d0077e12-d03f-4a83-bf43-ac2d8240d433
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277744279 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 39.kmac_test_vectors_kmac.4277744279 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_kmac_xof.1977744709
Short name	T233
Test name
Test status
Simulation time	241760016 ps
CPU time	6.73 seconds
Started	Feb 04 02:54:30 PM PST 24
Finished	Feb 04 02:54:42 PM PST 24
Peak memory	218896 kb
Host	smart-61b9f281-254d-48e7-87d1-9b74a0ef016b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977744709 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_kmac_xof.1977744709 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_224.1856303678
Short name	T1037
Test name
Test status
Simulation time	66955758562 ps
CPU time	2481.84 seconds
Started	Feb 04 02:54:28 PM PST 24
Finished	Feb 04 03:35:52 PM PST 24
Peak memory	403660 kb
Host	smart-f139bdb5-296f-40f2-a217-b3d2ead52e06
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1856303678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.1856303678 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_256.1501819976
Short name	T594
Test name
Test status
Simulation time	77197377837 ps
CPU time	1897.06 seconds
Started	Feb 04 02:54:31 PM PST 24
Finished	Feb 04 03:26:13 PM PST 24
Peak memory	390084 kb
Host	smart-ce613aaf-81c7-4c5b-b936-7b3a6de65c2e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1501819976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.1501819976 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_384.2504261223
Short name	T520
Test name
Test status
Simulation time	61667118759 ps
CPU time	1860.83 seconds
Started	Feb 04 02:54:28 PM PST 24
Finished	Feb 04 03:25:31 PM PST 24
Peak memory	341084 kb
Host	smart-4946fbd0-043a-461c-bbc5-d6d9dab3c60f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2504261223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.2504261223 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_512.1989991543
Short name	T928
Test name
Test status
Simulation time	38323880128 ps
CPU time	1449.52 seconds
Started	Feb 04 02:54:25 PM PST 24
Finished	Feb 04 03:18:38 PM PST 24
Peak memory	304360 kb
Host	smart-080d8947-b790-45c2-b943-d7835e3f3f4a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1989991543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.1989991543 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_shake_128.846172343
Short name	T234
Test name
Test status
Simulation time	262144879649 ps
CPU time	6486.73 seconds
Started	Feb 04 02:54:31 PM PST 24
Finished	Feb 04 04:42:43 PM PST 24
Peak memory	637472 kb
Host	smart-dda6aa14-fcde-41ec-96be-a9cae5ff25fc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=846172343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.846172343 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_shake_256.1265461000
Short name	T686
Test name
Test status
Simulation time	904369963554 ps
CPU time	5764.85 seconds
Started	Feb 04 02:54:29 PM PST 24
Finished	Feb 04 04:30:41 PM PST 24
Peak memory	564376 kb
Host	smart-3fb1f071-17f9-4ecf-8ed0-1758e1a3bf0c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1265461000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.1265461000 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/4.kmac_alert_test.2156838634
Short name	T1017
Test name
Test status
Simulation time	57565803 ps
CPU time	0.91 seconds
Started	Feb 04 02:45:07 PM PST 24
Finished	Feb 04 02:45:28 PM PST 24
Peak memory	219516 kb
Host	smart-4ab0d9c6-3ab1-4f3f-b21a-1494556a0bda
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156838634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.2156838634 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_alert_test/latest

Test location	/workspace/coverage/default/4.kmac_app.2249631054
Short name	T1051
Test name
Test status
Simulation time	8726315060 ps
CPU time	288.84 seconds
Started	Feb 04 02:45:04 PM PST 24
Finished	Feb 04 02:50:15 PM PST 24
Peak memory	244964 kb
Host	smart-3650913a-cb7e-43f5-b2bb-56a30194c93d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2249631054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.2249631054 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_app/latest

Test location	/workspace/coverage/default/4.kmac_app_with_partial_data.2579776867
Short name	T703
Test name
Test status
Simulation time	82800099588 ps
CPU time	487.05 seconds
Started	Feb 04 02:44:59 PM PST 24
Finished	Feb 04 02:53:30 PM PST 24
Peak memory	255188 kb
Host	smart-d837c65f-d144-4e96-9d95-b8693ade7b23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2579776867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.2579776867 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/4.kmac_burst_write.1996740420
Short name	T1121
Test name
Test status
Simulation time	21869046692 ps
CPU time	1203.32 seconds
Started	Feb 04 02:44:59 PM PST 24
Finished	Feb 04 03:05:27 PM PST 24
Peak memory	243320 kb
Host	smart-82d032c4-3323-4b48-a890-5f416222f62e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1996740420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.1996740420 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_burst_write/latest

Test location	/workspace/coverage/default/4.kmac_edn_timeout_error.3722500266
Short name	T945
Test name
Test status
Simulation time	2429174305 ps
CPU time	44.25 seconds
Started	Feb 04 02:45:04 PM PST 24
Finished	Feb 04 02:46:10 PM PST 24
Peak memory	236656 kb
Host	smart-f3135402-8860-490c-91a1-e24c461605ba
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3722500266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.3722500266 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/4.kmac_entropy_mode_error.1968520068
Short name	T86
Test name
Test status
Simulation time	64541096 ps
CPU time	1.17 seconds
Started	Feb 04 02:45:13 PM PST 24
Finished	Feb 04 02:45:31 PM PST 24
Peak memory	218612 kb
Host	smart-73b4771e-b25b-41a9-bc0c-ad5f179e6b8d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1968520068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.1968520068 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/4.kmac_entropy_ready_error.4028107933
Short name	T457
Test name
Test status
Simulation time	32378590818 ps
CPU time	88.42 seconds
Started	Feb 04 02:45:02 PM PST 24
Finished	Feb 04 02:46:53 PM PST 24
Peak memory	227032 kb
Host	smart-30f1f7e1-6bed-41b7-9664-a2db8d7806f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4028107933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.4028107933 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/4.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/4.kmac_entropy_refresh.1596617702
Short name	T910
Test name
Test status
Simulation time	1918165051 ps
CPU time	44.58 seconds
Started	Feb 04 02:45:00 PM PST 24
Finished	Feb 04 02:46:08 PM PST 24
Peak memory	227288 kb
Host	smart-440cdd53-cd6c-4a72-94d9-c42287d2a7b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1596617702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.1596617702 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/4.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/4.kmac_error.228463206
Short name	T281
Test name
Test status
Simulation time	17124960145 ps
CPU time	154.38 seconds
Started	Feb 04 02:44:56 PM PST 24
Finished	Feb 04 02:47:51 PM PST 24
Peak memory	251396 kb
Host	smart-2a6587ef-41f2-4138-8837-24237e607d24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=228463206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.228463206 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_error/latest

Test location	/workspace/coverage/default/4.kmac_key_error.724540307
Short name	T103
Test name
Test status
Simulation time	648814287 ps
CPU time	4.19 seconds
Started	Feb 04 02:45:00 PM PST 24
Finished	Feb 04 02:45:27 PM PST 24
Peak memory	218616 kb
Host	smart-3ce50bc4-fb0f-401a-9981-6bbd906e61a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=724540307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.724540307 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_key_error/latest

Test location	/workspace/coverage/default/4.kmac_lc_escalation.4109742230
Short name	T279
Test name
Test status
Simulation time	326824415 ps
CPU time	1.4 seconds
Started	Feb 04 02:45:09 PM PST 24
Finished	Feb 04 02:45:31 PM PST 24
Peak memory	219812 kb
Host	smart-d719620e-f977-4e0d-b96e-84105bf8d7ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4109742230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.4109742230 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/4.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/4.kmac_long_msg_and_output.2780265394
Short name	T537
Test name
Test status
Simulation time	263651220626 ps
CPU time	2457.89 seconds
Started	Feb 04 02:45:04 PM PST 24
Finished	Feb 04 03:26:25 PM PST 24
Peak memory	401328 kb
Host	smart-788b9ad7-a124-4ddc-ac01-dafb30142489
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780265394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an d_output.2780265394 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/4.kmac_mubi.1246481528
Short name	T558
Test name
Test status
Simulation time	32877553076 ps
CPU time	196.11 seconds
Started	Feb 04 02:45:03 PM PST 24
Finished	Feb 04 02:48:42 PM PST 24
Peak memory	241064 kb
Host	smart-be6b236e-2df4-460e-808b-de6bb5273264
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1246481528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.1246481528 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_mubi/latest

Test location	/workspace/coverage/default/4.kmac_sec_cm.3033487220
Short name	T7
Test name
Test status
Simulation time	4896949793 ps
CPU time	82.12 seconds
Started	Feb 04 02:45:20 PM PST 24
Finished	Feb 04 02:46:54 PM PST 24
Peak memory	276344 kb
Host	smart-59d0ade5-c937-48ed-8683-ae09ea9c9197
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033487220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.3033487220 +enable_maski ng=1 +sw_key_masked=0
Directory	/workspace/4.kmac_sec_cm/latest

Test location	/workspace/coverage/default/4.kmac_sideload.3069801245
Short name	T360
Test name
Test status
Simulation time	10710576749 ps
CPU time	342.38 seconds
Started	Feb 04 02:45:00 PM PST 24
Finished	Feb 04 02:51:06 PM PST 24
Peak memory	250316 kb
Host	smart-bdf39468-45fe-438d-859c-1c5d0c14ba00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3069801245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.3069801245 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_sideload/latest

Test location	/workspace/coverage/default/4.kmac_smoke.3427471141
Short name	T503
Test name
Test status
Simulation time	3808828251 ps
CPU time	75.38 seconds
Started	Feb 04 02:45:13 PM PST 24
Finished	Feb 04 02:46:46 PM PST 24
Peak memory	227064 kb
Host	smart-ed1aca72-24e8-485f-8045-4d495401a365
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3427471141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.3427471141 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_smoke/latest

Test location	/workspace/coverage/default/4.kmac_stress_all.2526451822
Short name	T970
Test name
Test status
Simulation time	194069563279 ps
CPU time	2065.61 seconds
Started	Feb 04 02:45:10 PM PST 24
Finished	Feb 04 03:19:55 PM PST 24
Peak memory	418576 kb
Host	smart-85b77dad-c544-4f1e-867d-a6714a70b6b7
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2526451822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.2526451822 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_stress_all/latest

Test location	/workspace/coverage/default/4.kmac_stress_all_with_rand_reset.116634027
Short name	T976
Test name
Test status
Simulation time	41255875631 ps
CPU time	704.13 seconds
Started	Feb 04 02:45:10 PM PST 24
Finished	Feb 04 02:57:14 PM PST 24
Peak memory	278740 kb
Host	smart-f84f3dfd-a4fc-40ee-86e3-5523c9405478
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=116634027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all_with_rand_reset.116634027 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_kmac.4223989515
Short name	T652
Test name
Test status
Simulation time	115247999 ps
CPU time	5.8 seconds
Started	Feb 04 02:45:04 PM PST 24
Finished	Feb 04 02:45:32 PM PST 24
Peak memory	218896 kb
Host	smart-151b8ec7-1df0-49ac-b71b-1a25c033e7ad
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223989515 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.kmac_test_vectors_kmac.4223989515 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_kmac_xof.2134841915
Short name	T620
Test name
Test status
Simulation time	668785967 ps
CPU time	6.27 seconds
Started	Feb 04 02:45:00 PM PST 24
Finished	Feb 04 02:45:30 PM PST 24
Peak memory	218848 kb
Host	smart-207b325b-c5b5-4e3a-bdc8-0423acddc37e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134841915 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.2134841915 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_224.2349593607
Short name	T178
Test name
Test status
Simulation time	182226305952 ps
CPU time	2025.19 seconds
Started	Feb 04 02:45:03 PM PST 24
Finished	Feb 04 03:19:11 PM PST 24
Peak memory	391776 kb
Host	smart-6e60988a-d3b2-4542-827d-eed321a256c0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2349593607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.2349593607 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_256.961782071
Short name	T325
Test name
Test status
Simulation time	121070635647 ps
CPU time	2116 seconds
Started	Feb 04 02:45:13 PM PST 24
Finished	Feb 04 03:20:46 PM PST 24
Peak memory	389008 kb
Host	smart-0791f082-8e49-4fc2-b71e-d29adafe2c72
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=961782071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.961782071 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_384.3713467510
Short name	T196
Test name
Test status
Simulation time	35868519925 ps
CPU time	1467.27 seconds
Started	Feb 04 02:45:05 PM PST 24
Finished	Feb 04 03:09:54 PM PST 24
Peak memory	344012 kb
Host	smart-63bc55e9-c7e1-4b71-bca3-35048cf997d9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3713467510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.3713467510 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_512.285901893
Short name	T186
Test name
Test status
Simulation time	49647879221 ps
CPU time	1310.11 seconds
Started	Feb 04 02:45:05 PM PST 24
Finished	Feb 04 03:07:17 PM PST 24
Peak memory	296144 kb
Host	smart-629ecb27-bf8e-4e7f-acf3-357711d3a1b3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=285901893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.285901893 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_shake_128.1081150668
Short name	T625
Test name
Test status
Simulation time	614648226228 ps
CPU time	5885.64 seconds
Started	Feb 04 02:44:58 PM PST 24
Finished	Feb 04 04:23:29 PM PST 24
Peak memory	661556 kb
Host	smart-793e3087-e574-4410-8933-6c4ea04becc5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1081150668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.1081150668 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_shake_256.24454524
Short name	T836
Test name
Test status
Simulation time	148562097753 ps
CPU time	5225.86 seconds
Started	Feb 04 02:45:04 PM PST 24
Finished	Feb 04 04:12:33 PM PST 24
Peak memory	561256 kb
Host	smart-a0d4880e-f08f-4008-83ac-50f1d585b2e2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=24454524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.24454524 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/40.kmac_alert_test.731255554
Short name	T676
Test name
Test status
Simulation time	50720309 ps
CPU time	0.87 seconds
Started	Feb 04 02:55:09 PM PST 24
Finished	Feb 04 02:55:11 PM PST 24
Peak memory	219500 kb
Host	smart-2ab4f77c-2421-4b04-8662-f2ccccfe0d16
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731255554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.731255554 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_alert_test/latest

Test location	/workspace/coverage/default/40.kmac_app.1700103328
Short name	T808
Test name
Test status
Simulation time	20396132749 ps
CPU time	77.88 seconds
Started	Feb 04 02:54:53 PM PST 24
Finished	Feb 04 02:56:12 PM PST 24
Peak memory	241800 kb
Host	smart-1292be03-183f-4d21-b020-96a4bc40b9fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1700103328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.1700103328 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_app/latest

Test location	/workspace/coverage/default/40.kmac_burst_write.789824870
Short name	T197
Test name
Test status
Simulation time	107965598573 ps
CPU time	978 seconds
Started	Feb 04 02:54:39 PM PST 24
Finished	Feb 04 03:10:58 PM PST 24
Peak memory	236860 kb
Host	smart-80ab339b-00d0-479e-a384-a454a213f3e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=789824870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.789824870 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_burst_write/latest

Test location	/workspace/coverage/default/40.kmac_entropy_refresh.2743872548
Short name	T714
Test name
Test status
Simulation time	3322393338 ps
CPU time	59.07 seconds
Started	Feb 04 02:54:56 PM PST 24
Finished	Feb 04 02:55:58 PM PST 24
Peak memory	230440 kb
Host	smart-c0e38bb2-1a1b-4953-bc6c-236305804707
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2743872548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.2743872548 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/40.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/40.kmac_error.3795812216
Short name	T1088
Test name
Test status
Simulation time	34511400715 ps
CPU time	408.06 seconds
Started	Feb 04 02:54:52 PM PST 24
Finished	Feb 04 03:01:41 PM PST 24
Peak memory	259984 kb
Host	smart-aaf90590-b526-4536-a7f6-3a44d18d8e5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3795812216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.3795812216 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_error/latest

Test location	/workspace/coverage/default/40.kmac_key_error.2404857105
Short name	T1036
Test name
Test status
Simulation time	1998339114 ps
CPU time	3.91 seconds
Started	Feb 04 02:54:53 PM PST 24
Finished	Feb 04 02:54:58 PM PST 24
Peak memory	218676 kb
Host	smart-d382c421-b346-4aec-b957-ad4c19f7f89c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2404857105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.2404857105 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_key_error/latest

Test location	/workspace/coverage/default/40.kmac_lc_escalation.4247548256
Short name	T760
Test name
Test status
Simulation time	130628042 ps
CPU time	1.56 seconds
Started	Feb 04 02:55:08 PM PST 24
Finished	Feb 04 02:55:10 PM PST 24
Peak memory	219828 kb
Host	smart-4977101e-80cc-485f-a6a1-8cb04c907591
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4247548256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.4247548256 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/40.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/40.kmac_long_msg_and_output.4077502189
Short name	T854
Test name
Test status
Simulation time	38905446317 ps
CPU time	333.43 seconds
Started	Feb 04 02:54:37 PM PST 24
Finished	Feb 04 03:00:11 PM PST 24
Peak memory	251864 kb
Host	smart-cc3a8d8a-0119-417c-83a8-06c73bf2b747
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077502189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_a nd_output.4077502189 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/40.kmac_sideload.3566313502
Short name	T958
Test name
Test status
Simulation time	776171073 ps
CPU time	20.61 seconds
Started	Feb 04 02:54:37 PM PST 24
Finished	Feb 04 02:54:58 PM PST 24
Peak memory	226596 kb
Host	smart-b23803bb-4457-477a-ac92-111feb5bf33d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3566313502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.3566313502 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_sideload/latest

Test location	/workspace/coverage/default/40.kmac_smoke.1392275464
Short name	T713
Test name
Test status
Simulation time	1345239528 ps
CPU time	28.27 seconds
Started	Feb 04 02:54:31 PM PST 24
Finished	Feb 04 02:55:04 PM PST 24
Peak memory	219780 kb
Host	smart-a18be8dc-523f-401a-92b1-51b64bf7da57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1392275464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.1392275464 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_smoke/latest

Test location	/workspace/coverage/default/40.kmac_stress_all.1566602887
Short name	T345
Test name
Test status
Simulation time	44100193850 ps
CPU time	1191.89 seconds
Started	Feb 04 02:55:11 PM PST 24
Finished	Feb 04 03:15:05 PM PST 24
Peak memory	350340 kb
Host	smart-ab33024c-55f0-404f-a4de-e9eebb66b3b9
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1566602887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.1566602887 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_stress_all/latest

Test location	/workspace/coverage/default/40.kmac_stress_all_with_rand_reset.2166911030
Short name	T936
Test name
Test status
Simulation time	71577851889 ps
CPU time	2621.2 seconds
Started	Feb 04 02:55:09 PM PST 24
Finished	Feb 04 03:38:53 PM PST 24
Peak memory	391328 kb
Host	smart-b68b8812-2889-4013-9091-48e72b6ada3f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2166911030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all_with_rand_reset.2166911030 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_kmac.1601392013
Short name	T890
Test name
Test status
Simulation time	639679457 ps
CPU time	6.45 seconds
Started	Feb 04 02:54:54 PM PST 24
Finished	Feb 04 02:55:05 PM PST 24
Peak memory	218824 kb
Host	smart-3e39a420-504d-418e-8ae3-5035d5ccf91e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601392013 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 40.kmac_test_vectors_kmac.1601392013 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_kmac_xof.4294258969
Short name	T1086
Test name
Test status
Simulation time	286899673 ps
CPU time	6.47 seconds
Started	Feb 04 02:54:53 PM PST 24
Finished	Feb 04 02:55:00 PM PST 24
Peak memory	218904 kb
Host	smart-10eec769-82d5-424f-89b2-dca8b49aedc5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294258969 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_kmac_xof.4294258969 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_224.3094230871
Short name	T978
Test name
Test status
Simulation time	177912259837 ps
CPU time	2474.48 seconds
Started	Feb 04 02:54:42 PM PST 24
Finished	Feb 04 03:35:58 PM PST 24
Peak memory	404240 kb
Host	smart-06c152c4-e2a5-40e8-84d5-396f7fed6d1c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3094230871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.3094230871 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_256.3524083272
Short name	T830
Test name
Test status
Simulation time	40714229085 ps
CPU time	2054.95 seconds
Started	Feb 04 02:54:42 PM PST 24
Finished	Feb 04 03:28:58 PM PST 24
Peak memory	386600 kb
Host	smart-6619bd73-2236-464e-a212-18b2dc236d14
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3524083272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.3524083272 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_384.2198128668
Short name	T994
Test name
Test status
Simulation time	98928563314 ps
CPU time	1611.85 seconds
Started	Feb 04 02:54:45 PM PST 24
Finished	Feb 04 03:21:38 PM PST 24
Peak memory	338956 kb
Host	smart-665fb67a-5aea-4afc-99f2-662e0aaef7a0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2198128668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.2198128668 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_512.3628732985
Short name	T526
Test name
Test status
Simulation time	39011753810 ps
CPU time	1033.34 seconds
Started	Feb 04 02:54:45 PM PST 24
Finished	Feb 04 03:11:59 PM PST 24
Peak memory	302332 kb
Host	smart-d84c4715-b267-40d2-90c6-60be973baccb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3628732985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.3628732985 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_shake_128.3438891312
Short name	T549
Test name
Test status
Simulation time	358640053964 ps
CPU time	5728.2 seconds
Started	Feb 04 02:54:46 PM PST 24
Finished	Feb 04 04:30:15 PM PST 24
Peak memory	674772 kb
Host	smart-49310c39-8243-43ed-be54-eab3210e0d56
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3438891312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.3438891312 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_shake_256.1850815389
Short name	T449
Test name
Test status
Simulation time	55568220737 ps
CPU time	5115.13 seconds
Started	Feb 04 02:54:55 PM PST 24
Finished	Feb 04 04:20:15 PM PST 24
Peak memory	581336 kb
Host	smart-d3ee60df-a6db-4c99-9104-b6a8ac5853dc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1850815389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.1850815389 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/41.kmac_alert_test.4155275306
Short name	T427
Test name
Test status
Simulation time	18364546 ps
CPU time	0.87 seconds
Started	Feb 04 02:55:33 PM PST 24
Finished	Feb 04 02:55:37 PM PST 24
Peak memory	218328 kb
Host	smart-083b6e27-09f0-480e-82a3-eeaead9c5fa6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155275306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.4155275306 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_alert_test/latest

Test location	/workspace/coverage/default/41.kmac_burst_write.3865088227
Short name	T813
Test name
Test status
Simulation time	13709373198 ps
CPU time	1332.99 seconds
Started	Feb 04 02:55:14 PM PST 24
Finished	Feb 04 03:17:32 PM PST 24
Peak memory	239772 kb
Host	smart-b6e6dc21-3713-4350-815e-f86de6046b56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3865088227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.3865088227 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_burst_write/latest

Test location	/workspace/coverage/default/41.kmac_entropy_refresh.2897271889
Short name	T515
Test name
Test status
Simulation time	8505284269 ps
CPU time	133.85 seconds
Started	Feb 04 02:55:24 PM PST 24
Finished	Feb 04 02:57:38 PM PST 24
Peak memory	236132 kb
Host	smart-3e056eee-15ed-40f3-a647-7a01476f849b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2897271889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.2897271889 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/41.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/41.kmac_error.2954437656
Short name	T986
Test name
Test status
Simulation time	4823786865 ps
CPU time	120.67 seconds
Started	Feb 04 02:55:25 PM PST 24
Finished	Feb 04 02:57:27 PM PST 24
Peak memory	244396 kb
Host	smart-2fef9747-36a6-4655-8238-2402abb2cce2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2954437656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.2954437656 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_error/latest

Test location	/workspace/coverage/default/41.kmac_key_error.3168287647
Short name	T104
Test name
Test status
Simulation time	1751905582 ps
CPU time	3.15 seconds
Started	Feb 04 02:55:24 PM PST 24
Finished	Feb 04 02:55:28 PM PST 24
Peak memory	218688 kb
Host	smart-d3a59bf9-f5f7-4bde-9f91-07b2584f7a5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3168287647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.3168287647 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_key_error/latest

Test location	/workspace/coverage/default/41.kmac_lc_escalation.262523398
Short name	T576
Test name
Test status
Simulation time	62539580 ps
CPU time	1.5 seconds
Started	Feb 04 02:55:24 PM PST 24
Finished	Feb 04 02:55:26 PM PST 24
Peak memory	219716 kb
Host	smart-d0cd4f2b-d004-4a0a-b694-6758d62dc5b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=262523398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.262523398 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/41.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/41.kmac_long_msg_and_output.2799999855
Short name	T168
Test name
Test status
Simulation time	426615900772 ps
CPU time	2722.97 seconds
Started	Feb 04 02:55:09 PM PST 24
Finished	Feb 04 03:40:35 PM PST 24
Peak memory	407296 kb
Host	smart-ca25064e-fd71-4130-a788-248b466f4911
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799999855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a nd_output.2799999855 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/41.kmac_sideload.1331554757
Short name	T1053
Test name
Test status
Simulation time	81434570743 ps
CPU time	550.47 seconds
Started	Feb 04 02:55:05 PM PST 24
Finished	Feb 04 03:04:16 PM PST 24
Peak memory	257216 kb
Host	smart-dd16c8ee-1c56-4821-b399-1e51ba47e10e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1331554757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.1331554757 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_sideload/latest

Test location	/workspace/coverage/default/41.kmac_smoke.2753563009
Short name	T580
Test name
Test status
Simulation time	1317261581 ps
CPU time	53.34 seconds
Started	Feb 04 02:55:09 PM PST 24
Finished	Feb 04 02:56:05 PM PST 24
Peak memory	219524 kb
Host	smart-280f36c2-4708-4d58-8fe6-ed6007f15038
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2753563009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.2753563009 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_smoke/latest

Test location	/workspace/coverage/default/41.kmac_stress_all.154611578
Short name	T381
Test name
Test status
Simulation time	34044289827 ps
CPU time	1191.92 seconds
Started	Feb 04 02:55:24 PM PST 24
Finished	Feb 04 03:15:18 PM PST 24
Peak memory	353472 kb
Host	smart-c2c83311-a49e-4895-8cd1-f4a0fef897da
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=154611578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.154611578 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_stress_all/latest

Test location	/workspace/coverage/default/41.kmac_stress_all_with_rand_reset.1381694466
Short name	T382
Test name
Test status
Simulation time	69610036397 ps
CPU time	2392.28 seconds
Started	Feb 04 02:55:25 PM PST 24
Finished	Feb 04 03:35:19 PM PST 24
Peak memory	359140 kb
Host	smart-2c419f29-0b52-4e8e-97bf-d7217711e99c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1381694466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all_with_rand_reset.1381694466 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_kmac.328958979
Short name	T754
Test name
Test status
Simulation time	207096703 ps
CPU time	6.41 seconds
Started	Feb 04 02:55:22 PM PST 24
Finished	Feb 04 02:55:29 PM PST 24
Peak memory	220124 kb
Host	smart-a564f932-d4bf-42d4-9f01-f44041ca1f2a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328958979 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 41.kmac_test_vectors_kmac.328958979 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_kmac_xof.880734045
Short name	T763
Test name
Test status
Simulation time	113023326 ps
CPU time	5.69 seconds
Started	Feb 04 02:55:15 PM PST 24
Finished	Feb 04 02:55:25 PM PST 24
Peak memory	218808 kb
Host	smart-1cc24f05-5719-48d2-b8a8-445844dd574e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880734045 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 41.kmac_test_vectors_kmac_xof.880734045 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_224.2267471510
Short name	T464
Test name
Test status
Simulation time	296317255010 ps
CPU time	2388.29 seconds
Started	Feb 04 02:55:22 PM PST 24
Finished	Feb 04 03:35:11 PM PST 24
Peak memory	389484 kb
Host	smart-4042051e-b012-4d0f-8ebd-1d8e4f5d56c8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2267471510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.2267471510 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_256.950817990
Short name	T1071
Test name
Test status
Simulation time	91784258922 ps
CPU time	2399.98 seconds
Started	Feb 04 02:55:17 PM PST 24
Finished	Feb 04 03:35:19 PM PST 24
Peak memory	388304 kb
Host	smart-2b7928c3-a7a7-459a-bcc6-915e305ffdd3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=950817990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.950817990 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_384.1754241272
Short name	T610
Test name
Test status
Simulation time	181632252271 ps
CPU time	1725.42 seconds
Started	Feb 04 02:55:15 PM PST 24
Finished	Feb 04 03:24:05 PM PST 24
Peak memory	339468 kb
Host	smart-a1ac2aab-da3b-4e40-937b-c79494d60683
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1754241272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.1754241272 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_512.1070039612
Short name	T1062
Test name
Test status
Simulation time	21572619695 ps
CPU time	1085.87 seconds
Started	Feb 04 02:55:22 PM PST 24
Finished	Feb 04 03:13:29 PM PST 24
Peak memory	300492 kb
Host	smart-b770975e-ddfa-496f-89aa-1b09f7fcf727
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1070039612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.1070039612 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_shake_128.1348675869
Short name	T961
Test name
Test status
Simulation time	359229345556 ps
CPU time	6094.25 seconds
Started	Feb 04 02:55:20 PM PST 24
Finished	Feb 04 04:36:56 PM PST 24
Peak memory	650140 kb
Host	smart-861068b3-e55a-49f5-997e-c8eaeec34ee8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1348675869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.1348675869 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_shake_256.2202274810
Short name	T930
Test name
Test status
Simulation time	365394569317 ps
CPU time	5649.38 seconds
Started	Feb 04 02:55:18 PM PST 24
Finished	Feb 04 04:29:30 PM PST 24
Peak memory	568468 kb
Host	smart-2991b821-cbe8-4440-b504-e5799cdd615c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2202274810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.2202274810 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/42.kmac_alert_test.1389287740
Short name	T298
Test name
Test status
Simulation time	27120472 ps
CPU time	0.88 seconds
Started	Feb 04 02:56:08 PM PST 24
Finished	Feb 04 02:56:10 PM PST 24
Peak memory	219520 kb
Host	smart-5eace77b-7cc6-43b3-b295-ff0665a374d9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389287740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.1389287740 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_alert_test/latest

Test location	/workspace/coverage/default/42.kmac_app.3456213623
Short name	T736
Test name
Test status
Simulation time	3375860452 ps
CPU time	30.55 seconds
Started	Feb 04 02:55:57 PM PST 24
Finished	Feb 04 02:56:30 PM PST 24
Peak memory	226556 kb
Host	smart-442c5c09-77b2-4c94-8d03-d7d75b713db9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3456213623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.3456213623 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_app/latest

Test location	/workspace/coverage/default/42.kmac_burst_write.279072696
Short name	T904
Test name
Test status
Simulation time	14889074833 ps
CPU time	1577.4 seconds
Started	Feb 04 02:55:33 PM PST 24
Finished	Feb 04 03:21:53 PM PST 24
Peak memory	240268 kb
Host	smart-52738cde-faf0-4fb7-9c55-4600c2b5630e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=279072696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.279072696 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_burst_write/latest

Test location	/workspace/coverage/default/42.kmac_entropy_refresh.1142109004
Short name	T1045
Test name
Test status
Simulation time	21714094449 ps
CPU time	221.28 seconds
Started	Feb 04 02:55:56 PM PST 24
Finished	Feb 04 02:59:40 PM PST 24
Peak memory	244552 kb
Host	smart-df20ecd6-714a-49cc-b8c3-a77cf47e6be4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1142109004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.1142109004 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/42.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/42.kmac_error.3874510599
Short name	T73
Test name
Test status
Simulation time	513550707 ps
CPU time	40.45 seconds
Started	Feb 04 02:55:58 PM PST 24
Finished	Feb 04 02:56:40 PM PST 24
Peak memory	243116 kb
Host	smart-59cc8952-a749-4f8c-be96-36700c4c6a63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3874510599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.3874510599 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_error/latest

Test location	/workspace/coverage/default/42.kmac_key_error.3872149625
Short name	T28
Test name
Test status
Simulation time	1509261557 ps
CPU time	2.61 seconds
Started	Feb 04 02:55:55 PM PST 24
Finished	Feb 04 02:56:02 PM PST 24
Peak memory	218664 kb
Host	smart-a39b1938-a8ed-4c6b-88a8-139bf23054b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3872149625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.3872149625 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_key_error/latest

Test location	/workspace/coverage/default/42.kmac_lc_escalation.3585811343
Short name	T888
Test name
Test status
Simulation time	34621609 ps
CPU time	1.35 seconds
Started	Feb 04 02:56:10 PM PST 24
Finished	Feb 04 02:56:14 PM PST 24
Peak memory	219624 kb
Host	smart-097b0507-5b12-471c-ad73-0857809bb7bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3585811343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.3585811343 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/42.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/42.kmac_long_msg_and_output.2407032559
Short name	T726
Test name
Test status
Simulation time	27542502288 ps
CPU time	3304.52 seconds
Started	Feb 04 02:55:31 PM PST 24
Finished	Feb 04 03:50:40 PM PST 24
Peak memory	470964 kb
Host	smart-6547dda5-aa5c-4f0e-a7eb-fa596a164d7c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407032559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a nd_output.2407032559 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/42.kmac_sideload.4172992113
Short name	T668
Test name
Test status
Simulation time	8174468047 ps
CPU time	493.88 seconds
Started	Feb 04 02:55:34 PM PST 24
Finished	Feb 04 03:03:50 PM PST 24
Peak memory	259092 kb
Host	smart-d9bb3175-93c4-46aa-8e80-62adb5c5aabd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4172992113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.4172992113 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_sideload/latest

Test location	/workspace/coverage/default/42.kmac_smoke.3840530317
Short name	T993
Test name
Test status
Simulation time	3629786825 ps
CPU time	52.29 seconds
Started	Feb 04 02:55:31 PM PST 24
Finished	Feb 04 02:56:28 PM PST 24
Peak memory	223416 kb
Host	smart-1ec811e1-a42d-4a1c-a896-9860f0a67e99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3840530317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.3840530317 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_smoke/latest

Test location	/workspace/coverage/default/42.kmac_stress_all.2733206141
Short name	T779
Test name
Test status
Simulation time	825903558 ps
CPU time	9.95 seconds
Started	Feb 04 02:56:17 PM PST 24
Finished	Feb 04 02:56:29 PM PST 24
Peak memory	227560 kb
Host	smart-b12f2726-7ecf-4dad-8be3-1e70d96f6fa9
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2733206141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2733206141 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_stress_all/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_kmac.3607566683
Short name	T586
Test name
Test status
Simulation time	1556512425 ps
CPU time	6.85 seconds
Started	Feb 04 02:55:51 PM PST 24
Finished	Feb 04 02:56:00 PM PST 24
Peak memory	220348 kb
Host	smart-5002b514-c86d-4a34-b9da-c0b6af8e7088
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607566683 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 42.kmac_test_vectors_kmac.3607566683 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_kmac_xof.364657946
Short name	T935
Test name
Test status
Simulation time	667912227 ps
CPU time	5.88 seconds
Started	Feb 04 02:55:52 PM PST 24
Finished	Feb 04 02:55:59 PM PST 24
Peak memory	218920 kb
Host	smart-33d7afe0-b931-493a-9f61-ed0ea63b97a9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364657946 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 42.kmac_test_vectors_kmac_xof.364657946 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_224.3927915857
Short name	T441
Test name
Test status
Simulation time	347623687634 ps
CPU time	2184.95 seconds
Started	Feb 04 02:55:37 PM PST 24
Finished	Feb 04 03:32:03 PM PST 24
Peak memory	393440 kb
Host	smart-c63f55e7-c8fa-4d92-9ca5-96420aa116d3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3927915857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.3927915857 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_256.725323957
Short name	T188
Test name
Test status
Simulation time	24938953439 ps
CPU time	2184.1 seconds
Started	Feb 04 02:55:51 PM PST 24
Finished	Feb 04 03:32:17 PM PST 24
Peak memory	383592 kb
Host	smart-65f9c9e3-b16a-466d-b5c6-23dd62be119e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=725323957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.725323957 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_384.2625951717
Short name	T665
Test name
Test status
Simulation time	263801185175 ps
CPU time	1869.02 seconds
Started	Feb 04 02:55:57 PM PST 24
Finished	Feb 04 03:27:08 PM PST 24
Peak memory	343348 kb
Host	smart-e022abe1-6001-4d43-b071-6b09d37e33b3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2625951717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.2625951717 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_512.594426978
Short name	T194
Test name
Test status
Simulation time	56413559137 ps
CPU time	1350.48 seconds
Started	Feb 04 02:55:51 PM PST 24
Finished	Feb 04 03:18:23 PM PST 24
Peak memory	302796 kb
Host	smart-8bc77079-6407-4c06-9c76-f9710b5613e0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=594426978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.594426978 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_shake_128.3429162795
Short name	T1103
Test name
Test status
Simulation time	293393552120 ps
CPU time	6451.42 seconds
Started	Feb 04 02:55:51 PM PST 24
Finished	Feb 04 04:43:25 PM PST 24
Peak memory	658624 kb
Host	smart-57b271b2-7ee4-422e-a4fd-db225edcaaa2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3429162795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.3429162795 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_shake_256.2538134538
Short name	T195
Test name
Test status
Simulation time	604790109294 ps
CPU time	5778.76 seconds
Started	Feb 04 02:55:51 PM PST 24
Finished	Feb 04 04:32:12 PM PST 24
Peak memory	576980 kb
Host	smart-ed59f832-4ad4-42a3-a354-baf99aa420f0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2538134538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.2538134538 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/43.kmac_alert_test.1809198548
Short name	T629
Test name
Test status
Simulation time	22324065 ps
CPU time	0.93 seconds
Started	Feb 04 02:56:52 PM PST 24
Finished	Feb 04 02:56:56 PM PST 24
Peak memory	218372 kb
Host	smart-77f61ff8-ebac-4d3c-bf53-407262090b0c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809198548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.1809198548 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_alert_test/latest

Test location	/workspace/coverage/default/43.kmac_app.2782881720
Short name	T552
Test name
Test status
Simulation time	24971569619 ps
CPU time	159.05 seconds
Started	Feb 04 02:56:19 PM PST 24
Finished	Feb 04 02:58:59 PM PST 24
Peak memory	238120 kb
Host	smart-49a7399c-6f8d-4096-bc79-649db4e9c395
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2782881720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.2782881720 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_app/latest

Test location	/workspace/coverage/default/43.kmac_burst_write.452967684
Short name	T504
Test name
Test status
Simulation time	84003881768 ps
CPU time	916.84 seconds
Started	Feb 04 02:56:16 PM PST 24
Finished	Feb 04 03:11:34 PM PST 24
Peak memory	243444 kb
Host	smart-7db320b7-e25f-4b70-a0bc-aa681279b1fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=452967684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.452967684 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_burst_write/latest

Test location	/workspace/coverage/default/43.kmac_entropy_refresh.1453509484
Short name	T911
Test name
Test status
Simulation time	2946504710 ps
CPU time	58.37 seconds
Started	Feb 04 02:56:26 PM PST 24
Finished	Feb 04 02:57:25 PM PST 24
Peak memory	231736 kb
Host	smart-8e56fc77-1038-47ed-a177-07fe63574d23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1453509484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.1453509484 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/43.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/43.kmac_error.756424037
Short name	T875
Test name
Test status
Simulation time	27782810213 ps
CPU time	491.27 seconds
Started	Feb 04 02:56:48 PM PST 24
Finished	Feb 04 03:05:00 PM PST 24
Peak memory	258068 kb
Host	smart-c5d296d9-c9e8-4c79-be06-3710aad92da7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=756424037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.756424037 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_error/latest

Test location	/workspace/coverage/default/43.kmac_key_error.3913399820
Short name	T841
Test name
Test status
Simulation time	1358013753 ps
CPU time	2.81 seconds
Started	Feb 04 02:56:47 PM PST 24
Finished	Feb 04 02:56:50 PM PST 24
Peak memory	218568 kb
Host	smart-b0c2ba50-d8b7-40c5-9f10-d0c959d4952a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3913399820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.3913399820 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_key_error/latest

Test location	/workspace/coverage/default/43.kmac_lc_escalation.2866196440
Short name	T291
Test name
Test status
Simulation time	734951390 ps
CPU time	17.76 seconds
Started	Feb 04 02:56:34 PM PST 24
Finished	Feb 04 02:56:57 PM PST 24
Peak memory	232276 kb
Host	smart-58256383-b166-4232-9a6e-8375038cb39f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2866196440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.2866196440 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/43.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/43.kmac_long_msg_and_output.994714340
Short name	T1024
Test name
Test status
Simulation time	16581580448 ps
CPU time	489.6 seconds
Started	Feb 04 02:56:17 PM PST 24
Finished	Feb 04 03:04:29 PM PST 24
Peak memory	256588 kb
Host	smart-42a1654b-9100-469d-9628-6a8b0ba03cee
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994714340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_an d_output.994714340 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/43.kmac_sideload.3486669068
Short name	T543
Test name
Test status
Simulation time	14188405631 ps
CPU time	298.07 seconds
Started	Feb 04 02:56:15 PM PST 24
Finished	Feb 04 03:01:14 PM PST 24
Peak memory	249000 kb
Host	smart-d6fde37e-d1de-4686-b22f-8fc8408e5be0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3486669068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.3486669068 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_sideload/latest

Test location	/workspace/coverage/default/43.kmac_smoke.1279343237
Short name	T459
Test name
Test status
Simulation time	1568294490 ps
CPU time	67.55 seconds
Started	Feb 04 02:56:07 PM PST 24
Finished	Feb 04 02:57:16 PM PST 24
Peak memory	223088 kb
Host	smart-41b4a5bf-3715-4d27-a557-a21a117cda8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1279343237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.1279343237 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_smoke/latest

Test location	/workspace/coverage/default/43.kmac_stress_all.3123929497
Short name	T645
Test name
Test status
Simulation time	34289661746 ps
CPU time	878.51 seconds
Started	Feb 04 02:56:48 PM PST 24
Finished	Feb 04 03:11:27 PM PST 24
Peak memory	324420 kb
Host	smart-fdc541b6-5449-403e-85a4-db21604fa5d9
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3123929497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.3123929497 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_stress_all/latest

Test location	/workspace/coverage/default/43.kmac_stress_all_with_rand_reset.3927939650
Short name	T486
Test name
Test status
Simulation time	11623540264 ps
CPU time	442.56 seconds
Started	Feb 04 02:56:54 PM PST 24
Finished	Feb 04 03:04:19 PM PST 24
Peak memory	271988 kb
Host	smart-e57a24e4-6f38-4107-9cd5-1284597ef391
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3927939650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all_with_rand_reset.3927939650 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_kmac.2685317934
Short name	T259
Test name
Test status
Simulation time	1206647211 ps
CPU time	6.35 seconds
Started	Feb 04 02:56:17 PM PST 24
Finished	Feb 04 02:56:26 PM PST 24
Peak memory	218920 kb
Host	smart-5b53fb11-c3c8-4a85-8ab3-8a1d4d5336b1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685317934 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 43.kmac_test_vectors_kmac.2685317934 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_kmac_xof.455984394
Short name	T649
Test name
Test status
Simulation time	116487766 ps
CPU time	6.88 seconds
Started	Feb 04 02:56:18 PM PST 24
Finished	Feb 04 02:56:27 PM PST 24
Peak memory	218896 kb
Host	smart-cdd47fb6-5f7a-451d-b0b2-2d0e0ef50d53
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455984394 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 43.kmac_test_vectors_kmac_xof.455984394 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_224.4120408160
Short name	T421
Test name
Test status
Simulation time	87519491016 ps
CPU time	2177.86 seconds
Started	Feb 04 02:56:11 PM PST 24
Finished	Feb 04 03:32:30 PM PST 24
Peak memory	395404 kb
Host	smart-1f73bfe6-fd9b-46c2-907b-dae626b7be26
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4120408160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.4120408160 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_256.3852266650
Short name	T933
Test name
Test status
Simulation time	41720380270 ps
CPU time	2113.9 seconds
Started	Feb 04 02:56:14 PM PST 24
Finished	Feb 04 03:31:29 PM PST 24
Peak memory	400856 kb
Host	smart-23649e1e-d367-4507-b56c-f174fa2aebc9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3852266650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.3852266650 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_384.499361478
Short name	T352
Test name
Test status
Simulation time	50725025750 ps
CPU time	1744.9 seconds
Started	Feb 04 02:56:16 PM PST 24
Finished	Feb 04 03:25:24 PM PST 24
Peak memory	342040 kb
Host	smart-6e954af1-b96b-43aa-80a7-e8bb4f96442a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=499361478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.499361478 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_512.1138066420
Short name	T871
Test name
Test status
Simulation time	12750991671 ps
CPU time	1295.61 seconds
Started	Feb 04 02:56:10 PM PST 24
Finished	Feb 04 03:17:48 PM PST 24
Peak memory	300452 kb
Host	smart-19107681-dbb9-4707-b8ce-3a18acfc89cd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1138066420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.1138066420 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_shake_128.14768619
Short name	T764
Test name
Test status
Simulation time	272720869024 ps
CPU time	5433.78 seconds
Started	Feb 04 02:56:16 PM PST 24
Finished	Feb 04 04:26:53 PM PST 24
Peak memory	670344 kb
Host	smart-a5018d56-1e8c-4204-9c87-2d30199b7113
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=14768619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.14768619 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_shake_256.2250682573
Short name	T219
Test name
Test status
Simulation time	54561618931 ps
CPU time	5003.4 seconds
Started	Feb 04 02:56:17 PM PST 24
Finished	Feb 04 04:19:44 PM PST 24
Peak memory	568300 kb
Host	smart-1c9e5b85-a2b9-4805-a232-8279f587bb52
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2250682573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.2250682573 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/44.kmac_alert_test.1491078947
Short name	T701
Test name
Test status
Simulation time	28163661 ps
CPU time	0.84 seconds
Started	Feb 04 02:57:25 PM PST 24
Finished	Feb 04 02:57:28 PM PST 24
Peak memory	219424 kb
Host	smart-43b30027-9a51-4be9-be1a-54c0f8126b38
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491078947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.1491078947 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_alert_test/latest

Test location	/workspace/coverage/default/44.kmac_app.1572379631
Short name	T1020
Test name
Test status
Simulation time	10591344239 ps
CPU time	128.52 seconds
Started	Feb 04 02:57:13 PM PST 24
Finished	Feb 04 02:59:22 PM PST 24
Peak memory	237472 kb
Host	smart-38d5bb0a-765d-4c13-88e0-4feb5899b037
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1572379631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.1572379631 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_app/latest

Test location	/workspace/coverage/default/44.kmac_burst_write.1352335460
Short name	T837
Test name
Test status
Simulation time	27706768862 ps
CPU time	1494.8 seconds
Started	Feb 04 02:57:04 PM PST 24
Finished	Feb 04 03:22:00 PM PST 24
Peak memory	241068 kb
Host	smart-6ea5dfaa-b51d-4574-9883-896e8d8b33bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1352335460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.1352335460 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_burst_write/latest

Test location	/workspace/coverage/default/44.kmac_entropy_refresh.3170957421
Short name	T1068
Test name
Test status
Simulation time	1181232720 ps
CPU time	4.94 seconds
Started	Feb 04 02:57:12 PM PST 24
Finished	Feb 04 02:57:18 PM PST 24
Peak memory	225612 kb
Host	smart-9f1a6937-8032-4ae1-96e4-8dbe297541eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3170957421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.3170957421 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/44.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/44.kmac_error.880717864
Short name	T1073
Test name
Test status
Simulation time	36119413038 ps
CPU time	323.88 seconds
Started	Feb 04 02:57:12 PM PST 24
Finished	Feb 04 03:02:37 PM PST 24
Peak memory	259808 kb
Host	smart-cd02d49e-caf5-4037-a75f-32ae0962ebe6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=880717864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.880717864 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_error/latest

Test location	/workspace/coverage/default/44.kmac_key_error.1363341400
Short name	T239
Test name
Test status
Simulation time	611979217 ps
CPU time	2.66 seconds
Started	Feb 04 02:57:14 PM PST 24
Finished	Feb 04 02:57:18 PM PST 24
Peak memory	218724 kb
Host	smart-0f9411a5-496a-44ff-996d-f6d09e7eafd2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1363341400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.1363341400 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_key_error/latest

Test location	/workspace/coverage/default/44.kmac_lc_escalation.565795982
Short name	T605
Test name
Test status
Simulation time	83186506 ps
CPU time	1.37 seconds
Started	Feb 04 02:57:11 PM PST 24
Finished	Feb 04 02:57:13 PM PST 24
Peak memory	219668 kb
Host	smart-b21550a4-a90e-4dcc-8a69-41b5918734ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=565795982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.565795982 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/44.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/44.kmac_long_msg_and_output.3000615182
Short name	T982
Test name
Test status
Simulation time	80279330457 ps
CPU time	2004.43 seconds
Started	Feb 04 02:56:53 PM PST 24
Finished	Feb 04 03:30:21 PM PST 24
Peak memory	378608 kb
Host	smart-54fb5ae6-615c-41ee-8f7e-ad9e32a19058
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000615182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a nd_output.3000615182 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/44.kmac_sideload.3234560042
Short name	T1078
Test name
Test status
Simulation time	5521073536 ps
CPU time	437.07 seconds
Started	Feb 04 02:56:53 PM PST 24
Finished	Feb 04 03:04:13 PM PST 24
Peak memory	255808 kb
Host	smart-8be40e46-e388-41a9-b536-0f4a8dd0ebf4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3234560042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.3234560042 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_sideload/latest

Test location	/workspace/coverage/default/44.kmac_smoke.1443346635
Short name	T621
Test name
Test status
Simulation time	840834510 ps
CPU time	13.41 seconds
Started	Feb 04 02:56:48 PM PST 24
Finished	Feb 04 02:57:03 PM PST 24
Peak memory	227016 kb
Host	smart-28948a2e-e9ca-428e-9419-dabf339621c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1443346635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.1443346635 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_smoke/latest

Test location	/workspace/coverage/default/44.kmac_stress_all.2717253590
Short name	T1126
Test name
Test status
Simulation time	4786987500 ps
CPU time	274.29 seconds
Started	Feb 04 02:57:27 PM PST 24
Finished	Feb 04 03:02:03 PM PST 24
Peak memory	276616 kb
Host	smart-b832e577-fc96-4424-96d9-66f06625f6c4
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2717253590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.2717253590 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_stress_all/latest

Test location	/workspace/coverage/default/44.kmac_stress_all_with_rand_reset.1874273423
Short name	T755
Test name
Test status
Simulation time	45014638555 ps
CPU time	856.38 seconds
Started	Feb 04 02:57:24 PM PST 24
Finished	Feb 04 03:11:43 PM PST 24
Peak memory	276624 kb
Host	smart-4351e790-40e8-4d7b-ac1d-0759cbf9bd28
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1874273423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all_with_rand_reset.1874273423 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_kmac.1475046594
Short name	T563
Test name
Test status
Simulation time	954847176 ps
CPU time	7.29 seconds
Started	Feb 04 02:57:10 PM PST 24
Finished	Feb 04 02:57:18 PM PST 24
Peak memory	218748 kb
Host	smart-6386023b-e264-452e-bfb9-b1134029f455
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475046594 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 44.kmac_test_vectors_kmac.1475046594 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_kmac_xof.2807658662
Short name	T787
Test name
Test status
Simulation time	165913995 ps
CPU time	6.04 seconds
Started	Feb 04 02:57:15 PM PST 24
Finished	Feb 04 02:57:21 PM PST 24
Peak memory	220148 kb
Host	smart-903e844e-48a8-479d-afaa-4c9debfc008e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807658662 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_kmac_xof.2807658662 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_224.881535349
Short name	T1025
Test name
Test status
Simulation time	98329181756 ps
CPU time	2676.59 seconds
Started	Feb 04 02:57:00 PM PST 24
Finished	Feb 04 03:41:42 PM PST 24
Peak memory	396392 kb
Host	smart-18e1c15f-48a5-4a07-8a7b-03e7de2b5f40
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=881535349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.881535349 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_256.301261187
Short name	T671
Test name
Test status
Simulation time	130507914123 ps
CPU time	2294.71 seconds
Started	Feb 04 02:57:00 PM PST 24
Finished	Feb 04 03:35:20 PM PST 24
Peak memory	400032 kb
Host	smart-3e4e13da-0f21-4155-969b-162b69d3e19a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=301261187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.301261187 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_384.731174078
Short name	T322
Test name
Test status
Simulation time	286843011953 ps
CPU time	1772.41 seconds
Started	Feb 04 02:57:00 PM PST 24
Finished	Feb 04 03:26:37 PM PST 24
Peak memory	339960 kb
Host	smart-f129a09d-1bcf-4888-82de-93d297706de5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=731174078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.731174078 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_512.4068041632
Short name	T847
Test name
Test status
Simulation time	127921711155 ps
CPU time	1366 seconds
Started	Feb 04 02:56:54 PM PST 24
Finished	Feb 04 03:19:43 PM PST 24
Peak memory	295832 kb
Host	smart-ac3feed5-2be5-4c27-afd4-6d4c65b71c0a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4068041632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.4068041632 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_shake_128.2975793749
Short name	T1095
Test name
Test status
Simulation time	271985699164 ps
CPU time	5502.63 seconds
Started	Feb 04 02:57:09 PM PST 24
Finished	Feb 04 04:28:53 PM PST 24
Peak memory	645408 kb
Host	smart-b9c604d9-e6c0-4815-81fa-74316d9c15d9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2975793749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.2975793749 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_shake_256.2989166816
Short name	T788
Test name
Test status
Simulation time	190785026116 ps
CPU time	5245.83 seconds
Started	Feb 04 02:57:09 PM PST 24
Finished	Feb 04 04:24:37 PM PST 24
Peak memory	562776 kb
Host	smart-170774b6-efb7-4d05-8c45-f6f5fef90517
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2989166816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.2989166816 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/45.kmac_alert_test.3954644543
Short name	T922
Test name
Test status
Simulation time	18472794 ps
CPU time	0.89 seconds
Started	Feb 04 02:58:12 PM PST 24
Finished	Feb 04 02:58:14 PM PST 24
Peak memory	219456 kb
Host	smart-8463c863-bd72-4b27-a48d-900d0a91d3cf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954644543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.3954644543 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_alert_test/latest

Test location	/workspace/coverage/default/45.kmac_app.647689774
Short name	T1035
Test name
Test status
Simulation time	3661222260 ps
CPU time	151.95 seconds
Started	Feb 04 02:58:02 PM PST 24
Finished	Feb 04 03:00:35 PM PST 24
Peak memory	237848 kb
Host	smart-e80ced96-6ad0-4d9b-a289-706e22b60176
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=647689774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.647689774 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_app/latest

Test location	/workspace/coverage/default/45.kmac_burst_write.2628207647
Short name	T773
Test name
Test status
Simulation time	18142059578 ps
CPU time	234.04 seconds
Started	Feb 04 02:57:32 PM PST 24
Finished	Feb 04 03:01:28 PM PST 24
Peak memory	231012 kb
Host	smart-9e925907-3df5-4f3a-9d04-54da573f439a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2628207647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.2628207647 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_burst_write/latest

Test location	/workspace/coverage/default/45.kmac_entropy_refresh.623569787
Short name	T476
Test name
Test status
Simulation time	7339531661 ps
CPU time	224.54 seconds
Started	Feb 04 02:57:55 PM PST 24
Finished	Feb 04 03:01:41 PM PST 24
Peak memory	244596 kb
Host	smart-f9074615-0bbf-4855-9e59-6818e811182d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=623569787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.623569787 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/45.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/45.kmac_error.2841343969
Short name	T326
Test name
Test status
Simulation time	3322300715 ps
CPU time	68.79 seconds
Started	Feb 04 02:57:54 PM PST 24
Finished	Feb 04 02:59:05 PM PST 24
Peak memory	243532 kb
Host	smart-2559766f-15a0-4d5b-9616-f765e03c877d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2841343969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.2841343969 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_error/latest

Test location	/workspace/coverage/default/45.kmac_key_error.2961860828
Short name	T366
Test name
Test status
Simulation time	1239139800 ps
CPU time	4.26 seconds
Started	Feb 04 02:58:10 PM PST 24
Finished	Feb 04 02:58:15 PM PST 24
Peak memory	218604 kb
Host	smart-efabeb24-0c6e-4c5b-908e-dff34f144894
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2961860828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.2961860828 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_key_error/latest

Test location	/workspace/coverage/default/45.kmac_lc_escalation.1214638318
Short name	T641
Test name
Test status
Simulation time	128336596 ps
CPU time	1.39 seconds
Started	Feb 04 02:58:10 PM PST 24
Finished	Feb 04 02:58:12 PM PST 24
Peak memory	219648 kb
Host	smart-27353c9c-158c-4e1b-b8ec-47eb155aa19e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1214638318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.1214638318 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/45.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/45.kmac_long_msg_and_output.4058246930
Short name	T344
Test name
Test status
Simulation time	223831541296 ps
CPU time	2178.33 seconds
Started	Feb 04 02:57:31 PM PST 24
Finished	Feb 04 03:33:51 PM PST 24
Peak memory	390388 kb
Host	smart-b9168c80-6f19-4967-ade6-46c770664459
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058246930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a nd_output.4058246930 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/45.kmac_sideload.3548499970
Short name	T918
Test name
Test status
Simulation time	12919870639 ps
CPU time	242.78 seconds
Started	Feb 04 02:57:30 PM PST 24
Finished	Feb 04 03:01:34 PM PST 24
Peak memory	242612 kb
Host	smart-ed9adf86-39e4-46ba-8879-6011f6b860a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3548499970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.3548499970 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_sideload/latest

Test location	/workspace/coverage/default/45.kmac_smoke.3984871064
Short name	T784
Test name
Test status
Simulation time	726596750 ps
CPU time	9.82 seconds
Started	Feb 04 02:57:28 PM PST 24
Finished	Feb 04 02:57:39 PM PST 24
Peak memory	226996 kb
Host	smart-463ae288-7903-47a5-b9c9-145a35fabf9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3984871064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.3984871064 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_smoke/latest

Test location	/workspace/coverage/default/45.kmac_stress_all.57670151
Short name	T548
Test name
Test status
Simulation time	74120709605 ps
CPU time	1664.96 seconds
Started	Feb 04 02:58:04 PM PST 24
Finished	Feb 04 03:25:50 PM PST 24
Peak memory	384748 kb
Host	smart-88dcf325-0ddf-4344-b218-f44beef0bacb
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=57670151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.57670151 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_stress_all/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_kmac.260439133
Short name	T387
Test name
Test status
Simulation time	1025048512 ps
CPU time	6.44 seconds
Started	Feb 04 02:57:55 PM PST 24
Finished	Feb 04 02:58:03 PM PST 24
Peak memory	220156 kb
Host	smart-06a43581-5ed1-450c-b23f-64a2d989c09b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260439133 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 45.kmac_test_vectors_kmac.260439133 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_kmac_xof.24941531
Short name	T886
Test name
Test status
Simulation time	137786184 ps
CPU time	6.32 seconds
Started	Feb 04 02:57:55 PM PST 24
Finished	Feb 04 02:58:03 PM PST 24
Peak memory	220344 kb
Host	smart-6514339a-2113-443f-b535-0dac4b7395bb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24941531 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 45.kmac_test_vectors_kmac_xof.24941531 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_224.874628547
Short name	T691
Test name
Test status
Simulation time	272561375499 ps
CPU time	2356.18 seconds
Started	Feb 04 02:57:31 PM PST 24
Finished	Feb 04 03:36:50 PM PST 24
Peak memory	397784 kb
Host	smart-6e311728-fb2c-4005-96b3-dcb761b0a003
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=874628547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.874628547 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_256.127334890
Short name	T593
Test name
Test status
Simulation time	79201478343 ps
CPU time	1937.23 seconds
Started	Feb 04 02:57:39 PM PST 24
Finished	Feb 04 03:29:57 PM PST 24
Peak memory	380152 kb
Host	smart-9319d9f9-87a4-49d2-aed2-804652996588
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=127334890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.127334890 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_384.311409417
Short name	T946
Test name
Test status
Simulation time	306569422076 ps
CPU time	1778.19 seconds
Started	Feb 04 02:57:54 PM PST 24
Finished	Feb 04 03:27:35 PM PST 24
Peak memory	347904 kb
Host	smart-a70a5990-6377-4d9e-b872-6f76c478541f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=311409417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.311409417 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_512.3781161526
Short name	T318
Test name
Test status
Simulation time	48052447291 ps
CPU time	1437.96 seconds
Started	Feb 04 02:57:38 PM PST 24
Finished	Feb 04 03:21:37 PM PST 24
Peak memory	302016 kb
Host	smart-9f98c419-8895-4daa-9a2a-7f16d5c03293
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3781161526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.3781161526 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_shake_128.267644538
Short name	T680
Test name
Test status
Simulation time	778693993301 ps
CPU time	6077.57 seconds
Started	Feb 04 02:57:46 PM PST 24
Finished	Feb 04 04:39:06 PM PST 24
Peak memory	656408 kb
Host	smart-d3055025-dab7-4be7-afc6-37ef32bf93cc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=267644538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.267644538 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_shake_256.641964318
Short name	T199
Test name
Test status
Simulation time	215547428608 ps
CPU time	4509.47 seconds
Started	Feb 04 02:57:47 PM PST 24
Finished	Feb 04 04:12:58 PM PST 24
Peak memory	572308 kb
Host	smart-d7e12d7f-68bc-4311-9c00-67afa19b416e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=641964318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.641964318 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/46.kmac_alert_test.1695738095
Short name	T950
Test name
Test status
Simulation time	36726839 ps
CPU time	0.87 seconds
Started	Feb 04 02:58:32 PM PST 24
Finished	Feb 04 02:58:34 PM PST 24
Peak memory	219512 kb
Host	smart-b8981067-e267-4d8d-b3d4-0ee55bbc1473
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695738095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.1695738095 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_alert_test/latest

Test location	/workspace/coverage/default/46.kmac_app.2446516176
Short name	T540
Test name
Test status
Simulation time	3644474989 ps
CPU time	45.51 seconds
Started	Feb 04 02:58:19 PM PST 24
Finished	Feb 04 02:59:06 PM PST 24
Peak memory	229252 kb
Host	smart-0e771888-dfff-4823-996e-79f0c8df80ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2446516176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.2446516176 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_app/latest

Test location	/workspace/coverage/default/46.kmac_burst_write.2798760316
Short name	T1129
Test name
Test status
Simulation time	55484813562 ps
CPU time	1348.09 seconds
Started	Feb 04 02:58:12 PM PST 24
Finished	Feb 04 03:20:41 PM PST 24
Peak memory	239772 kb
Host	smart-c174eed2-a226-4195-acde-eda0455bd046
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2798760316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.2798760316 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_burst_write/latest

Test location	/workspace/coverage/default/46.kmac_entropy_refresh.1082650752
Short name	T391
Test name
Test status
Simulation time	31169298619 ps
CPU time	273.53 seconds
Started	Feb 04 02:58:19 PM PST 24
Finished	Feb 04 03:02:54 PM PST 24
Peak memory	249688 kb
Host	smart-6ca6a110-eae9-4161-bd07-971dfbbd5117
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1082650752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.1082650752 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/46.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/46.kmac_error.3213697506
Short name	T711
Test name
Test status
Simulation time	28680591460 ps
CPU time	421.36 seconds
Started	Feb 04 02:58:25 PM PST 24
Finished	Feb 04 03:05:28 PM PST 24
Peak memory	253456 kb
Host	smart-a61d6198-0035-4bc6-914f-440df003a444
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3213697506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.3213697506 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_error/latest

Test location	/workspace/coverage/default/46.kmac_key_error.2487287522
Short name	T657
Test name
Test status
Simulation time	5277857677 ps
CPU time	6.26 seconds
Started	Feb 04 02:58:24 PM PST 24
Finished	Feb 04 02:58:32 PM PST 24
Peak memory	218736 kb
Host	smart-5b01c67e-9992-4db5-b725-e72deba4b9a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2487287522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.2487287522 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_key_error/latest

Test location	/workspace/coverage/default/46.kmac_lc_escalation.369326170
Short name	T780
Test name
Test status
Simulation time	2060732613 ps
CPU time	22.42 seconds
Started	Feb 04 02:58:24 PM PST 24
Finished	Feb 04 02:58:49 PM PST 24
Peak memory	235108 kb
Host	smart-1c253cb2-d503-4db2-a328-453ef0296c46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=369326170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.369326170 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/46.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/46.kmac_long_msg_and_output.1065696776
Short name	T172
Test name
Test status
Simulation time	50620030322 ps
CPU time	1658.74 seconds
Started	Feb 04 02:58:04 PM PST 24
Finished	Feb 04 03:25:43 PM PST 24
Peak memory	393136 kb
Host	smart-03ec2646-9c09-4064-99ef-f0c2d82ab14f
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065696776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a nd_output.1065696776 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/46.kmac_sideload.1796404816
Short name	T483
Test name
Test status
Simulation time	2712024450 ps
CPU time	113.99 seconds
Started	Feb 04 02:58:11 PM PST 24
Finished	Feb 04 03:00:05 PM PST 24
Peak memory	233260 kb
Host	smart-6d592bbe-6db1-4f31-afbc-d292113f2398
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1796404816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.1796404816 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_sideload/latest

Test location	/workspace/coverage/default/46.kmac_smoke.1601744446
Short name	T534
Test name
Test status
Simulation time	2923064104 ps
CPU time	28.38 seconds
Started	Feb 04 02:58:11 PM PST 24
Finished	Feb 04 02:58:40 PM PST 24
Peak memory	227052 kb
Host	smart-a7d7db80-599f-4306-a1b6-fa4a051d90a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1601744446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.1601744446 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_smoke/latest

Test location	/workspace/coverage/default/46.kmac_stress_all.4293837258
Short name	T1031
Test name
Test status
Simulation time	15779967229 ps
CPU time	522.16 seconds
Started	Feb 04 02:58:25 PM PST 24
Finished	Feb 04 03:07:08 PM PST 24
Peak memory	296656 kb
Host	smart-b8390a8f-8d9c-4e7c-af6d-13e2ea7f7137
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4293837258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.4293837258 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_stress_all/latest

Test location	/workspace/coverage/default/46.kmac_stress_all_with_rand_reset.3553330198
Short name	T592
Test name
Test status
Simulation time	51367910732 ps
CPU time	2781.88 seconds
Started	Feb 04 02:58:26 PM PST 24
Finished	Feb 04 03:44:49 PM PST 24
Peak memory	433524 kb
Host	smart-d9ae2d9c-a59f-4be3-bd5c-393dcabe67c7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3553330198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all_with_rand_reset.3553330198 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_kmac.424732519
Short name	T300
Test name
Test status
Simulation time	109447400 ps
CPU time	5.49 seconds
Started	Feb 04 02:58:12 PM PST 24
Finished	Feb 04 02:58:18 PM PST 24
Peak memory	220256 kb
Host	smart-15d1656b-f0b9-4a8f-bc61-286078b2cee9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424732519 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 46.kmac_test_vectors_kmac.424732519 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_kmac_xof.2242306941
Short name	T692
Test name
Test status
Simulation time	215811546 ps
CPU time	7.11 seconds
Started	Feb 04 02:58:19 PM PST 24
Finished	Feb 04 02:58:27 PM PST 24
Peak memory	220128 kb
Host	smart-7adb83f7-9f45-49c3-ab8a-91f2ff89081b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242306941 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_kmac_xof.2242306941 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_224.146671666
Short name	T1057
Test name
Test status
Simulation time	431685303005 ps
CPU time	2380.5 seconds
Started	Feb 04 02:58:11 PM PST 24
Finished	Feb 04 03:37:52 PM PST 24
Peak memory	388648 kb
Host	smart-8e0c49cc-c51f-4ea6-8496-464a029b999e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=146671666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.146671666 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_256.718648096
Short name	T631
Test name
Test status
Simulation time	384163406646 ps
CPU time	2596.28 seconds
Started	Feb 04 02:58:11 PM PST 24
Finished	Feb 04 03:41:29 PM PST 24
Peak memory	392248 kb
Host	smart-cb21cee1-14f8-4c96-bbb1-cfe394777ee6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=718648096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.718648096 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_384.4012250338
Short name	T443
Test name
Test status
Simulation time	26579380111 ps
CPU time	1602.12 seconds
Started	Feb 04 02:58:14 PM PST 24
Finished	Feb 04 03:24:57 PM PST 24
Peak memory	343940 kb
Host	smart-9931b593-e749-4218-a6ae-4f57f04d9235
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4012250338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.4012250338 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_512.3501946959
Short name	T1106
Test name
Test status
Simulation time	63734651071 ps
CPU time	1195.04 seconds
Started	Feb 04 02:58:12 PM PST 24
Finished	Feb 04 03:18:08 PM PST 24
Peak memory	300168 kb
Host	smart-ce1d8c53-1639-456e-9ca3-09be046f0822
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3501946959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.3501946959 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_shake_128.3684286672
Short name	T561
Test name
Test status
Simulation time	61771028144 ps
CPU time	5453.72 seconds
Started	Feb 04 02:58:13 PM PST 24
Finished	Feb 04 04:29:08 PM PST 24
Peak memory	639656 kb
Host	smart-da0ea9e5-ce20-4f4e-875a-6aa647b944c2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3684286672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.3684286672 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_shake_256.4063809542
Short name	T1048
Test name
Test status
Simulation time	97545413287 ps
CPU time	5105.58 seconds
Started	Feb 04 02:58:11 PM PST 24
Finished	Feb 04 04:23:19 PM PST 24
Peak memory	570784 kb
Host	smart-9f934cd6-70a5-4779-8162-d8ba1cdc94d2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4063809542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.4063809542 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/47.kmac_alert_test.659773248
Short name	T555
Test name
Test status
Simulation time	52066473 ps
CPU time	0.92 seconds
Started	Feb 04 02:59:14 PM PST 24
Finished	Feb 04 02:59:16 PM PST 24
Peak memory	218376 kb
Host	smart-5ef5807c-b018-4b90-bd0a-eb97f76437cb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659773248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.659773248 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_alert_test/latest

Test location	/workspace/coverage/default/47.kmac_app.1636520317
Short name	T264
Test name
Test status
Simulation time	6740613228 ps
CPU time	59.51 seconds
Started	Feb 04 02:59:02 PM PST 24
Finished	Feb 04 03:00:03 PM PST 24
Peak memory	237484 kb
Host	smart-ac03ad42-f9b8-479b-af5f-16080fa39361
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1636520317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.1636520317 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_app/latest

Test location	/workspace/coverage/default/47.kmac_burst_write.1004702695
Short name	T975
Test name
Test status
Simulation time	12901280120 ps
CPU time	472.71 seconds
Started	Feb 04 02:58:32 PM PST 24
Finished	Feb 04 03:06:26 PM PST 24
Peak memory	241776 kb
Host	smart-bd24e54b-ee7c-44be-9fe4-dc2a3a7b3b5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1004702695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.1004702695 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_burst_write/latest

Test location	/workspace/coverage/default/47.kmac_entropy_refresh.3204728748
Short name	T974
Test name
Test status
Simulation time	9051254071 ps
CPU time	370.27 seconds
Started	Feb 04 02:59:09 PM PST 24
Finished	Feb 04 03:05:20 PM PST 24
Peak memory	252528 kb
Host	smart-0e916f03-5d6e-4511-93d7-844c91567a18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3204728748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.3204728748 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/47.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/47.kmac_error.3457825565
Short name	T521
Test name
Test status
Simulation time	7297762337 ps
CPU time	367.09 seconds
Started	Feb 04 02:59:07 PM PST 24
Finished	Feb 04 03:05:15 PM PST 24
Peak memory	260856 kb
Host	smart-0a28f268-b666-4f40-b3b7-e4045988d373
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3457825565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.3457825565 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_error/latest

Test location	/workspace/coverage/default/47.kmac_key_error.2315928446
Short name	T1027
Test name
Test status
Simulation time	705021439 ps
CPU time	4.22 seconds
Started	Feb 04 02:59:14 PM PST 24
Finished	Feb 04 02:59:19 PM PST 24
Peak memory	218676 kb
Host	smart-41aaa763-2ab3-4651-985f-f8020fdf0144
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2315928446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.2315928446 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_key_error/latest

Test location	/workspace/coverage/default/47.kmac_lc_escalation.1899964651
Short name	T231
Test name
Test status
Simulation time	146383132 ps
CPU time	1.38 seconds
Started	Feb 04 02:59:06 PM PST 24
Finished	Feb 04 02:59:09 PM PST 24
Peak memory	219660 kb
Host	smart-6fb32717-3c62-466b-817a-2de48f490ec1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1899964651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.1899964651 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/47.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/47.kmac_long_msg_and_output.1171898033
Short name	T546
Test name
Test status
Simulation time	41698298959 ps
CPU time	533.39 seconds
Started	Feb 04 02:58:34 PM PST 24
Finished	Feb 04 03:07:29 PM PST 24
Peak memory	268932 kb
Host	smart-30bea40d-d007-4435-8fb8-f4a822d67f9e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171898033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a nd_output.1171898033 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/47.kmac_sideload.542074202
Short name	T852
Test name
Test status
Simulation time	63444270070 ps
CPU time	137.5 seconds
Started	Feb 04 02:58:33 PM PST 24
Finished	Feb 04 03:00:53 PM PST 24
Peak memory	236512 kb
Host	smart-ed48f1e6-4889-4e89-bfb0-f7f1c19b3994
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=542074202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.542074202 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_sideload/latest

Test location	/workspace/coverage/default/47.kmac_smoke.2712875055
Short name	T1022
Test name
Test status
Simulation time	480170401 ps
CPU time	23.34 seconds
Started	Feb 04 02:58:30 PM PST 24
Finished	Feb 04 02:58:54 PM PST 24
Peak memory	219908 kb
Host	smart-baa9b9c8-7f19-4b6e-8acf-2a239d5a5efc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2712875055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.2712875055 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_smoke/latest

Test location	/workspace/coverage/default/47.kmac_stress_all.463925255
Short name	T718
Test name
Test status
Simulation time	7076540340 ps
CPU time	42.09 seconds
Started	Feb 04 02:59:22 PM PST 24
Finished	Feb 04 03:00:07 PM PST 24
Peak memory	243860 kb
Host	smart-2733244c-5be6-4b3e-99fb-86a40aea735b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=463925255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.463925255 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_stress_all/latest

Test location	/workspace/coverage/default/47.kmac_stress_all_with_rand_reset.2081006303
Short name	T819
Test name
Test status
Simulation time	163285890693 ps
CPU time	935.96 seconds
Started	Feb 04 02:59:21 PM PST 24
Finished	Feb 04 03:15:01 PM PST 24
Peak memory	287216 kb
Host	smart-7051d154-0904-4c6a-9e5a-27501d0f40d9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2081006303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all_with_rand_reset.2081006303 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_kmac.2162038304
Short name	T966
Test name
Test status
Simulation time	190002269 ps
CPU time	6.47 seconds
Started	Feb 04 02:58:57 PM PST 24
Finished	Feb 04 02:59:04 PM PST 24
Peak memory	218824 kb
Host	smart-560a0944-a5a3-4246-be7c-36013ca9fb06
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162038304 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 47.kmac_test_vectors_kmac.2162038304 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_kmac_xof.966716210
Short name	T785
Test name
Test status
Simulation time	2054097640 ps
CPU time	6.16 seconds
Started	Feb 04 02:59:06 PM PST 24
Finished	Feb 04 02:59:14 PM PST 24
Peak memory	218912 kb
Host	smart-d16fce87-fbd6-4d19-b493-d9f77453494a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966716210 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 47.kmac_test_vectors_kmac_xof.966716210 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_224.4229922909
Short name	T959
Test name
Test status
Simulation time	132693127401 ps
CPU time	2261.64 seconds
Started	Feb 04 02:58:40 PM PST 24
Finished	Feb 04 03:36:23 PM PST 24
Peak memory	402988 kb
Host	smart-24620790-8101-4925-8a7c-16e74e2a0748
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4229922909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.4229922909 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_256.3143987025
Short name	T349
Test name
Test status
Simulation time	20335970652 ps
CPU time	1837.03 seconds
Started	Feb 04 02:58:48 PM PST 24
Finished	Feb 04 03:29:26 PM PST 24
Peak memory	389564 kb
Host	smart-07082c8f-8e12-4b29-b3c5-d94ac81d239d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3143987025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.3143987025 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_384.3907937022
Short name	T968
Test name
Test status
Simulation time	64011022828 ps
CPU time	1539.03 seconds
Started	Feb 04 02:58:39 PM PST 24
Finished	Feb 04 03:24:21 PM PST 24
Peak memory	338140 kb
Host	smart-3ab1569a-8782-4048-8e5d-ac5c18cba0a0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3907937022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.3907937022 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_512.3453180213
Short name	T204
Test name
Test status
Simulation time	44794796709 ps
CPU time	1150.36 seconds
Started	Feb 04 02:59:06 PM PST 24
Finished	Feb 04 03:18:18 PM PST 24
Peak memory	307148 kb
Host	smart-7c78c5e2-a9cd-4f92-aa98-25f1fa101851
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3453180213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.3453180213 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_shake_128.3220469864
Short name	T707
Test name
Test status
Simulation time	65929694215 ps
CPU time	5742.08 seconds
Started	Feb 04 02:59:09 PM PST 24
Finished	Feb 04 04:34:52 PM PST 24
Peak memory	656536 kb
Host	smart-59249a24-3299-4772-9034-e6574be8da2e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3220469864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.3220469864 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_shake_256.4244969582
Short name	T488
Test name
Test status
Simulation time	208533611017 ps
CPU time	4832.6 seconds
Started	Feb 04 02:59:07 PM PST 24
Finished	Feb 04 04:19:42 PM PST 24
Peak memory	563096 kb
Host	smart-2d189c09-72ca-47c5-a613-0cb34889cd99
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4244969582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.4244969582 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/48.kmac_alert_test.3966377072
Short name	T209
Test name
Test status
Simulation time	18057974 ps
CPU time	0.85 seconds
Started	Feb 04 02:59:51 PM PST 24
Finished	Feb 04 02:59:53 PM PST 24
Peak memory	218272 kb
Host	smart-a9e612ee-30a2-481c-9324-80d9c1fbb2d5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966377072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.3966377072 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_alert_test/latest

Test location	/workspace/coverage/default/48.kmac_app.2138111581
Short name	T263
Test name
Test status
Simulation time	1697804876 ps
CPU time	19.89 seconds
Started	Feb 04 02:59:44 PM PST 24
Finished	Feb 04 03:00:06 PM PST 24
Peak memory	226860 kb
Host	smart-778c4cb4-cc58-42c0-ba75-01c1887f8abc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2138111581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.2138111581 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_app/latest

Test location	/workspace/coverage/default/48.kmac_burst_write.1128935069
Short name	T206
Test name
Test status
Simulation time	12102204097 ps
CPU time	415.14 seconds
Started	Feb 04 02:59:23 PM PST 24
Finished	Feb 04 03:06:20 PM PST 24
Peak memory	242104 kb
Host	smart-6e0c64d5-9c09-44a0-abd7-03baff814bd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1128935069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.1128935069 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_burst_write/latest

Test location	/workspace/coverage/default/48.kmac_entropy_refresh.2767622035
Short name	T332
Test name
Test status
Simulation time	6097863719 ps
CPU time	152.39 seconds
Started	Feb 04 02:59:44 PM PST 24
Finished	Feb 04 03:02:19 PM PST 24
Peak memory	238160 kb
Host	smart-c704d09b-eec3-4ccb-8238-da444a492dea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2767622035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.2767622035 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/48.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/48.kmac_error.3377269634
Short name	T636
Test name
Test status
Simulation time	25761740579 ps
CPU time	292.35 seconds
Started	Feb 04 02:59:50 PM PST 24
Finished	Feb 04 03:04:43 PM PST 24
Peak memory	259808 kb
Host	smart-fcb67f94-ea0c-433e-a28d-041d17dce95b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3377269634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.3377269634 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_error/latest

Test location	/workspace/coverage/default/48.kmac_key_error.2763065688
Short name	T356
Test name
Test status
Simulation time	2614791995 ps
CPU time	4.46 seconds
Started	Feb 04 02:59:52 PM PST 24
Finished	Feb 04 02:59:58 PM PST 24
Peak memory	218704 kb
Host	smart-d26718db-bdb6-452d-a17c-7e7d0d2d8298
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2763065688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.2763065688 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_key_error/latest

Test location	/workspace/coverage/default/48.kmac_lc_escalation.301595937
Short name	T920
Test name
Test status
Simulation time	82643646 ps
CPU time	1.45 seconds
Started	Feb 04 02:59:51 PM PST 24
Finished	Feb 04 02:59:53 PM PST 24
Peak memory	219820 kb
Host	smart-b48bfa7c-57a8-4581-a1ed-44fa6f751a95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=301595937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.301595937 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/48.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/48.kmac_long_msg_and_output.3533657848
Short name	T294
Test name
Test status
Simulation time	3066623594 ps
CPU time	74.09 seconds
Started	Feb 04 02:59:14 PM PST 24
Finished	Feb 04 03:00:29 PM PST 24
Peak memory	234668 kb
Host	smart-435bdefe-b35e-47de-974d-1427004f2de2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533657848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a nd_output.3533657848 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/48.kmac_sideload.2890019163
Short name	T374
Test name
Test status
Simulation time	43240424501 ps
CPU time	427.31 seconds
Started	Feb 04 02:59:25 PM PST 24
Finished	Feb 04 03:06:38 PM PST 24
Peak memory	251984 kb
Host	smart-6e0e6842-a195-408e-85c0-88a33aeff2d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2890019163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.2890019163 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_sideload/latest

Test location	/workspace/coverage/default/48.kmac_smoke.4144743174
Short name	T1019
Test name
Test status
Simulation time	1482097076 ps
CPU time	34.58 seconds
Started	Feb 04 02:59:21 PM PST 24
Finished	Feb 04 02:59:59 PM PST 24
Peak memory	223352 kb
Host	smart-e42ec38c-f2c3-4188-9944-ed4e3e299780
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4144743174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.4144743174 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_smoke/latest

Test location	/workspace/coverage/default/48.kmac_stress_all.1509612833
Short name	T545
Test name
Test status
Simulation time	106998223260 ps
CPU time	895.91 seconds
Started	Feb 04 02:59:50 PM PST 24
Finished	Feb 04 03:14:46 PM PST 24
Peak memory	309368 kb
Host	smart-21db614f-5da0-4e39-9bb4-3f32839b58a1
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1509612833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.1509612833 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_stress_all/latest

Test location	/workspace/coverage/default/48.kmac_stress_all_with_rand_reset.750201589
Short name	T16
Test name
Test status
Simulation time	77219225388 ps
CPU time	334.26 seconds
Started	Feb 04 02:59:50 PM PST 24
Finished	Feb 04 03:05:26 PM PST 24
Peak memory	264808 kb
Host	smart-66380c4f-3930-4e2c-9c16-6ae9dd536582
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=750201589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all_with_rand_reset.750201589 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_kmac.2713566367
Short name	T939
Test name
Test status
Simulation time	240136272 ps
CPU time	6.36 seconds
Started	Feb 04 02:59:43 PM PST 24
Finished	Feb 04 02:59:53 PM PST 24
Peak memory	220092 kb
Host	smart-2de7a6ef-f94a-4e49-b802-4276786e6860
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713566367 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 48.kmac_test_vectors_kmac.2713566367 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_kmac_xof.2186202619
Short name	T765
Test name
Test status
Simulation time	349624109 ps
CPU time	6.2 seconds
Started	Feb 04 02:59:48 PM PST 24
Finished	Feb 04 02:59:55 PM PST 24
Peak memory	220260 kb
Host	smart-d798e2e0-1b66-44bf-854f-0fa885e0bb18
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186202619 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_kmac_xof.2186202619 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_224.3015059318
Short name	T624
Test name
Test status
Simulation time	39967080549 ps
CPU time	1993.97 seconds
Started	Feb 04 02:59:26 PM PST 24
Finished	Feb 04 03:32:45 PM PST 24
Peak memory	390608 kb
Host	smart-f76f8e51-4a93-449f-b7ee-f6dfe6186193
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3015059318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.3015059318 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_256.801499967
Short name	T169
Test name
Test status
Simulation time	1868145942780 ps
CPU time	3178.68 seconds
Started	Feb 04 02:59:33 PM PST 24
Finished	Feb 04 03:52:32 PM PST 24
Peak memory	395508 kb
Host	smart-6b63f7da-8cbf-4f02-9806-e90871a25dcf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=801499967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.801499967 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_384.3434926627
Short name	T639
Test name
Test status
Simulation time	15155482433 ps
CPU time	1643.03 seconds
Started	Feb 04 02:59:31 PM PST 24
Finished	Feb 04 03:26:54 PM PST 24
Peak memory	340128 kb
Host	smart-40bdab8b-d775-4814-8248-2dc5961c410e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3434926627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.3434926627 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_512.1635336349
Short name	T634
Test name
Test status
Simulation time	34942104894 ps
CPU time	1286.23 seconds
Started	Feb 04 02:59:37 PM PST 24
Finished	Feb 04 03:21:06 PM PST 24
Peak memory	298116 kb
Host	smart-a70ab70d-dfc7-4ad5-a44f-fb4f358ffae8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1635336349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.1635336349 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_shake_128.2089914072
Short name	T1041
Test name
Test status
Simulation time	119901188034 ps
CPU time	5528.78 seconds
Started	Feb 04 02:59:38 PM PST 24
Finished	Feb 04 04:31:50 PM PST 24
Peak memory	648256 kb
Host	smart-fd3c8523-0b1c-4292-a450-059fb023418a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2089914072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.2089914072 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_shake_256.66458357
Short name	T32
Test name
Test status
Simulation time	908383929023 ps
CPU time	5584.9 seconds
Started	Feb 04 02:59:45 PM PST 24
Finished	Feb 04 04:32:52 PM PST 24
Peak memory	568528 kb
Host	smart-b1ca97b4-86e7-44bc-a930-f0fbfd92b6ff
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=66458357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.66458357 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/49.kmac_alert_test.448718220
Short name	T887
Test name
Test status
Simulation time	102271627 ps
CPU time	0.93 seconds
Started	Feb 04 03:00:43 PM PST 24
Finished	Feb 04 03:00:45 PM PST 24
Peak memory	218272 kb
Host	smart-2c91bbfe-5718-4cf7-8808-0c7471a3a43c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448718220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.448718220 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_alert_test/latest

Test location	/workspace/coverage/default/49.kmac_app.2592265073
Short name	T651
Test name
Test status
Simulation time	50145004216 ps
CPU time	349.49 seconds
Started	Feb 04 03:00:33 PM PST 24
Finished	Feb 04 03:06:24 PM PST 24
Peak memory	251920 kb
Host	smart-7bf6fbb7-2cfe-4521-9462-79d5097744e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2592265073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.2592265073 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_app/latest

Test location	/workspace/coverage/default/49.kmac_burst_write.3678062223
Short name	T1110
Test name
Test status
Simulation time	19630294288 ps
CPU time	419.68 seconds
Started	Feb 04 02:59:55 PM PST 24
Finished	Feb 04 03:06:56 PM PST 24
Peak memory	240360 kb
Host	smart-2ec0ae05-15e2-4653-adb5-841060e0c7b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3678062223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.3678062223 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_burst_write/latest

Test location	/workspace/coverage/default/49.kmac_entropy_refresh.2281655605
Short name	T536
Test name
Test status
Simulation time	2848363512 ps
CPU time	42.94 seconds
Started	Feb 04 03:00:33 PM PST 24
Finished	Feb 04 03:01:17 PM PST 24
Peak memory	228840 kb
Host	smart-b2e60a39-cdea-4d00-ba9e-0f65851e3cff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2281655605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.2281655605 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/49.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/49.kmac_error.1819705968
Short name	T378
Test name
Test status
Simulation time	12510726264 ps
CPU time	431.84 seconds
Started	Feb 04 03:00:37 PM PST 24
Finished	Feb 04 03:07:50 PM PST 24
Peak memory	275696 kb
Host	smart-c7faeaf3-3013-45fb-899c-d94aae7b7556
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1819705968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.1819705968 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_error/latest

Test location	/workspace/coverage/default/49.kmac_key_error.2439566656
Short name	T303
Test name
Test status
Simulation time	3984014147 ps
CPU time	6.16 seconds
Started	Feb 04 03:00:37 PM PST 24
Finished	Feb 04 03:00:44 PM PST 24
Peak memory	218676 kb
Host	smart-eeffd42d-a8ff-4a52-99ac-29131b721da8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2439566656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.2439566656 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_key_error/latest

Test location	/workspace/coverage/default/49.kmac_lc_escalation.3605343261
Short name	T1128
Test name
Test status
Simulation time	110394994 ps
CPU time	1.37 seconds
Started	Feb 04 03:00:39 PM PST 24
Finished	Feb 04 03:00:42 PM PST 24
Peak memory	219928 kb
Host	smart-ad9161e7-67d3-4d2c-9d5b-aa0ce1aca24f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3605343261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.3605343261 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/49.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/49.kmac_sideload.840896892
Short name	T293
Test name
Test status
Simulation time	8258169540 ps
CPU time	227.91 seconds
Started	Feb 04 02:59:57 PM PST 24
Finished	Feb 04 03:03:47 PM PST 24
Peak memory	242060 kb
Host	smart-83a962c8-cf26-4bbc-80dd-e382fef326d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=840896892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.840896892 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_sideload/latest

Test location	/workspace/coverage/default/49.kmac_smoke.1195581600
Short name	T183
Test name
Test status
Simulation time	3092044221 ps
CPU time	61.7 seconds
Started	Feb 04 02:59:51 PM PST 24
Finished	Feb 04 03:00:54 PM PST 24
Peak memory	224344 kb
Host	smart-41f27794-28eb-426b-a990-c3a0f918aa4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1195581600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.1195581600 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_smoke/latest

Test location	/workspace/coverage/default/49.kmac_stress_all.2717255991
Short name	T807
Test name
Test status
Simulation time	107155266926 ps
CPU time	3144.09 seconds
Started	Feb 04 03:00:38 PM PST 24
Finished	Feb 04 03:53:05 PM PST 24
Peak memory	424128 kb
Host	smart-71cb7381-a1f6-4794-84d3-415ec1e11d8c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2717255991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.2717255991 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_stress_all/latest

Test location	/workspace/coverage/default/49.kmac_stress_all_with_rand_reset.2525364191
Short name	T434
Test name
Test status
Simulation time	72050219148 ps
CPU time	2866.68 seconds
Started	Feb 04 03:00:39 PM PST 24
Finished	Feb 04 03:48:29 PM PST 24
Peak memory	352884 kb
Host	smart-13f43aa4-ade6-4fdc-9565-8688557fdf5e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2525364191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all_with_rand_reset.2525364191 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_kmac.2238157214
Short name	T266
Test name
Test status
Simulation time	1417147663 ps
CPU time	6.81 seconds
Started	Feb 04 03:00:31 PM PST 24
Finished	Feb 04 03:00:39 PM PST 24
Peak memory	220264 kb
Host	smart-4cd89f1c-d986-481b-9f38-ce9a403fd73a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238157214 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 49.kmac_test_vectors_kmac.2238157214 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_kmac_xof.4228443199
Short name	T315
Test name
Test status
Simulation time	517079507 ps
CPU time	7.02 seconds
Started	Feb 04 03:00:35 PM PST 24
Finished	Feb 04 03:00:43 PM PST 24
Peak memory	218652 kb
Host	smart-3d85ba08-7348-424c-9c36-c747da09c7ba
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228443199 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_kmac_xof.4228443199 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_224.2555447037
Short name	T884
Test name
Test status
Simulation time	84985319687 ps
CPU time	2367.62 seconds
Started	Feb 04 03:00:13 PM PST 24
Finished	Feb 04 03:39:42 PM PST 24
Peak memory	394408 kb
Host	smart-3ec96cbb-2381-4d4a-a4ab-db3f05b177ae
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2555447037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.2555447037 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_256.2223736186
Short name	T1083
Test name
Test status
Simulation time	116674073760 ps
CPU time	2327.06 seconds
Started	Feb 04 03:00:13 PM PST 24
Finished	Feb 04 03:39:01 PM PST 24
Peak memory	396104 kb
Host	smart-9604eb6a-c73b-477d-8bd2-08b9b350e6c0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2223736186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.2223736186 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_384.501165979
Short name	T1120
Test name
Test status
Simulation time	15182245320 ps
CPU time	1541.73 seconds
Started	Feb 04 03:00:10 PM PST 24
Finished	Feb 04 03:25:53 PM PST 24
Peak memory	340832 kb
Host	smart-fba35f4f-60b4-4628-b8dc-98c2f5b466ca
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=501165979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.501165979 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_512.4165871771
Short name	T952
Test name
Test status
Simulation time	205324593300 ps
CPU time	1331.59 seconds
Started	Feb 04 03:00:19 PM PST 24
Finished	Feb 04 03:22:32 PM PST 24
Peak memory	302260 kb
Host	smart-bedce9bc-e612-4617-a584-4b3a2b516aef
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4165871771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.4165871771 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_shake_128.615003581
Short name	T1125
Test name
Test status
Simulation time	566500373779 ps
CPU time	6482.61 seconds
Started	Feb 04 03:00:35 PM PST 24
Finished	Feb 04 04:48:40 PM PST 24
Peak memory	656104 kb
Host	smart-9bf410e2-763f-42e4-8125-7b90b2a72a1d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=615003581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.615003581 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_shake_256.4010401968
Short name	T288
Test name
Test status
Simulation time	438381328093 ps
CPU time	5026.07 seconds
Started	Feb 04 03:00:26 PM PST 24
Finished	Feb 04 04:24:16 PM PST 24
Peak memory	571080 kb
Host	smart-4da2aa50-7adf-459c-a102-0a97257b6a7f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4010401968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.4010401968 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/5.kmac_alert_test.1652406291
Short name	T706
Test name
Test status
Simulation time	190646749 ps
CPU time	0.86 seconds
Started	Feb 04 02:45:13 PM PST 24
Finished	Feb 04 02:45:31 PM PST 24
Peak memory	219460 kb
Host	smart-82657242-55e8-4fe6-b637-69bb05bee2ac
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652406291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.1652406291 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_alert_test/latest

Test location	/workspace/coverage/default/5.kmac_app.1894115842
Short name	T317
Test name
Test status
Simulation time	5361124804 ps
CPU time	329.14 seconds
Started	Feb 04 02:45:11 PM PST 24
Finished	Feb 04 02:50:59 PM PST 24
Peak memory	255184 kb
Host	smart-39f16c00-42b7-42e1-9433-8cfaf1bec0d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1894115842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.1894115842 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_app/latest

Test location	/workspace/coverage/default/5.kmac_app_with_partial_data.3212657656
Short name	T1050
Test name
Test status
Simulation time	10282212364 ps
CPU time	193.69 seconds
Started	Feb 04 02:45:08 PM PST 24
Finished	Feb 04 02:48:42 PM PST 24
Peak memory	241768 kb
Host	smart-3e00183d-b47f-4dc7-8f73-67b928a74c05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3212657656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.3212657656 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/5.kmac_burst_write.626041822
Short name	T801
Test name
Test status
Simulation time	130791846440 ps
CPU time	456.09 seconds
Started	Feb 04 02:45:09 PM PST 24
Finished	Feb 04 02:53:05 PM PST 24
Peak memory	234580 kb
Host	smart-38608105-bfc1-42e1-9e80-830816314827
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=626041822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.626041822 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_burst_write/latest

Test location	/workspace/coverage/default/5.kmac_edn_timeout_error.479997318
Short name	T741
Test name
Test status
Simulation time	187926700 ps
CPU time	11.34 seconds
Started	Feb 04 02:45:07 PM PST 24
Finished	Feb 04 02:45:39 PM PST 24
Peak memory	239156 kb
Host	smart-5ed5a02e-bb0f-46a1-a60d-e68a7619e01d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=479997318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.479997318 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/5.kmac_entropy_mode_error.1073751106
Short name	T553
Test name
Test status
Simulation time	42727216 ps
CPU time	1.24 seconds
Started	Feb 04 02:45:16 PM PST 24
Finished	Feb 04 02:45:32 PM PST 24
Peak memory	218636 kb
Host	smart-76540a14-4898-4aa7-8f1c-ce768949c89f
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1073751106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.1073751106 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/5.kmac_entropy_ready_error.3611581881
Short name	T40
Test name
Test status
Simulation time	34851109342 ps
CPU time	71.12 seconds
Started	Feb 04 02:45:18 PM PST 24
Finished	Feb 04 02:46:43 PM PST 24
Peak memory	222100 kb
Host	smart-36793990-8b60-4e2c-951e-056284837cfd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3611581881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.3611581881 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/5.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/5.kmac_entropy_refresh.2567989236
Short name	T76
Test name
Test status
Simulation time	87984517636 ps
CPU time	241.56 seconds
Started	Feb 04 02:45:13 PM PST 24
Finished	Feb 04 02:49:32 PM PST 24
Peak memory	243468 kb
Host	smart-b314cf3e-38cc-45f1-b2f7-305395d324c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2567989236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.2567989236 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/5.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/5.kmac_error.1296023341
Short name	T461
Test name
Test status
Simulation time	3564663102 ps
CPU time	115.61 seconds
Started	Feb 04 02:45:06 PM PST 24
Finished	Feb 04 02:47:23 PM PST 24
Peak memory	251720 kb
Host	smart-04b672aa-9eee-47ba-a933-c25d0325149a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1296023341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.1296023341 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_error/latest

Test location	/workspace/coverage/default/5.kmac_key_error.1629710280
Short name	T42
Test name
Test status
Simulation time	895589048 ps
CPU time	3.7 seconds
Started	Feb 04 02:45:18 PM PST 24
Finished	Feb 04 02:45:35 PM PST 24
Peak memory	218644 kb
Host	smart-f01fb81b-be1e-47e2-819a-45fedf674447
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1629710280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.1629710280 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_key_error/latest

Test location	/workspace/coverage/default/5.kmac_lc_escalation.4101536474
Short name	T10
Test name
Test status
Simulation time	225176654 ps
CPU time	6.98 seconds
Started	Feb 04 02:45:17 PM PST 24
Finished	Feb 04 02:45:38 PM PST 24
Peak memory	234460 kb
Host	smart-3f2f0647-7e48-40d7-9300-3f549d3a7f7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4101536474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.4101536474 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/5.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/5.kmac_long_msg_and_output.478790375
Short name	T1097
Test name
Test status
Simulation time	98375804039 ps
CPU time	2517.59 seconds
Started	Feb 04 02:45:12 PM PST 24
Finished	Feb 04 03:27:28 PM PST 24
Peak memory	411344 kb
Host	smart-a0141c9b-f949-4458-83bd-b7c9e3e619f0
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478790375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and _output.478790375 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/5.kmac_mubi.2939340953
Short name	T535
Test name
Test status
Simulation time	750825895 ps
CPU time	16.16 seconds
Started	Feb 04 02:45:13 PM PST 24
Finished	Feb 04 02:45:46 PM PST 24
Peak memory	227440 kb
Host	smart-1df54a2e-ae07-4a09-945e-61062950049e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2939340953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.2939340953 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_mubi/latest

Test location	/workspace/coverage/default/5.kmac_sideload.3789203924
Short name	T878
Test name
Test status
Simulation time	54482446348 ps
CPU time	382.41 seconds
Started	Feb 04 02:45:10 PM PST 24
Finished	Feb 04 02:51:52 PM PST 24
Peak memory	251788 kb
Host	smart-cc1caab6-a2cf-44ad-8e39-79daaccc82c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3789203924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.3789203924 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_sideload/latest

Test location	/workspace/coverage/default/5.kmac_smoke.1936609129
Short name	T309
Test name
Test status
Simulation time	3499275177 ps
CPU time	28.26 seconds
Started	Feb 04 02:45:13 PM PST 24
Finished	Feb 04 02:45:58 PM PST 24
Peak memory	219732 kb
Host	smart-a8eff014-64bf-44e5-871a-b4427486188d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1936609129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.1936609129 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_smoke/latest

Test location	/workspace/coverage/default/5.kmac_stress_all_with_rand_reset.3576433773
Short name	T1093
Test name
Test status
Simulation time	865525776221 ps
CPU time	1488.12 seconds
Started	Feb 04 02:45:09 PM PST 24
Finished	Feb 04 03:10:18 PM PST 24
Peak memory	301380 kb
Host	smart-4ee5a0f1-b791-435f-9ac9-5574ea18c831
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3576433773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_rand_reset.3576433773 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_kmac.1314532751
Short name	T740
Test name
Test status
Simulation time	924105198 ps
CPU time	6.55 seconds
Started	Feb 04 02:45:05 PM PST 24
Finished	Feb 04 02:45:33 PM PST 24
Peak memory	220092 kb
Host	smart-d109a13b-dedf-485d-9b30-2f5e7856bbb9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314532751 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.kmac_test_vectors_kmac.1314532751 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_kmac_xof.3567441560
Short name	T772
Test name
Test status
Simulation time	101327580 ps
CPU time	5.48 seconds
Started	Feb 04 02:45:06 PM PST 24
Finished	Feb 04 02:45:32 PM PST 24
Peak memory	220272 kb
Host	smart-3505b054-6f36-455e-a5fa-2ddfa0eabbd5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567441560 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_kmac_xof.3567441560 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_224.188453376
Short name	T1079
Test name
Test status
Simulation time	38161600786 ps
CPU time	2155.03 seconds
Started	Feb 04 02:45:09 PM PST 24
Finished	Feb 04 03:21:25 PM PST 24
Peak memory	394756 kb
Host	smart-040c8216-9df8-4a0f-95a4-59cfb079bed5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=188453376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.188453376 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_256.3262977074
Short name	T944
Test name
Test status
Simulation time	281795483767 ps
CPU time	2135.75 seconds
Started	Feb 04 02:45:12 PM PST 24
Finished	Feb 04 03:21:06 PM PST 24
Peak memory	396868 kb
Host	smart-b9477825-23d6-4d8f-8d2a-adbe9fd17a49
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3262977074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.3262977074 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_384.2736923256
Short name	T192
Test name
Test status
Simulation time	683316393442 ps
CPU time	1643.86 seconds
Started	Feb 04 02:45:11 PM PST 24
Finished	Feb 04 03:12:54 PM PST 24
Peak memory	341200 kb
Host	smart-c6edbf84-fd67-4b13-b395-8d560c317fe9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2736923256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.2736923256 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_512.2990477644
Short name	T455
Test name
Test status
Simulation time	51456751276 ps
CPU time	1417.79 seconds
Started	Feb 04 02:45:20 PM PST 24
Finished	Feb 04 03:09:10 PM PST 24
Peak memory	303072 kb
Host	smart-bd54e119-4438-4eb9-b4cb-c32b5ed45d83
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2990477644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.2990477644 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_shake_128.445940652
Short name	T744
Test name
Test status
Simulation time	60675085435 ps
CPU time	5180.2 seconds
Started	Feb 04 02:45:07 PM PST 24
Finished	Feb 04 04:11:48 PM PST 24
Peak memory	664588 kb
Host	smart-26bbf0ef-1d21-4ad8-9518-c28b65d34492
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=445940652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.445940652 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_shake_256.1495285028
Short name	T600
Test name
Test status
Simulation time	55261640334 ps
CPU time	4710.41 seconds
Started	Feb 04 02:45:17 PM PST 24
Finished	Feb 04 04:04:02 PM PST 24
Peak memory	571612 kb
Host	smart-87d13bed-d491-4be0-9348-192de50a2d8b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1495285028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.1495285028 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/6.kmac_alert_test.1691988532
Short name	T827
Test name
Test status
Simulation time	33772770 ps
CPU time	0.95 seconds
Started	Feb 04 02:45:40 PM PST 24
Finished	Feb 04 02:45:44 PM PST 24
Peak memory	219524 kb
Host	smart-bc09f87e-5d3c-4beb-b67d-3e75c966c542
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691988532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.1691988532 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_alert_test/latest

Test location	/workspace/coverage/default/6.kmac_app.1499175858
Short name	T702
Test name
Test status
Simulation time	8535253576 ps
CPU time	146.06 seconds
Started	Feb 04 02:45:30 PM PST 24
Finished	Feb 04 02:48:02 PM PST 24
Peak memory	243412 kb
Host	smart-9f2317e4-d1eb-49d5-bb5f-9368e911b828
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1499175858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.1499175858 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_app/latest

Test location	/workspace/coverage/default/6.kmac_app_with_partial_data.3601275640
Short name	T965
Test name
Test status
Simulation time	1625747823 ps
CPU time	52.54 seconds
Started	Feb 04 02:45:43 PM PST 24
Finished	Feb 04 02:46:41 PM PST 24
Peak memory	230044 kb
Host	smart-375d6314-c42b-4a62-94ba-ae9652721aa5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3601275640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.3601275640 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/6.kmac_burst_write.3039038528
Short name	T470
Test name
Test status
Simulation time	44639396439 ps
CPU time	1026.96 seconds
Started	Feb 04 02:45:11 PM PST 24
Finished	Feb 04 03:02:37 PM PST 24
Peak memory	238924 kb
Host	smart-fd3a51e1-3618-4cc0-9bcb-27e4fd79e6b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3039038528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.3039038528 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_burst_write/latest

Test location	/workspace/coverage/default/6.kmac_edn_timeout_error.839626339
Short name	T809
Test name
Test status
Simulation time	23361242 ps
CPU time	1.03 seconds
Started	Feb 04 02:45:35 PM PST 24
Finished	Feb 04 02:45:39 PM PST 24
Peak memory	218496 kb
Host	smart-c81f61ba-3fe4-485a-97f8-4a0ce5ab28a1
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=839626339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.839626339 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/6.kmac_entropy_mode_error.3124649791
Short name	T739
Test name
Test status
Simulation time	52334736 ps
CPU time	1.13 seconds
Started	Feb 04 02:45:31 PM PST 24
Finished	Feb 04 02:45:37 PM PST 24
Peak memory	218664 kb
Host	smart-23a56c20-ef6d-4c5a-a179-5bfc72809e6d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3124649791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.3124649791 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/6.kmac_entropy_ready_error.1054292244
Short name	T1011
Test name
Test status
Simulation time	3127830555 ps
CPU time	43.6 seconds
Started	Feb 04 02:45:29 PM PST 24
Finished	Feb 04 02:46:19 PM PST 24
Peak memory	220756 kb
Host	smart-1dcf34c7-e442-4b65-ae8b-f65daef2b897
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1054292244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.1054292244 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/6.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/6.kmac_entropy_refresh.3113176921
Short name	T377
Test name
Test status
Simulation time	10908791973 ps
CPU time	57.71 seconds
Started	Feb 04 02:45:40 PM PST 24
Finished	Feb 04 02:46:41 PM PST 24
Peak memory	230928 kb
Host	smart-c1fe6b1b-04c1-43d3-8da2-16667a7246ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3113176921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.3113176921 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/6.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/6.kmac_error.897877198
Short name	T971
Test name
Test status
Simulation time	26260804292 ps
CPU time	315.24 seconds
Started	Feb 04 02:45:34 PM PST 24
Finished	Feb 04 02:50:53 PM PST 24
Peak memory	259448 kb
Host	smart-4525b1fe-598e-4749-964f-7c1ef2c8ad52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=897877198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.897877198 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_error/latest

Test location	/workspace/coverage/default/6.kmac_key_error.571417372
Short name	T446
Test name
Test status
Simulation time	383813512 ps
CPU time	2.56 seconds
Started	Feb 04 02:45:29 PM PST 24
Finished	Feb 04 02:45:38 PM PST 24
Peak memory	218616 kb
Host	smart-0f052bc1-8755-430d-b435-29dc0341facc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=571417372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.571417372 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_key_error/latest

Test location	/workspace/coverage/default/6.kmac_lc_escalation.3273853098
Short name	T99
Test name
Test status
Simulation time	443683685 ps
CPU time	1.54 seconds
Started	Feb 04 02:45:43 PM PST 24
Finished	Feb 04 02:45:50 PM PST 24
Peak memory	220432 kb
Host	smart-30efe071-cef0-4f16-bdc5-32e4448e05c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3273853098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.3273853098 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/6.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/6.kmac_long_msg_and_output.1302052074
Short name	T916
Test name
Test status
Simulation time	36325257992 ps
CPU time	3013.57 seconds
Started	Feb 04 02:45:08 PM PST 24
Finished	Feb 04 03:35:42 PM PST 24
Peak memory	480520 kb
Host	smart-8da43dc9-cf94-4cad-9466-31b365bce6a8
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302052074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an d_output.1302052074 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/6.kmac_mubi.1379006814
Short name	T646
Test name
Test status
Simulation time	42779380235 ps
CPU time	277.81 seconds
Started	Feb 04 02:45:42 PM PST 24
Finished	Feb 04 02:50:26 PM PST 24
Peak memory	248208 kb
Host	smart-c9178b1a-211a-4007-8f59-ef85089c1bcb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1379006814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.1379006814 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_mubi/latest

Test location	/workspace/coverage/default/6.kmac_sideload.3036231578
Short name	T903
Test name
Test status
Simulation time	17943164921 ps
CPU time	121.73 seconds
Started	Feb 04 02:45:16 PM PST 24
Finished	Feb 04 02:47:33 PM PST 24
Peak memory	233496 kb
Host	smart-593407df-0041-4d97-8420-1d3705ceb781
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3036231578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.3036231578 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_sideload/latest

Test location	/workspace/coverage/default/6.kmac_smoke.2088917065
Short name	T185
Test name
Test status
Simulation time	1140476153 ps
CPU time	43.52 seconds
Started	Feb 04 02:45:20 PM PST 24
Finished	Feb 04 02:46:16 PM PST 24
Peak memory	226956 kb
Host	smart-5d18c6cc-2570-466e-b8f7-794ce01c0d92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2088917065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.2088917065 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_smoke/latest

Test location	/workspace/coverage/default/6.kmac_stress_all.1318389997
Short name	T13
Test name
Test status
Simulation time	161943349995 ps
CPU time	1194.73 seconds
Started	Feb 04 02:45:28 PM PST 24
Finished	Feb 04 03:05:30 PM PST 24
Peak memory	317520 kb
Host	smart-79f8e546-feb2-439e-a552-4b87f6326e39
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1318389997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.1318389997 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_stress_all/latest

Test location	/workspace/coverage/default/6.kmac_stress_all_with_rand_reset.344533997
Short name	T1124
Test name
Test status
Simulation time	212252516523 ps
CPU time	524.97 seconds
Started	Feb 04 02:45:33 PM PST 24
Finished	Feb 04 02:54:21 PM PST 24
Peak memory	261240 kb
Host	smart-01eea595-3efa-41e1-a93d-e26d3e05fcf6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=344533997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_with_rand_reset.344533997 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_kmac.2468468105
Short name	T426
Test name
Test status
Simulation time	888714262 ps
CPU time	6.15 seconds
Started	Feb 04 02:45:37 PM PST 24
Finished	Feb 04 02:45:46 PM PST 24
Peak memory	218924 kb
Host	smart-147b643e-29f6-4d3c-842a-00f6b6f14efb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468468105 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.kmac_test_vectors_kmac.2468468105 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_kmac_xof.3464479000
Short name	T1133
Test name
Test status
Simulation time	818334707 ps
CPU time	6.86 seconds
Started	Feb 04 02:45:29 PM PST 24
Finished	Feb 04 02:45:42 PM PST 24
Peak memory	220128 kb
Host	smart-9e587284-74d9-40a7-b12f-8f28f17e97a7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464479000 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_kmac_xof.3464479000 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_224.3871699839
Short name	T749
Test name
Test status
Simulation time	39847026681 ps
CPU time	1907.14 seconds
Started	Feb 04 02:45:16 PM PST 24
Finished	Feb 04 03:17:18 PM PST 24
Peak memory	402448 kb
Host	smart-72fcba35-6653-47ce-9da8-9221bc580ecd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3871699839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.3871699839 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_256.3448221180
Short name	T984
Test name
Test status
Simulation time	19104658608 ps
CPU time	2023.3 seconds
Started	Feb 04 02:45:11 PM PST 24
Finished	Feb 04 03:19:13 PM PST 24
Peak memory	376044 kb
Host	smart-12eaefe7-4ff5-4132-b5c8-988bb4a8b98c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3448221180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.3448221180 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_384.276811832
Short name	T24
Test name
Test status
Simulation time	191444343796 ps
CPU time	1816.22 seconds
Started	Feb 04 02:45:16 PM PST 24
Finished	Feb 04 03:15:47 PM PST 24
Peak memory	343828 kb
Host	smart-79ddbc45-e88e-480b-92ff-fb706245558a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=276811832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.276811832 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_512.2547168561
Short name	T895
Test name
Test status
Simulation time	32253544320 ps
CPU time	1191.32 seconds
Started	Feb 04 02:45:16 PM PST 24
Finished	Feb 04 03:05:22 PM PST 24
Peak memory	295368 kb
Host	smart-7386608f-469f-4f71-92a8-195a0c31c169
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2547168561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.2547168561 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_shake_128.69792582
Short name	T225
Test name
Test status
Simulation time	2003735124653 ps
CPU time	6533.7 seconds
Started	Feb 04 02:45:10 PM PST 24
Finished	Feb 04 04:34:24 PM PST 24
Peak memory	660888 kb
Host	smart-7f9d4708-8e6a-4c2b-97ef-aad9f57adb54
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=69792582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.69792582 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_shake_256.525110294
Short name	T1029
Test name
Test status
Simulation time	976337162769 ps
CPU time	5503.03 seconds
Started	Feb 04 02:45:09 PM PST 24
Finished	Feb 04 04:17:13 PM PST 24
Peak memory	574644 kb
Host	smart-e02761c5-761a-4345-b4d3-a0b97f97e1cc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=525110294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.525110294 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/7.kmac_alert_test.3656458474
Short name	T938
Test name
Test status
Simulation time	98691200 ps
CPU time	0.87 seconds
Started	Feb 04 02:45:42 PM PST 24
Finished	Feb 04 02:45:49 PM PST 24
Peak memory	218388 kb
Host	smart-51fdcf5f-6850-4697-bc30-9d1771cbc4f7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656458474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.3656458474 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_alert_test/latest

Test location	/workspace/coverage/default/7.kmac_app.3330928216
Short name	T1089
Test name
Test status
Simulation time	2499182527 ps
CPU time	21.74 seconds
Started	Feb 04 02:45:26 PM PST 24
Finished	Feb 04 02:45:56 PM PST 24
Peak memory	232364 kb
Host	smart-3e7ebd98-b92d-4c53-af61-cee90a6b35b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3330928216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.3330928216 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_app/latest

Test location	/workspace/coverage/default/7.kmac_app_with_partial_data.3082399159
Short name	T866
Test name
Test status
Simulation time	61347270175 ps
CPU time	325.18 seconds
Started	Feb 04 02:45:43 PM PST 24
Finished	Feb 04 02:51:14 PM PST 24
Peak memory	247696 kb
Host	smart-972425f6-4de0-484a-89e4-52465ebc78c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3082399159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.3082399159 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/7.kmac_burst_write.1124124461
Short name	T270
Test name
Test status
Simulation time	59281662263 ps
CPU time	965.69 seconds
Started	Feb 04 02:45:38 PM PST 24
Finished	Feb 04 03:01:46 PM PST 24
Peak memory	238260 kb
Host	smart-40a7e914-655c-4c52-8154-2643c459fd27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1124124461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.1124124461 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_burst_write/latest

Test location	/workspace/coverage/default/7.kmac_edn_timeout_error.876255769
Short name	T287
Test name
Test status
Simulation time	20797572 ps
CPU time	1.09 seconds
Started	Feb 04 02:45:29 PM PST 24
Finished	Feb 04 02:45:36 PM PST 24
Peak memory	218776 kb
Host	smart-e89c2468-8772-492e-b6a4-f40bb6440c0f
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=876255769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.876255769 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/7.kmac_entropy_mode_error.2046317031
Short name	T85
Test name
Test status
Simulation time	36620290 ps
CPU time	0.88 seconds
Started	Feb 04 02:45:34 PM PST 24
Finished	Feb 04 02:45:38 PM PST 24
Peak memory	218440 kb
Host	smart-760ef839-e6d9-448e-8230-8575416c4744
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2046317031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.2046317031 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/7.kmac_entropy_ready_error.3725919078
Short name	T424
Test name
Test status
Simulation time	3825952183 ps
CPU time	44.97 seconds
Started	Feb 04 02:45:33 PM PST 24
Finished	Feb 04 02:46:22 PM PST 24
Peak memory	219784 kb
Host	smart-c8f0a5dd-19fe-4d04-9dd2-19df002298da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3725919078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.3725919078 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/7.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/7.kmac_entropy_refresh.927412842
Short name	T385
Test name
Test status
Simulation time	90090607343 ps
CPU time	287.13 seconds
Started	Feb 04 02:45:27 PM PST 24
Finished	Feb 04 02:50:21 PM PST 24
Peak memory	250484 kb
Host	smart-7cccd703-b94e-49e8-936a-76ae607ae780
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=927412842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.927412842 +enable_masking=1 +sw_ key_masked=0
Directory	/workspace/7.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/7.kmac_error.4146111045
Short name	T583
Test name
Test status
Simulation time	333339251 ps
CPU time	4.67 seconds
Started	Feb 04 02:45:32 PM PST 24
Finished	Feb 04 02:45:41 PM PST 24
Peak memory	226344 kb
Host	smart-cdd98038-22cc-479a-8da9-2c2356f8db4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4146111045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.4146111045 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_error/latest

Test location	/workspace/coverage/default/7.kmac_key_error.2253778546
Short name	T957
Test name
Test status
Simulation time	1692939248 ps
CPU time	3.24 seconds
Started	Feb 04 02:45:30 PM PST 24
Finished	Feb 04 02:45:39 PM PST 24
Peak memory	218772 kb
Host	smart-f24c44a7-d0a5-4d0b-840b-8f749d9f226a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2253778546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.2253778546 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_key_error/latest

Test location	/workspace/coverage/default/7.kmac_lc_escalation.1666811292
Short name	T996
Test name
Test status
Simulation time	5136079135 ps
CPU time	22.56 seconds
Started	Feb 04 02:45:31 PM PST 24
Finished	Feb 04 02:45:59 PM PST 24
Peak memory	235312 kb
Host	smart-58e73206-1798-4f40-a346-d042d3ee5ef5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1666811292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1666811292 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/7.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/7.kmac_long_msg_and_output.2029889518
Short name	T578
Test name
Test status
Simulation time	230567067282 ps
CPU time	2018.59 seconds
Started	Feb 04 02:45:30 PM PST 24
Finished	Feb 04 03:19:14 PM PST 24
Peak memory	389884 kb
Host	smart-940b8878-62cb-41e1-aa14-0bc5ad704b1b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029889518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an d_output.2029889518 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/7.kmac_mubi.1560318590
Short name	T20
Test name
Test status
Simulation time	13537571857 ps
CPU time	209.66 seconds
Started	Feb 04 02:45:40 PM PST 24
Finished	Feb 04 02:49:16 PM PST 24
Peak memory	246212 kb
Host	smart-70198cc9-5d75-4bd3-ac4f-cae002cd37e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1560318590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.1560318590 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_mubi/latest

Test location	/workspace/coverage/default/7.kmac_sideload.1667099691
Short name	T661
Test name
Test status
Simulation time	327793549 ps
CPU time	9.14 seconds
Started	Feb 04 02:45:34 PM PST 24
Finished	Feb 04 02:45:47 PM PST 24
Peak memory	221776 kb
Host	smart-d97fbc16-a808-465d-9047-045064e85d7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1667099691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.1667099691 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_sideload/latest

Test location	/workspace/coverage/default/7.kmac_smoke.805324651
Short name	T924
Test name
Test status
Simulation time	715613940 ps
CPU time	31.5 seconds
Started	Feb 04 02:45:35 PM PST 24
Finished	Feb 04 02:46:10 PM PST 24
Peak memory	227004 kb
Host	smart-cd337c6f-6f32-447c-8c7f-bbb4e488b787
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=805324651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.805324651 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_smoke/latest

Test location	/workspace/coverage/default/7.kmac_stress_all.2304377
Short name	T1013
Test name
Test status
Simulation time	20526218199 ps
CPU time	1666.77 seconds
Started	Feb 04 02:45:31 PM PST 24
Finished	Feb 04 03:13:23 PM PST 24
Peak memory	423956 kb
Host	smart-63f8ab3c-6faf-4c88-b864-d3fc04d28cd3
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2304377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.2304377 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_stress_all/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_kmac.1530294850
Short name	T664
Test name
Test status
Simulation time	275801447 ps
CPU time	6.26 seconds
Started	Feb 04 02:45:36 PM PST 24
Finished	Feb 04 02:45:46 PM PST 24
Peak memory	218732 kb
Host	smart-a1e73bac-4b24-4a4d-974c-8ee41877a33a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530294850 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.kmac_test_vectors_kmac.1530294850 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_kmac_xof.564250626
Short name	T777
Test name
Test status
Simulation time	278461461 ps
CPU time	7.2 seconds
Started	Feb 04 02:45:29 PM PST 24
Finished	Feb 04 02:45:43 PM PST 24
Peak memory	218868 kb
Host	smart-586ea284-4c38-45a2-8aee-4f644f18c253
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564250626 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 7.kmac_test_vectors_kmac_xof.564250626 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_224.1335641846
Short name	T781
Test name
Test status
Simulation time	62221827664 ps
CPU time	1908.21 seconds
Started	Feb 04 02:45:24 PM PST 24
Finished	Feb 04 03:17:22 PM PST 24
Peak memory	386872 kb
Host	smart-0f121a98-d413-4ce4-a9eb-178a42c0f0fe
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1335641846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.1335641846 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_256.2839605999
Short name	T891
Test name
Test status
Simulation time	44101621595 ps
CPU time	2120.53 seconds
Started	Feb 04 02:45:40 PM PST 24
Finished	Feb 04 03:21:06 PM PST 24
Peak memory	389420 kb
Host	smart-94512c60-4b78-44ea-a972-7ad5e05089df
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2839605999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.2839605999 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_384.3348908814
Short name	T1010
Test name
Test status
Simulation time	58608598012 ps
CPU time	1643.94 seconds
Started	Feb 04 02:45:33 PM PST 24
Finished	Feb 04 03:13:01 PM PST 24
Peak memory	339364 kb
Host	smart-303722bb-2900-4bbb-a4ce-38834e2f365b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3348908814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.3348908814 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_512.1312210009
Short name	T917
Test name
Test status
Simulation time	21365942863 ps
CPU time	1193.31 seconds
Started	Feb 04 02:45:38 PM PST 24
Finished	Feb 04 03:05:34 PM PST 24
Peak memory	302176 kb
Host	smart-fd39f674-a3b9-41f3-bf2b-038a3b66191a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1312210009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.1312210009 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_shake_128.2996665298
Short name	T203
Test name
Test status
Simulation time	72861277578 ps
CPU time	5935.9 seconds
Started	Feb 04 02:45:34 PM PST 24
Finished	Feb 04 04:24:35 PM PST 24
Peak memory	650900 kb
Host	smart-4f1a743c-25af-4b2e-befa-8ccbc6fca736
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2996665298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.2996665298 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_shake_256.2548929415
Short name	T337
Test name
Test status
Simulation time	311218754768 ps
CPU time	5254.33 seconds
Started	Feb 04 02:45:30 PM PST 24
Finished	Feb 04 04:13:10 PM PST 24
Peak memory	567956 kb
Host	smart-3dbcbc9b-1690-4cbb-8be8-8c1a75d1e87d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2548929415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.2548929415 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/8.kmac_alert_test.1929616473
Short name	T258
Test name
Test status
Simulation time	43198248 ps
CPU time	0.79 seconds
Started	Feb 04 02:45:40 PM PST 24
Finished	Feb 04 02:45:45 PM PST 24
Peak memory	218296 kb
Host	smart-f77d3fc0-a445-4fd9-9532-0ae5004278d6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929616473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.1929616473 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_alert_test/latest

Test location	/workspace/coverage/default/8.kmac_app.124066212
Short name	T1061
Test name
Test status
Simulation time	3423669501 ps
CPU time	19.86 seconds
Started	Feb 04 02:45:42 PM PST 24
Finished	Feb 04 02:46:08 PM PST 24
Peak memory	227148 kb
Host	smart-fc2fb2a3-bc57-4cc6-9aee-06e150aab4fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=124066212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.124066212 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_app/latest

Test location	/workspace/coverage/default/8.kmac_app_with_partial_data.3752906780
Short name	T531
Test name
Test status
Simulation time	1941517759 ps
CPU time	10.47 seconds
Started	Feb 04 02:45:28 PM PST 24
Finished	Feb 04 02:45:45 PM PST 24
Peak memory	220128 kb
Host	smart-4f85bfcd-8a9e-4d6b-8551-9a5d17eb5e2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3752906780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.3752906780 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/8.kmac_burst_write.2959045579
Short name	T587
Test name
Test status
Simulation time	8389968232 ps
CPU time	73.61 seconds
Started	Feb 04 02:45:27 PM PST 24
Finished	Feb 04 02:46:48 PM PST 24
Peak memory	233436 kb
Host	smart-de587176-8bd7-4174-aaec-40063f88127b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2959045579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.2959045579 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_burst_write/latest

Test location	/workspace/coverage/default/8.kmac_edn_timeout_error.1486595146
Short name	T435
Test name
Test status
Simulation time	1246826680 ps
CPU time	8.77 seconds
Started	Feb 04 02:45:41 PM PST 24
Finished	Feb 04 02:45:55 PM PST 24
Peak memory	236972 kb
Host	smart-fc0b9b2e-9f39-4134-b8a8-1b0ea68789d1
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1486595146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.1486595146 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/8.kmac_entropy_mode_error.1105787334
Short name	T84
Test name
Test status
Simulation time	25491249 ps
CPU time	1.11 seconds
Started	Feb 04 02:45:40 PM PST 24
Finished	Feb 04 02:45:46 PM PST 24
Peak memory	218600 kb
Host	smart-0da017c3-cef5-48ed-b035-2c7110eb3039
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1105787334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.1105787334 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/8.kmac_entropy_ready_error.319352157
Short name	T38
Test name
Test status
Simulation time	1401256932 ps
CPU time	24.78 seconds
Started	Feb 04 02:45:38 PM PST 24
Finished	Feb 04 02:46:05 PM PST 24
Peak memory	227088 kb
Host	smart-13afde37-ac3c-4c87-bbf1-d7c8c5113edc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=319352157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.319352157 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspace/8.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/8.kmac_entropy_refresh.4121798588
Short name	T1085
Test name
Test status
Simulation time	2479529657 ps
CPU time	34.13 seconds
Started	Feb 04 02:45:42 PM PST 24
Finished	Feb 04 02:46:22 PM PST 24
Peak memory	226936 kb
Host	smart-e6a24f94-a136-4588-a604-0c27ac8a31e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4121798588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.4121798588 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/8.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/8.kmac_error.4194091036
Short name	T923
Test name
Test status
Simulation time	2289211329 ps
CPU time	192.64 seconds
Started	Feb 04 02:45:42 PM PST 24
Finished	Feb 04 02:49:01 PM PST 24
Peak memory	251612 kb
Host	smart-dad32cdd-e1b0-47ad-ac88-a0e53cc68e13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4194091036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.4194091036 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_error/latest

Test location	/workspace/coverage/default/8.kmac_key_error.2624229657
Short name	T39
Test name
Test status
Simulation time	2212394808 ps
CPU time	6.73 seconds
Started	Feb 04 02:45:25 PM PST 24
Finished	Feb 04 02:45:40 PM PST 24
Peak memory	218620 kb
Host	smart-6fc0e15b-45d4-4b0e-b0fd-b0075371aeb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2624229657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.2624229657 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_key_error/latest

Test location	/workspace/coverage/default/8.kmac_lc_escalation.967672286
Short name	T413
Test name
Test status
Simulation time	163159355 ps
CPU time	1.42 seconds
Started	Feb 04 02:45:42 PM PST 24
Finished	Feb 04 02:45:50 PM PST 24
Peak memory	219724 kb
Host	smart-b41a1f28-b047-4e4a-bc62-69406ff69161
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=967672286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.967672286 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/8.kmac_long_msg_and_output.4069956536
Short name	T227
Test name
Test status
Simulation time	63035223747 ps
CPU time	2417.52 seconds
Started	Feb 04 02:45:33 PM PST 24
Finished	Feb 04 03:25:55 PM PST 24
Peak memory	407256 kb
Host	smart-a7a15688-acb3-4d0c-b234-bbe960960eea
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069956536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an d_output.4069956536 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/8.kmac_mubi.537184198
Short name	T415
Test name
Test status
Simulation time	4534839391 ps
CPU time	211.28 seconds
Started	Feb 04 02:45:33 PM PST 24
Finished	Feb 04 02:49:09 PM PST 24
Peak memory	241952 kb
Host	smart-688ce2bb-c5b3-4819-aae9-49e7cc60f31b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=537184198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.537184198 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_mubi/latest

Test location	/workspace/coverage/default/8.kmac_sideload.1673686794
Short name	T363
Test name
Test status
Simulation time	5592091990 ps
CPU time	206.23 seconds
Started	Feb 04 02:45:39 PM PST 24
Finished	Feb 04 02:49:07 PM PST 24
Peak memory	242272 kb
Host	smart-cb233879-9c89-45ce-8c5f-5ca123fa1c64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1673686794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.1673686794 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_sideload/latest

Test location	/workspace/coverage/default/8.kmac_smoke.1927627406
Short name	T397
Test name
Test status
Simulation time	1690318830 ps
CPU time	73.48 seconds
Started	Feb 04 02:45:27 PM PST 24
Finished	Feb 04 02:46:48 PM PST 24
Peak memory	226952 kb
Host	smart-bcd3f0ec-db17-4ed8-8b45-5a17c5ba1800
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1927627406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.1927627406 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_smoke/latest

Test location	/workspace/coverage/default/8.kmac_stress_all.2270272728
Short name	T673
Test name
Test status
Simulation time	8769952794 ps
CPU time	521.51 seconds
Started	Feb 04 02:45:42 PM PST 24
Finished	Feb 04 02:54:30 PM PST 24
Peak memory	308500 kb
Host	smart-832485ca-1328-4a49-a7bc-ca100f40bff8
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2270272728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.2270272728 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_stress_all/latest

Test location	/workspace/coverage/default/8.kmac_stress_all_with_rand_reset.3771831947
Short name	T663
Test name
Test status
Simulation time	107001135533 ps
CPU time	905.51 seconds
Started	Feb 04 02:45:34 PM PST 24
Finished	Feb 04 03:00:44 PM PST 24
Peak memory	324464 kb
Host	smart-0bc61b17-3f48-43ed-9c0c-4265a94df268
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3771831947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all_with_rand_reset.3771831947 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_kmac.3750388099
Short name	T474
Test name
Test status
Simulation time	533570186 ps
CPU time	5.6 seconds
Started	Feb 04 02:45:35 PM PST 24
Finished	Feb 04 02:45:44 PM PST 24
Peak memory	218872 kb
Host	smart-297189ed-53f1-45b2-af23-8e7eb569affd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750388099 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.kmac_test_vectors_kmac.3750388099 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_kmac_xof.2407109221
Short name	T735
Test name
Test status
Simulation time	563073606 ps
CPU time	6.74 seconds
Started	Feb 04 02:45:27 PM PST 24
Finished	Feb 04 02:45:41 PM PST 24
Peak memory	220416 kb
Host	smart-6ac58863-9540-4310-b5d1-5e6489064fd3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407109221 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_kmac_xof.2407109221 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_224.1432874988
Short name	T660
Test name
Test status
Simulation time	65968001341 ps
CPU time	2091.73 seconds
Started	Feb 04 02:45:36 PM PST 24
Finished	Feb 04 03:20:31 PM PST 24
Peak memory	392844 kb
Host	smart-f0fa1701-4247-49c3-861c-d0b380c4c3cf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1432874988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.1432874988 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_256.2085075981
Short name	T348
Test name
Test status
Simulation time	130320299168 ps
CPU time	2292.35 seconds
Started	Feb 04 02:45:40 PM PST 24
Finished	Feb 04 03:23:59 PM PST 24
Peak memory	390256 kb
Host	smart-0d59e176-c7bc-4914-a75d-832023fe6fc9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2085075981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.2085075981 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_384.1324255163
Short name	T987
Test name
Test status
Simulation time	15589255605 ps
CPU time	1554.72 seconds
Started	Feb 04 02:45:33 PM PST 24
Finished	Feb 04 03:11:32 PM PST 24
Peak memory	335520 kb
Host	smart-68ca2b84-d705-4290-93a0-efcf6a69dbc4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1324255163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.1324255163 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_512.3823254968
Short name	T171
Test name
Test status
Simulation time	203958970568 ps
CPU time	1515.11 seconds
Started	Feb 04 02:45:40 PM PST 24
Finished	Feb 04 03:11:01 PM PST 24
Peak memory	302680 kb
Host	smart-198d5984-964f-48da-8fd6-6013afcebcbc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3823254968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.3823254968 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_shake_128.3590097004
Short name	T1065
Test name
Test status
Simulation time	154174635122 ps
CPU time	5350.48 seconds
Started	Feb 04 02:45:37 PM PST 24
Finished	Feb 04 04:14:51 PM PST 24
Peak memory	659824 kb
Host	smart-e6c1c24d-9440-4737-b22f-896b95a4200c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3590097004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.3590097004 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_shake_256.708439824
Short name	T695
Test name
Test status
Simulation time	631954672438 ps
CPU time	5426.05 seconds
Started	Feb 04 02:45:30 PM PST 24
Finished	Feb 04 04:16:02 PM PST 24
Peak memory	575848 kb
Host	smart-15279667-d0be-45d1-9615-43cb45de66a7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=708439824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.708439824 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/9.kmac_alert_test.1799412011
Short name	T506
Test name
Test status
Simulation time	32995986 ps
CPU time	0.88 seconds
Started	Feb 04 02:45:39 PM PST 24
Finished	Feb 04 02:45:43 PM PST 24
Peak memory	219504 kb
Host	smart-5396a180-ae1a-4e12-b8cd-9778983af32d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799412011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.1799412011 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_alert_test/latest

Test location	/workspace/coverage/default/9.kmac_app.1906820137
Short name	T433
Test name
Test status
Simulation time	11356690396 ps
CPU time	139.45 seconds
Started	Feb 04 02:45:46 PM PST 24
Finished	Feb 04 02:48:11 PM PST 24
Peak memory	235904 kb
Host	smart-f83404b6-99ba-48a1-8fa9-9af541e4b0ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1906820137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.1906820137 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_app/latest

Test location	/workspace/coverage/default/9.kmac_burst_write.4271676518
Short name	T926
Test name
Test status
Simulation time	32728372507 ps
CPU time	858.86 seconds
Started	Feb 04 02:45:37 PM PST 24
Finished	Feb 04 02:59:59 PM PST 24
Peak memory	236572 kb
Host	smart-e8263987-f653-49af-a0e2-7b5bda64b963
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4271676518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.4271676518 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_burst_write/latest

Test location	/workspace/coverage/default/9.kmac_edn_timeout_error.3130354573
Short name	T78
Test name
Test status
Simulation time	75627127 ps
CPU time	1.12 seconds
Started	Feb 04 02:45:45 PM PST 24
Finished	Feb 04 02:45:52 PM PST 24
Peak memory	218700 kb
Host	smart-6ffe83a2-80c5-4f98-8b30-76c8da3af17e
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3130354573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.3130354573 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/9.kmac_entropy_mode_error.3848851093
Short name	T845
Test name
Test status
Simulation time	57588459 ps
CPU time	1.03 seconds
Started	Feb 04 02:45:41 PM PST 24
Finished	Feb 04 02:45:49 PM PST 24
Peak memory	218556 kb
Host	smart-42577e7e-f1cb-4b22-9f41-e1942daf39dd
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3848851093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.3848851093 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/9.kmac_entropy_ready_error.3258211069
Short name	T565
Test name
Test status
Simulation time	73953688693 ps
CPU time	45.96 seconds
Started	Feb 04 02:45:41 PM PST 24
Finished	Feb 04 02:46:33 PM PST 24
Peak memory	220716 kb
Host	smart-fdf3bf5b-2c4b-46b0-b5b6-fd907f9b3d4b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3258211069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.3258211069 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/9.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/9.kmac_entropy_refresh.2340062213
Short name	T1107
Test name
Test status
Simulation time	196194430194 ps
CPU time	437.72 seconds
Started	Feb 04 02:45:40 PM PST 24
Finished	Feb 04 02:53:03 PM PST 24
Peak memory	254448 kb
Host	smart-998a9e71-f667-4ffd-8fed-fa82f678ee4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2340062213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.2340062213 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/9.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/9.kmac_error.424269709
Short name	T463
Test name
Test status
Simulation time	37372547034 ps
CPU time	319.05 seconds
Started	Feb 04 02:45:42 PM PST 24
Finished	Feb 04 02:51:07 PM PST 24
Peak memory	260104 kb
Host	smart-2a2dad5d-36f5-4c23-bd8e-d3e19ebde2a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=424269709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.424269709 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_error/latest

Test location	/workspace/coverage/default/9.kmac_key_error.2193238992
Short name	T36
Test name
Test status
Simulation time	1078817146 ps
CPU time	3.97 seconds
Started	Feb 04 02:45:28 PM PST 24
Finished	Feb 04 02:45:39 PM PST 24
Peak memory	218536 kb
Host	smart-8221edec-506b-4d2c-bd67-ab0635c944ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2193238992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.2193238992 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_key_error/latest

Test location	/workspace/coverage/default/9.kmac_lc_escalation.1951117532
Short name	T704
Test name
Test status
Simulation time	96419985 ps
CPU time	1.33 seconds
Started	Feb 04 02:45:50 PM PST 24
Finished	Feb 04 02:45:54 PM PST 24
Peak memory	219964 kb
Host	smart-c56cfb39-edcb-4b72-a1b2-202a7e0530e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1951117532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.1951117532 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/9.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/9.kmac_long_msg_and_output.2970409195
Short name	T375
Test name
Test status
Simulation time	213696042379 ps
CPU time	1529.56 seconds
Started	Feb 04 02:45:38 PM PST 24
Finished	Feb 04 03:11:10 PM PST 24
Peak memory	342060 kb
Host	smart-9affc2d5-694b-4dad-8424-c03b6f22606f
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970409195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an d_output.2970409195 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/9.kmac_mubi.2023998423
Short name	T19
Test name
Test status
Simulation time	89021384134 ps
CPU time	173.37 seconds
Started	Feb 04 02:45:46 PM PST 24
Finished	Feb 04 02:48:45 PM PST 24
Peak memory	242100 kb
Host	smart-72b6f093-bda4-4d05-8dcf-5776fa6948ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2023998423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.2023998423 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_mubi/latest

Test location	/workspace/coverage/default/9.kmac_sideload.3138034764
Short name	T343
Test name
Test status
Simulation time	26573113591 ps
CPU time	499.35 seconds
Started	Feb 04 02:45:46 PM PST 24
Finished	Feb 04 02:54:11 PM PST 24
Peak memory	256244 kb
Host	smart-ce91d162-4636-4127-ae5f-36ca47f9f3ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3138034764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.3138034764 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_sideload/latest

Test location	/workspace/coverage/default/9.kmac_smoke.4275713462
Short name	T176
Test name
Test status
Simulation time	3013200619 ps
CPU time	60.01 seconds
Started	Feb 04 02:45:35 PM PST 24
Finished	Feb 04 02:46:38 PM PST 24
Peak memory	219020 kb
Host	smart-0e56d6d3-ed5c-4a47-b303-05bee20fbcec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4275713462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.4275713462 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_smoke/latest

Test location	/workspace/coverage/default/9.kmac_stress_all.821873551
Short name	T747
Test name
Test status
Simulation time	19046931800 ps
CPU time	1552.49 seconds
Started	Feb 04 02:45:43 PM PST 24
Finished	Feb 04 03:11:41 PM PST 24
Peak memory	358580 kb
Host	smart-0a0e49d4-691e-4b61-a362-22eabf0b7e89
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=821873551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.821873551 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_stress_all/latest

Test location	/workspace/coverage/default/9.kmac_stress_all_with_rand_reset.1323021624
Short name	T1130
Test name
Test status
Simulation time	170857860740 ps
CPU time	1142.66 seconds
Started	Feb 04 02:45:43 PM PST 24
Finished	Feb 04 03:04:52 PM PST 24
Peak memory	291504 kb
Host	smart-1121b758-10b3-43a8-b4a8-06b38aef0f4f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1323021624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all_with_rand_reset.1323021624 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_kmac.557089485
Short name	T336
Test name
Test status
Simulation time	538766014 ps
CPU time	5.64 seconds
Started	Feb 04 02:45:35 PM PST 24
Finished	Feb 04 02:45:44 PM PST 24
Peak memory	220072 kb
Host	smart-2f3eaf41-5caf-44e1-a5fd-9405364a20c7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557089485 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 9.kmac_test_vectors_kmac.557089485 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_kmac_xof.45960958
Short name	T951
Test name
Test status
Simulation time	921037620 ps
CPU time	6.54 seconds
Started	Feb 04 02:45:40 PM PST 24
Finished	Feb 04 02:45:52 PM PST 24
Peak memory	218860 kb
Host	smart-ebfe2811-93f7-4ad9-937a-534ad3bb8373
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45960958 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 9.kmac_test_vectors_kmac_xof.45960958 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_224.3340163202
Short name	T213
Test name
Test status
Simulation time	42502995335 ps
CPU time	1909.44 seconds
Started	Feb 04 02:45:35 PM PST 24
Finished	Feb 04 03:17:28 PM PST 24
Peak memory	400016 kb
Host	smart-3b131d50-73d1-4b72-8b4f-6c09b0b6a6d4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3340163202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.3340163202 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_256.461166257
Short name	T275
Test name
Test status
Simulation time	91200991084 ps
CPU time	2341.4 seconds
Started	Feb 04 02:45:47 PM PST 24
Finished	Feb 04 03:24:53 PM PST 24
Peak memory	386500 kb
Host	smart-de5ab76b-9f6e-4048-875f-635813a37868
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=461166257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.461166257 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_384.3931493865
Short name	T817
Test name
Test status
Simulation time	326611251409 ps
CPU time	1953.18 seconds
Started	Feb 04 02:45:42 PM PST 24
Finished	Feb 04 03:18:22 PM PST 24
Peak memory	348060 kb
Host	smart-2c321780-f911-4f52-9066-f336f855cc0f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3931493865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.3931493865 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_512.1278058299
Short name	T492
Test name
Test status
Simulation time	158567322512 ps
CPU time	1404.14 seconds
Started	Feb 04 02:45:34 PM PST 24
Finished	Feb 04 03:09:02 PM PST 24
Peak memory	295888 kb
Host	smart-81c90573-d918-483c-9b6a-708276169db2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1278058299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.1278058299 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_shake_128.4108069631
Short name	T1058
Test name
Test status
Simulation time	700678235869 ps
CPU time	6199.22 seconds
Started	Feb 04 02:45:43 PM PST 24
Finished	Feb 04 04:29:09 PM PST 24
Peak memory	649524 kb
Host	smart-5e5124be-35e5-4c74-aa2f-c74216cd8184
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4108069631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.4108069631 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_shake_256.174489319
Short name	T518
Test name
Test status
Simulation time	310206696513 ps
CPU time	4853.78 seconds
Started	Feb 04 02:45:40 PM PST 24
Finished	Feb 04 04:06:40 PM PST 24
Peak memory	561776 kb
Host	smart-c161656e-4c8f-4f5c-8164-33053f94fff6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=174489319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.174489319 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_shake_256/latest

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%