Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99362693	1			T54	8		T56	5		T59	1
all_values[1]	99362693	1			T54	8		T56	5		T59	1
all_values[2]	99362693	1			T54	8		T56	5		T59	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

653625

1

T54

16

T56

6

T59

3

auto[1]

297434454

1

T54

8

T56

9

T60

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

296560698

1

T54

18

T56

3

T59

3

auto[1]

1527381

1

T54

6

T56

12

T60

9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	222408	1			T54	4		T56	1		T59	1
all_values[0]	auto[0]	auto[1]	2349	1			T54	2		T56	3		T60	2
all_values[0]	auto[1]	auto[0]	98631158	1			T54	2		T105	1		T156	1
all_values[0]	auto[1]	auto[1]	506778	1			T56	1		T60	1		T115	3
all_values[1]	auto[0]	auto[0]	237407	1			T54	5		T59	1		T61	1
all_values[1]	auto[0]	auto[1]	1750	1			T54	2		T56	1		T115	5
all_values[1]	auto[1]	auto[0]	98616159	1			T54	1		T56	1		T60	2
all_values[1]	auto[1]	auto[1]	507377	1			T56	3		T60	3		T115	2
all_values[2]	auto[0]	auto[0]	187979	1			T54	2		T59	1		T60	2
all_values[2]	auto[0]	auto[1]	1732	1			T54	1		T56	1		T60	2
all_values[2]	auto[1]	auto[0]	98665587	1			T54	4		T56	1		T105	2
all_values[2]	auto[1]	auto[1]	507395	1			T54	1		T56	3		T60	1