Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10152	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	8953	1			T4	17		T10	38		T19	43
len_5001_7500	14258	1			T4	17		T10	36		T19	83
len_2501_5000	9164	1			T4	17		T10	36		T19	17
len_1025_2500	5391	1			T4	10		T10	22		T19	6
len_769_1024	6792	1			T4	2		T10	4		T19	28
len_513_768	7189	1			T4	2		T10	4		T19	21
len_257_512	21193	1			T4	2		T10	52		T19	21
len_0_256	256166	1			T4	290		T10	2017		T11	9
len_keccak_block_sizes[72]	717	1			T4	2		T10	3		T21	2
len_keccak_block_sizes[104]	608	1			T4	2		T10	3		T21	2
len_keccak_block_sizes[136]	525	1			T4	2		T10	3		T21	2
len_keccak_block_sizes[144]	415	1			T4	2		T10	3		T21	2
len_keccak_block_sizes[168]	319	1			T10	3		T53	3		T175	1
len_1	758	1			T4	2		T10	3		T21	2
len_0	1227	1			T4	2		T10	3		T19	3