Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99362693	1			T54	8		T56	5		T59	1
all_pins[1]	99362693	1			T54	8		T56	5		T59	1
all_pins[2]	99362693	1			T54	8		T56	5		T59	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	248013946	1			T54	24		T56	12		T59	3
values[0x1]	50074133	1			T56	3		T60	6		T115	6
transitions[0x0=>0x1]	49658243	1			T56	2		T60	3		T115	4
transitions[0x1=>0x0]	49658266	1			T56	2		T60	4		T115	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98855915	1			T54	8		T56	4		T59	1
all_pins[0]	values[0x1]	506778	1			T56	1		T60	1		T115	3
all_pins[0]	transitions[0x0=>0x1]	213356	1			T56	1		T115	3		T156	2
all_pins[0]	transitions[0x1=>0x0]	48958601	1			T60	3		T158	3		T164	1
all_pins[1]	values[0x0]	50110670	1			T54	8		T56	5		T59	1
all_pins[1]	values[0x1]	49252023	1			T60	4		T158	4		T164	2
all_pins[1]	transitions[0x0=>0x1]	49131411	1			T60	3		T158	4		T164	2
all_pins[1]	transitions[0x1=>0x0]	194720	1			T56	2		T115	3		T156	2
all_pins[2]	values[0x0]	99047361	1			T54	8		T56	3		T59	1
all_pins[2]	values[0x1]	315332	1			T56	2		T60	1		T115	3
all_pins[2]	transitions[0x0=>0x1]	313476	1			T56	1		T115	1		T156	1
all_pins[2]	transitions[0x1=>0x0]	504945	1			T60	1		T115	2		T156	1