Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 272 1 T54 7 T56 4 T60 4
all_values[1] 272 1 T54 7 T56 4 T60 4
all_values[2] 272 1 T54 7 T56 4 T60 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 433 1 T54 14 T56 8 T60 6
auto[1] 383 1 T54 7 T56 4 T60 6


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 318 1 T54 13 T56 6 T60 2
auto[1] 498 1 T54 8 T56 6 T60 10


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 490 1 T54 16 T56 8 T60 5
auto[1] 326 1 T54 5 T56 4 T60 7


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 48 1 T54 2 T60 1 T105 3
all_values[0] auto[0] auto[0] auto[1] 41 1 T54 2 T56 1 T60 1
all_values[0] auto[0] auto[1] auto[0] 44 1 T54 2 T157 1 T165 1
all_values[0] auto[0] auto[1] auto[1] 29 1 T156 1 T158 1 T164 1
all_values[0] auto[1] auto[0] auto[1] 65 1 T54 1 T56 3 T60 1
all_values[0] auto[1] auto[1] auto[1] 45 1 T60 1 T115 2 T156 1
all_values[1] auto[0] auto[0] auto[0] 57 1 T54 2 T56 2 T105 4
all_values[1] auto[0] auto[0] auto[1] 30 1 T54 1 T164 1 T166 1
all_values[1] auto[0] auto[1] auto[0] 61 1 T56 2 T115 1 T156 2
all_values[1] auto[0] auto[1] auto[1] 21 1 T60 1 T158 3 T167 1
all_values[1] auto[1] auto[0] auto[1] 50 1 T54 3 T115 1 T156 1
all_values[1] auto[1] auto[1] auto[1] 53 1 T54 1 T60 3 T115 1
all_values[2] auto[0] auto[0] auto[0] 59 1 T54 3 T56 2 T60 1
all_values[2] auto[0] auto[0] auto[1] 28 1 T60 1 T157 1 T158 2
all_values[2] auto[0] auto[1] auto[0] 49 1 T54 4 T105 1 T115 1
all_values[2] auto[0] auto[1] auto[1] 23 1 T56 1 T115 2 T156 1
all_values[2] auto[1] auto[0] auto[1] 55 1 T60 1 T105 2 T115 3
all_values[2] auto[1] auto[1] auto[1] 58 1 T56 1 T60 1 T115 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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