Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101120644	1			T1	465420		T2	4515		T3	2995
all_values[1]	101120644	1			T1	465420		T2	4515		T3	2995
all_values[2]	101120644	1			T1	465420		T2	4515		T3	2995

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

567835

1

T1

6

T2

448

T3

776

auto[1]

302794097

1

T1

139625

T2

13097

T3

8209

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301822725

1

T1

138604

T2

13425

T3

8883

auto[1]

1539207

1

T1

10212

T2

120

T3

102

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	193445	1			T2	236		T3	342		T36	185
all_values[0]	auto[0]	auto[1]	2034	1			T2	4		T3	6		T36	2
all_values[0]	auto[1]	auto[0]	100414130	1			T1	462016		T2	4239		T3	2619
all_values[0]	auto[1]	auto[1]	511035	1			T1	3404		T2	36		T3	28
all_values[1]	auto[0]	auto[0]	193483	1			T1	2		T3	212		T34	23
all_values[1]	auto[0]	auto[1]	1568	1			T1	1		T3	2		T34	1
all_values[1]	auto[1]	auto[0]	100414092	1			T1	462014		T2	4475		T3	2749
all_values[1]	auto[1]	auto[1]	511501	1			T1	3403		T2	40		T3	32
all_values[2]	auto[0]	auto[0]	175810	1			T1	2		T2	206		T3	212
all_values[2]	auto[0]	auto[1]	1495	1			T1	1		T2	2		T3	2
all_values[2]	auto[1]	auto[0]	100431765	1			T1	462014		T2	4269		T3	2749
all_values[2]	auto[1]	auto[1]	511574	1			T1	3403		T2	38		T3	32