Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101120644	1			T1	465420		T2	4515		T3	2995
all_pins[1]	101120644	1			T1	465420		T2	4515		T3	2995
all_pins[2]	101120644	1			T1	465420		T2	4515		T3	2995

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	250372997	1			T1	110827		T2	11495		T3	7849
values[0x1]	52988935	1			T1	287987		T2	2050		T3	1136
transitions[0x0=>0x1]	52569066	1			T1	286595		T2	2016		T3	1111
transitions[0x1=>0x0]	52569095	1			T1	286595		T2	2016		T3	1111

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100609609	1			T1	462016		T2	4479		T3	2967
all_pins[0]	values[0x1]	511035	1			T1	3404		T2	36		T3	28
all_pins[0]	transitions[0x0=>0x1]	216293	1			T1	2012		T2	2		T3	4
all_pins[0]	transitions[0x1=>0x0]	51862608	1			T1	283191		T2	1980		T3	1073
all_pins[1]	values[0x0]	48963294	1			T1	180837		T2	2501		T3	1898
all_pins[1]	values[0x1]	52157350	1			T1	284583		T2	2014		T3	1097
all_pins[1]	transitions[0x0=>0x1]	52034155	1			T1	284583		T2	2014		T3	1096
all_pins[1]	transitions[0x1=>0x0]	197355	1			T3	10		T65	830		T14	1640
all_pins[2]	values[0x0]	100800094	1			T1	465420		T2	4515		T3	2984
all_pins[2]	values[0x1]	320550	1			T3	11		T65	832		T14	2957
all_pins[2]	transitions[0x0=>0x1]	318618	1			T3	11		T65	832		T14	2938
all_pins[2]	transitions[0x1=>0x0]	509132	1			T1	3404		T2	36		T3	28