Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11001947 |
1 |
|
|
T1 |
47900 |
|
T2 |
4850 |
|
T3 |
3679 |
auto[1] |
11001931 |
1 |
|
|
T1 |
47900 |
|
T2 |
4850 |
|
T3 |
3679 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21763046 |
1 |
|
|
T1 |
93928 |
|
T2 |
9658 |
|
T3 |
7332 |
triple_byte_access |
80030 |
1 |
|
|
T1 |
620 |
|
T2 |
20 |
|
T3 |
16 |
halfword_access |
80730 |
1 |
|
|
T1 |
632 |
|
T2 |
10 |
|
T3 |
6 |
byte_access |
80072 |
1 |
|
|
T1 |
620 |
|
T2 |
12 |
|
T3 |
4 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10881531 |
1 |
|
|
T1 |
46964 |
|
T2 |
4829 |
|
T3 |
3666 |
auto[0] |
triple_byte_access |
40015 |
1 |
|
|
T1 |
310 |
|
T2 |
10 |
|
T3 |
8 |
auto[0] |
halfword_access |
40365 |
1 |
|
|
T1 |
316 |
|
T2 |
5 |
|
T3 |
3 |
auto[0] |
byte_access |
40036 |
1 |
|
|
T1 |
310 |
|
T2 |
6 |
|
T3 |
2 |
auto[1] |
word_access |
10881515 |
1 |
|
|
T1 |
46964 |
|
T2 |
4829 |
|
T3 |
3666 |
auto[1] |
triple_byte_access |
40015 |
1 |
|
|
T1 |
310 |
|
T2 |
10 |
|
T3 |
8 |
auto[1] |
halfword_access |
40365 |
1 |
|
|
T1 |
316 |
|
T2 |
5 |
|
T3 |
3 |
auto[1] |
byte_access |
40036 |
1 |
|
|
T1 |
310 |
|
T2 |
6 |
|
T3 |
2 |