Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 293 1 T137 7 T138 7 T139 7
all_values[1] 293 1 T137 7 T138 7 T139 7
all_values[2] 293 1 T137 7 T138 7 T139 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 488 1 T137 14 T138 11 T139 9
auto[1] 391 1 T137 7 T138 10 T139 12


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 336 1 T137 6 T138 14 T139 10
auto[1] 543 1 T137 15 T138 7 T139 11


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 501 1 T137 11 T138 17 T139 12
auto[1] 378 1 T137 10 T138 4 T139 9


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 64 1 T137 3 T138 3 T139 1
all_values[0] auto[0] auto[0] auto[1] 28 1 T177 2 T178 1 T179 1
all_values[0] auto[0] auto[1] auto[0] 46 1 T137 1 T138 2 T139 2
all_values[0] auto[0] auto[1] auto[1] 29 1 T137 2 T138 1 T177 1
all_values[0] auto[1] auto[0] auto[1] 77 1 T139 2 T172 2 T178 1
all_values[0] auto[1] auto[1] auto[1] 49 1 T137 1 T138 1 T139 2
all_values[1] auto[0] auto[0] auto[0] 62 1 T138 3 T139 1 T177 3
all_values[1] auto[0] auto[0] auto[1] 22 1 T137 2 T138 1 T172 2
all_values[1] auto[0] auto[1] auto[0] 54 1 T138 2 T139 3 T179 4
all_values[1] auto[0] auto[1] auto[1] 28 1 T172 1 T180 2 T181 1
all_values[1] auto[1] auto[0] auto[1] 76 1 T137 5 T139 2 T172 4
all_values[1] auto[1] auto[1] auto[1] 51 1 T138 1 T139 1 T178 2
all_values[2] auto[0] auto[0] auto[0] 53 1 T138 3 T139 1 T172 1
all_values[2] auto[0] auto[0] auto[1] 31 1 T137 1 T172 2 T177 1
all_values[2] auto[0] auto[1] auto[0] 57 1 T137 2 T138 1 T139 2
all_values[2] auto[0] auto[1] auto[1] 27 1 T138 1 T139 2 T177 1
all_values[2] auto[1] auto[0] auto[1] 75 1 T137 3 T138 1 T139 2
all_values[2] auto[1] auto[1] auto[1] 50 1 T137 1 T138 1 T172 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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