Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
99403677 |
1 |
|
|
T3 |
457364 |
|
T7 |
452412 |
|
T8 |
292 |
all_values[1] |
99403677 |
1 |
|
|
T3 |
457364 |
|
T7 |
452412 |
|
T8 |
292 |
all_values[2] |
99403677 |
1 |
|
|
T3 |
457364 |
|
T7 |
452412 |
|
T8 |
292 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
552351 |
1 |
|
|
T3 |
22 |
|
T8 |
7 |
|
T30 |
11231 |
auto[1] |
297658680 |
1 |
|
|
T3 |
137207 |
|
T7 |
135723 |
|
T8 |
869 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
296674605 |
1 |
|
|
T3 |
136192 |
|
T7 |
134713 |
|
T8 |
840 |
auto[1] |
1536426 |
1 |
|
|
T3 |
10167 |
|
T7 |
10098 |
|
T8 |
36 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
12 |
0 |
12 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
173222 |
1 |
|
|
T30 |
5338 |
|
T31 |
1 |
|
T34 |
3111 |
all_values[0] |
auto[0] |
auto[1] |
2063 |
1 |
|
|
T30 |
20 |
|
T31 |
2 |
|
T34 |
16 |
all_values[0] |
auto[1] |
auto[0] |
98718313 |
1 |
|
|
T3 |
453975 |
|
T7 |
449046 |
|
T8 |
280 |
all_values[0] |
auto[1] |
auto[1] |
510079 |
1 |
|
|
T3 |
3389 |
|
T7 |
3366 |
|
T8 |
12 |
all_values[1] |
auto[0] |
auto[0] |
173489 |
1 |
|
|
T3 |
2 |
|
T30 |
5784 |
|
T31 |
1 |
all_values[1] |
auto[0] |
auto[1] |
1575 |
1 |
|
|
T3 |
1 |
|
T30 |
12 |
|
T31 |
2 |
all_values[1] |
auto[1] |
auto[0] |
98718046 |
1 |
|
|
T3 |
453973 |
|
T7 |
449046 |
|
T8 |
280 |
all_values[1] |
auto[1] |
auto[1] |
510567 |
1 |
|
|
T3 |
3388 |
|
T7 |
3366 |
|
T8 |
12 |
all_values[2] |
auto[0] |
auto[0] |
200328 |
1 |
|
|
T3 |
11 |
|
T8 |
6 |
|
T30 |
69 |
all_values[2] |
auto[0] |
auto[1] |
1674 |
1 |
|
|
T3 |
8 |
|
T8 |
1 |
|
T30 |
8 |
all_values[2] |
auto[1] |
auto[0] |
98691207 |
1 |
|
|
T3 |
453964 |
|
T7 |
449046 |
|
T8 |
274 |
all_values[2] |
auto[1] |
auto[1] |
510468 |
1 |
|
|
T3 |
3381 |
|
T7 |
3366 |
|
T8 |
11 |