Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
341208 |
1 |
|
|
T3 |
4530 |
|
T7 |
4530 |
|
T8 |
18 |
auto[1] |
354106 |
1 |
|
|
T30 |
438 |
|
T32 |
230 |
|
T34 |
612 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174430 |
1 |
|
|
T3 |
1087 |
|
T7 |
1108 |
|
T8 |
2 |
lower_val |
172267 |
1 |
|
|
T3 |
1142 |
|
T7 |
1178 |
|
T8 |
8 |
zero_val |
1855 |
1 |
|
|
T3 |
9 |
|
T7 |
7 |
|
T8 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
259068 |
1 |
|
|
T3 |
2294 |
|
T7 |
2312 |
|
T8 |
8 |
lower_val |
259200 |
1 |
|
|
T3 |
2236 |
|
T7 |
2218 |
|
T8 |
10 |
zero_val |
177046 |
1 |
|
|
T30 |
210 |
|
T32 |
102 |
|
T34 |
294 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
42526 |
1 |
|
|
T3 |
567 |
|
T7 |
586 |
|
T8 |
2 |
higher_val |
higher_val |
auto[1] |
22351 |
1 |
|
|
T30 |
29 |
|
T32 |
27 |
|
T34 |
44 |
higher_val |
lower_val |
auto[0] |
42754 |
1 |
|
|
T3 |
520 |
|
T7 |
522 |
|
T30 |
17 |
higher_val |
lower_val |
auto[1] |
22376 |
1 |
|
|
T30 |
25 |
|
T32 |
21 |
|
T34 |
47 |
higher_val |
zero_val |
auto[0] |
83 |
1 |
|
|
T30 |
1 |
|
T34 |
1 |
|
T40 |
1 |
higher_val |
zero_val |
auto[1] |
44340 |
1 |
|
|
T30 |
46 |
|
T32 |
25 |
|
T34 |
78 |
lower_val |
higher_val |
auto[0] |
42230 |
1 |
|
|
T3 |
572 |
|
T7 |
584 |
|
T8 |
1 |
lower_val |
higher_val |
auto[1] |
21956 |
1 |
|
|
T30 |
26 |
|
T32 |
14 |
|
T34 |
36 |
lower_val |
lower_val |
auto[0] |
41989 |
1 |
|
|
T3 |
570 |
|
T7 |
594 |
|
T8 |
7 |
lower_val |
lower_val |
auto[1] |
22130 |
1 |
|
|
T30 |
34 |
|
T32 |
11 |
|
T34 |
23 |
lower_val |
zero_val |
auto[0] |
76 |
1 |
|
|
T34 |
1 |
|
T11 |
1 |
|
T27 |
1 |
lower_val |
zero_val |
auto[1] |
43886 |
1 |
|
|
T30 |
51 |
|
T32 |
19 |
|
T34 |
66 |
zero_val |
higher_val |
auto[0] |
548 |
1 |
|
|
T3 |
4 |
|
T7 |
3 |
|
T30 |
1 |
zero_val |
higher_val |
auto[1] |
138 |
1 |
|
|
T30 |
1 |
|
T34 |
4 |
|
T40 |
2 |
zero_val |
lower_val |
auto[0] |
564 |
1 |
|
|
T3 |
5 |
|
T7 |
4 |
|
T8 |
1 |
zero_val |
lower_val |
auto[1] |
153 |
1 |
|
|
T30 |
3 |
|
T34 |
6 |
|
T9 |
1 |
zero_val |
zero_val |
auto[0] |
257 |
1 |
|
|
T30 |
1 |
|
T47 |
1 |
|
T40 |
1 |
zero_val |
zero_val |
auto[1] |
195 |
1 |
|
|
T30 |
1 |
|
T34 |
2 |
|
T9 |
1 |