Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99403677	1			T3	457364		T7	452412		T8	292
all_pins[1]	99403677	1			T3	457364		T7	452412		T8	292
all_pins[2]	99403677	1			T3	457364		T7	452412		T8	292

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	247085197	1			T3	108672		T7	107367		T8	749
values[0x1]	51125834	1			T3	285364		T7	283563		T8	127
transitions[0x0=>0x1]	50696588	1			T3	283992		T7	282215		T8	115
transitions[0x1=>0x0]	50696610	1			T3	283992		T7	282215		T8	115

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98893598	1			T3	453975		T7	449046		T8	280
all_pins[0]	values[0x1]	510079	1			T3	3389		T7	3366		T8	12
all_pins[0]	transitions[0x0=>0x1]	216565	1			T3	2017		T7	2018		T30	62
all_pins[0]	transitions[0x1=>0x0]	49982227	1			T3	280603		T7	278849		T8	103
all_pins[1]	values[0x0]	49127936	1			T3	175389		T7	172215		T8	177
all_pins[1]	values[0x1]	50275741	1			T3	281975		T7	280197		T8	115
all_pins[1]	transitions[0x0=>0x1]	50142069	1			T3	281975		T7	280197		T8	115
all_pins[1]	transitions[0x1=>0x0]	206342	1			T30	4186		T34	10560		T40	1138
all_pins[2]	values[0x0]	99063663	1			T3	457364		T7	452412		T8	292
all_pins[2]	values[0x1]	340014	1			T30	7186		T34	18207		T40	2059
all_pins[2]	transitions[0x0=>0x1]	337954	1			T30	7148		T34	18078		T40	2044
all_pins[2]	transitions[0x1=>0x0]	508041	1			T3	3389		T7	3366		T8	12