Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	704	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5444	1			T30	43		T34	63		T40	3
len_601_800	12579	1			T30	79		T34	115		T40	31
len_401_600	8284	1			T30	45		T34	70		T40	19
len_201_400	16445	1			T3	251		T7	251		T30	30
len_65_200	74463	1			T3	680		T7	680		T30	21
len_min_for_xof_require_squeeze	1013	1			T3	10		T7	10		T31	9
len_keccak_block_sizes[72]	763	1			T3	5		T7	5		T31	9
len_keccak_block_sizes[104]	765	1			T3	5		T7	5		T31	9
len_keccak_block_sizes[136]	761	1			T3	5		T7	5		T31	9
len_keccak_block_sizes[144]	287	1			T3	5		T7	5		T52	5
len_keccak_block_sizes[168]	279	1			T3	5		T7	5		T52	5
len_datapath_width	14188	1			T3	5		T7	5		T8	3
len_2_63	213964	1			T3	1329		T7	1329		T8	6
len_1	62	1			T87	1		T135	2		T137	1