Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	18	0	18	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	18	0	18	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1			T121	7		T122	7		T123	4
all_values[1]	278	1			T121	7		T122	7		T123	4
all_values[2]	278	1			T121	7		T122	7		T123	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

453

1

T121

13

T122

10

T123

5

auto[1]

381

1

T121

8

T122

11

T123

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

326

1

T121

4

T122

6

T123

4

auto[1]

508

1

T121

17

T122

15

T123

8

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

502

1

T121

10

T122

10

T123

6

auto[1]

332

1

T121

11

T122

11

T123

6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	18	0	18	100.00
Automatically Generated Cross Bins	18	0	18	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

53

1

T122

1

T168

1

T169

2

all_values[0]

auto[0]

auto[0]

auto[1]

24

1

T121

1

T123

1

T168

1

all_values[0]

auto[0]

auto[1]

auto[0]

44

1

T121

1

T123

1

T170

2

all_values[0]

auto[0]

auto[1]

auto[1]

38

1

T121

1

T122

1

T168

1

all_values[0]

auto[1]

auto[0]

auto[1]

72

1

T121

3

T122

4

T123

2

all_values[0]

auto[1]

auto[1]

auto[1]

47

1

T121

1

T122

1

T170

2

all_values[1]

auto[0]

auto[0]

auto[0]

64

1

T121

2

T122

1

T123

1

all_values[1]

auto[0]

auto[0]

auto[1]

39

1

T121

1

T122

1

T170

2

all_values[1]

auto[0]

auto[1]

auto[0]

56

1

T122

2

T168

3

T170

2

all_values[1]

auto[0]

auto[1]

auto[1]

21

1

T123

1

T169

1

T171

1

all_values[1]

auto[1]

auto[0]

auto[1]

62

1

T121

3

T122

3

T168

2

all_values[1]

auto[1]

auto[1]

auto[1]

36

1

T121

1

T123

2

T168

1

all_values[2]

auto[0]

auto[0]

auto[0]

62

1

T168

2

T170

2

T169

2

all_values[2]

auto[0]

auto[0]

auto[1]

17

1

T121

1

T157

1

T172

1

all_values[2]

auto[0]

auto[1]

auto[0]

47

1

T121

1

T122

2

T123

2

all_values[2]

auto[0]

auto[1]

auto[1]

37

1

T121

2

T122

2

T170

1

all_values[2]

auto[1]

auto[0]

auto[1]

60

1

T121

2

T123

1

T168

2

all_values[2]

auto[1]

auto[1]

auto[1]

55

1

T121

1

T122

3

T123

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal